| { |
| "area": 22.3776, |
| "cell_footprint": "sky130_fd_sc_ms__dlclkp", |
| "cell_leakage_power": 45.50191, |
| "clock_gating_integrated_cell": "latch_posedge", |
| "driver_waveform_fall": "ramp", |
| "driver_waveform_rise": "ramp", |
| "leakage_power": [ |
| { |
| "value": 39.0535391, |
| "when": "!GATE&CLK" |
| }, |
| { |
| "value": 42.8326707, |
| "when": "GATE&!CLK" |
| }, |
| { |
| "value": 33.2779813, |
| "when": "GATE&CLK" |
| }, |
| { |
| "value": 45.5019098, |
| "when": "!GATE&!CLK" |
| } |
| ], |
| "pg_pin,VGND": { |
| "pg_type": "primary_ground", |
| "related_bias_pin": "VPB", |
| "voltage_name": "VGND" |
| }, |
| "pg_pin,VNB": { |
| "pg_type": "nwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VNB" |
| }, |
| "pg_pin,VPB": { |
| "pg_type": "pwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VPB" |
| }, |
| "pg_pin,VPWR": { |
| "pg_type": "primary_power", |
| "related_bias_pin": "VNB", |
| "voltage_name": "VPWR" |
| }, |
| "pin,CLK": { |
| "capacitance": 0.01295, |
| "clock": "true", |
| "clock_gate_clock_pin": "true", |
| "direction": "input", |
| "internal_power": { |
| "fall_power,hidden_pwr_template13": { |
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| 0.01, |
| 0.01735, |
| 0.02602, |
| 0.03903, |
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| 0.0572517, |
| 0.0724031, |
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| ] |
| }, |
| "rise_power,hidden_pwr_template13": { |
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| 0.0363216, |
| 0.0516751, |
| 0.0747204 |
| ] |
| } |
| }, |
| "max_transition": 1.0, |
| "min_pulse_width_low": 0.09577, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR" |
| }, |
| "pin,GATE": { |
| "capacitance": 0.00286, |
| "clock": "false", |
| "clock_gate_enable_pin": "true", |
| "direction": "input", |
| "internal_power": { |
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| 0.01735, |
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| ], |
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| 0.0357207, |
| 0.0382914, |
| 0.0435133, |
| 0.0513566, |
| 0.0631323, |
| 0.0808086 |
| ] |
| }, |
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| ], |
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| 0.0266811, |
| 0.0320317, |
| 0.0400694, |
| 0.0521379, |
| 0.0702546 |
| ] |
| } |
| }, |
| "max_transition": 1.0, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
| "timing": [ |
| { |
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| 0.0625, |
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| [ |
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| 0.27502, |
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| [ |
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| [ |
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| 0.37462, |
| 0.40392 |
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| [ |
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| 0.34533, |
| 0.34533, |
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| 0.4215, |
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| 0.3922, |
| 0.40392, |
| 0.4215, |
| 0.44494, |
| 0.46837, |
| 0.49181 |
| ] |
| ] |
| }, |
| "related_pin": "CLK", |
| "rise_constraint,sethold_template_rise10x10": { |
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| 0.03125, |
| 0.0625, |
| 0.125, |
| 0.25, |
| 0.5, |
| 0.75, |
| 1.0, |
| 1.25, |
| 1.5 |
| ], |
| "index_2": [ |
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| 0.03125, |
| 0.0625, |
| 0.125, |
| 0.25, |
| 0.5, |
| 0.75, |
| 1.0, |
| 1.25, |
| 1.5 |
| ], |
| "values": [ |
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| 0.06994, |
| 0.06994, |
| 0.0758, |
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| 0.19298, |
| 0.22814, |
| 0.2633 |
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| [ |
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| [ |
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| [ |
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| 0.1549, |
| 0.19298, |
| 0.22814 |
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| [ |
| 0.02013, |
| 0.0172, |
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| 0.02599, |
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| 0.16955, |
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| [ |
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| [ |
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| 0.00255, |
| 0.04064, |
| 0.08166, |
| 0.11974, |
| 0.16076 |
| ] |
| ] |
| }, |
| "timing_type": "setup_rising" |
| }, |
| { |
| "fall_constraint,sethold_template_fall10x10": { |
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| 0.01, |
| 0.03125, |
| 0.0625, |
| 0.125, |
| 0.25, |
| 0.5, |
| 0.75, |
| 1.0, |
| 1.25, |
| 1.5 |
| ], |
| "index_2": [ |
| 0.01, |
| 0.03125, |
| 0.0625, |
| 0.125, |
| 0.25, |
| 0.5, |
| 0.75, |
| 1.0, |
| 1.25, |
| 1.5 |
| ], |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| -0.33436, |
| -0.3578, |
| -0.38124, |
| -0.40467 |
| ] |
| ] |
| }, |
| "related_pin": "CLK", |
| "rise_constraint,sethold_template_rise10x10": { |
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| 0.01, |
| 0.03125, |
| 0.0625, |
| 0.125, |
| 0.25, |
| 0.5, |
| 0.75, |
| 1.0, |
| 1.25, |
| 1.5 |
| ], |
| "index_2": [ |
| 0.01, |
| 0.03125, |
| 0.0625, |
| 0.125, |
| 0.25, |
| 0.5, |
| 0.75, |
| 1.0, |
| 1.25, |
| 1.5 |
| ], |
| "values": [ |
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| 0.01427, |
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| [ |
| 0.00841, |
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| 0.00548, |
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| [ |
| 0.0172, |
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| [ |
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| [ |
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| [ |
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| [ |
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| -0.07655 |
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| ] |
| }, |
| "timing_type": "hold_rising" |
| } |
| ] |
| }, |
| "pin,GCLK": { |
| "clock_gate_out_pin": "true", |
| "direction": "output", |
| "internal_power": { |
| "fall_power,pwr_template13x11": { |
| "index_1": [ |
| 0.01, |
| 0.01735, |
| 0.02602, |
| 0.03903, |
| 0.05855, |
| 0.08782, |
| 0.13172, |
| 0.19757, |
| 0.29634, |
| 0.44449, |
| 0.6667, |
| 1, |
| 1.5 |
| ], |
| "index_2": [ |
| 0, |
| 0.00667, |
| 0.01001, |
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| 0.11406, |
| 0.17109, |
| 0.25663 |
| ], |
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| [ |
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| 0.01323, |
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| 0.30328, |
| 0.45019, |
| 0.66986, |
| 0.99977, |
| 1.4971 |
| ], |
| [ |
| 0.01325, |
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| 0.06856, |
| 0.097, |
| 0.1401, |
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| 0.30289, |
| 0.44907, |
| 0.66983, |
| 0.99981, |
| 1.49556 |
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| 0.01331, |
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| 0.44926, |
| 0.66981, |
| 1.00159, |
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| [ |
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| 0.30337, |
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| 1.49503 |
| ], |
| [ |
| 0.01447, |
| 0.05087, |
| 0.06935, |
| 0.09743, |
| 0.14024, |
| 0.20511, |
| 0.30291, |
| 0.44978, |
| 0.66989, |
| 0.99925, |
| 1.49443 |
| ], |
| [ |
| 0.0154, |
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| 0.44983, |
| 0.6698, |
| 1.00231, |
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| ], |
| [ |
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| 0.30329, |
| 0.44997, |
| 0.6697, |
| 1.00074, |
| 1.4953 |
| ], |
| [ |
| 0.01869, |
| 0.05559, |
| 0.07335, |
| 0.10048, |
| 0.14255, |
| 0.20664, |
| 0.30341, |
| 0.44964, |
| 0.66899, |
| 0.99874, |
| 1.49525 |
| ], |
| [ |
| 0.02129, |
| 0.05908, |
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| 0.10395, |
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| 0.20882, |
| 0.30515, |
| 0.4511, |
| 0.67146, |
| 1.00051, |
| 1.49686 |
| ], |
| [ |
| 0.02491, |
| 0.06383, |
| 0.08149, |
| 0.10843, |
| 0.15008, |
| 0.21284, |
| 0.30879, |
| 0.45342, |
| 0.67182, |
| 1.00155, |
| 1.4946 |
| ], |
| [ |
| 0.0299, |
| 0.06993, |
| 0.08795, |
| 0.11508, |
| 0.15658, |
| 0.2196, |
| 0.31572, |
| 0.45975, |
| 0.67618, |
| 1.0026, |
| 1.4948 |
| ], |
| [ |
| 0.0367, |
| 0.0782, |
| 0.0967, |
| 0.1242, |
| 0.1654, |
| 0.2291, |
| 0.326, |
| 0.472, |
| 0.6883, |
| 1.0121, |
| 1.5008 |
| ] |
| ] |
| }, |
| "timing_sense": "positive_unate" |
| } |
| }, |
| "pin,M0": { |
| "direction": "internal", |
| "internal_node": "M0", |
| "related_ground_pin": "VNB", |
| "related_power_pin": "VPWR" |
| }, |
| "statetable,CLK GATE,M0": { |
| "table": [ |
| "L L : - : L", |
| "L H : - : H", |
| "H - : - : N" |
| ] |
| } |
| } |
