{
  "area": 49.5504,
  "cell_footprint": "sdfrbp",
  "cell_leakage_power": 0.0,
  "driver_waveform_fall": "ramp",
  "driver_waveform_rise": "ramp",
  "ff IQ,IQ_N": {
    "clear": "!RESET_B",
    "clocked_on": "CLK",
    "next_state": "(D&!SCE) | (SCD&SCE)"
  },
  "pg_pin VGND": {
    "pg_type": "primary_ground",
    "voltage_name": "VGND"
  },
  "pg_pin VNB": {
    "pg_type": "primary_ground",
    "voltage_name": "VNB"
  },
  "pg_pin VPB": {
    "pg_type": "primary_power",
    "voltage_name": "VPB"
  },
  "pg_pin VPWR": {
    "pg_type": "primary_power",
    "voltage_name": "VPWR"
  },
  "pin CLK": {
    "capacitance": 0.003056,
    "clock": "true",
    "direction": "input",
    "fall_capacitance": 0.002899,
    "internal_power": {
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        "values": [
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      "rise_power hidden_pwr_template13": {
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        "values": [
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    "max_transition": 1.0,
    "min_pulse_width_high": 0.111586,
    "min_pulse_width_low": 0.206058,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.003213
  },
  "pin D": {
    "capacitance": 0.001882,
    "clock": "false",
    "direction": "input",
    "fall_capacitance": 0.00179,
    "internal_power": {
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      "rise_power hidden_pwr_template13": {
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        "values": [
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    },
    "max_transition": 1.0,
    "nextstate_type": "data",
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.001974,
    "timing": [
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        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "setup_rising",
        "violation_delay_degrade_pct": 10
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      {
        "fall_constraint vio_10_10_1": {
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        "related_pin": "CLK",
        "rise_constraint vio_10_10_1": {
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        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "hold_rising",
        "violation_delay_degrade_pct": 10
      }
    ]
  },
  "pin Q": {
    "direction": "output",
    "function": "IQ",
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          "index_2": [
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        "related_pin": "RESET_B",
        "rise_power scalar": {
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      {
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        "sim_opt": "runlvl=5 accurate=1",
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      {
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        "fall_constraint vio_10_10_1": {
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        "related_pin": "CLK",
        "rise_constraint vio_10_10_1": {
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        "values": [
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      "rise_power hidden_pwr_template13": {
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        "values": [
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    "max_transition": 1.0,
    "nextstate_type": "scan_enable",
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    "rise_capacitance": 0.004517,
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        "related_pin": "CLK",
        "rise_constraint vio_10_10_1": {
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        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "setup_rising",
        "violation_delay_degrade_pct": 10
      },
      {
        "fall_constraint vio_10_10_1": {
          "index_1": [
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            0.0625,
            0.125,
            0.25,
            0.5,
            0.75,
            1.0,
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            0.125,
            0.25,
            0.5,
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            1.0,
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          "values": [
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              -0.1666523,
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              -0.2179219,
              -0.2793639,
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              -0.3766133,
              -0.4185241,
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            [
              -0.1438822,
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              -0.4142598,
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            [
              -0.1381855,
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              -0.1554707,
              -0.1729674,
              -0.2079609,
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              -0.4110045,
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            [
              -0.1316751,
              -0.1396016,
              -0.1489603,
              -0.1652363,
              -0.2002298,
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              -0.3157897,
              -0.363804,
              -0.4081562,
              -0.4488464
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            [
              -0.1247578,
              -0.1314635,
              -0.1408223,
              -0.158319,
              -0.1933125,
              -0.2584167,
              -0.3113138,
              -0.3605488,
              -0.404901,
              -0.4480325
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            [
              -0.1182474,
              -0.1249531,
              -0.1343119,
              -0.1518086,
              -0.1880228,
              -0.2531269,
              -0.3084655,
              -0.3577005,
              -0.4044941,
              -0.4476256
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            [
              -0.1166198,
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              -0.1863952,
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              -0.3092793,
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            [
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            [
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            [
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              -0.162388,
              -0.1973815,
              -0.2649271,
              -0.322707,
              -0.3743835,
              -0.4211771,
              -0.4679707
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          ]
        },
        "related_pin": "CLK",
        "rise_constraint vio_10_10_1": {
          "index_1": [
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            0.0625,
            0.125,
            0.25,
            0.5,
            0.75,
            1.0,
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            [
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            [
              -0.1040059,
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              -0.2270853,
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            [
              -0.1023783,
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            [
              -0.1040059,
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            [
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            [
              -0.132082,
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              -0.1619811,
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              -0.261265,
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            [
              -0.1438822,
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              -0.3068379,
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            [
              -0.156903,
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              -0.170526,
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        },
        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "hold_rising",
        "violation_delay_degrade_pct": 10
      }
    ]
  },
  "test_cell": {
    "ff IQ,IQ_N": {
      "clear": "!RESET_B",
      "clocked_on": "CLK",
      "next_state": "D"
    },
    "pin CLK": {
      "direction": "input"
    },
    "pin D": {
      "direction": "input"
    },
    "pin Q": {
      "direction": "output",
      "function": "IQ",
      "signal_type": "test_scan_out"
    },
    "pin Q_N": {
      "direction": "output",
      "function": "IQ_N",
      "signal_type": "test_scan_out_inverted"
    },
    "pin RESET_B": {
      "direction": "input"
    },
    "pin SCD": {
      "direction": "input",
      "signal_type": "test_scan_in"
    },
    "pin SCE": {
      "direction": "input",
      "signal_type": "test_scan_enable"
    }
  }
}