| { |
| "area": 38.3616, |
| "cell_footprint": "sky130_fd_sc_ms__dfrbp", |
| "cell_leakage_power": 135.662, |
| "driver_waveform_fall": "ramp", |
| "driver_waveform_rise": "ramp", |
| "ff,IQ,IQ_N": { |
| "clear": "!RESET_B", |
| "clocked_on": "CLK", |
| "next_state": "D" |
| }, |
| "leakage_power": [ |
| { |
| "value": 122.5405271, |
| "when": "D&RESET_B&CLK" |
| }, |
| { |
| "value": 61.2162196, |
| "when": "!D&RESET_B&!CLK" |
| }, |
| { |
| "value": 49.5874524, |
| "when": "!D&!RESET_B&CLK" |
| }, |
| { |
| "value": 117.8020526, |
| "when": "!D&RESET_B&CLK" |
| }, |
| { |
| "value": 135.6620487, |
| "when": "D&RESET_B&!CLK" |
| }, |
| { |
| "value": 51.5565617, |
| "when": "D&!RESET_B&CLK" |
| }, |
| { |
| "value": 55.7631559, |
| "when": "!D&!RESET_B&!CLK" |
| }, |
| { |
| "value": 57.7330077, |
| "when": "D&!RESET_B&!CLK" |
| } |
| ], |
| "pg_pin,VGND": { |
| "pg_type": "primary_ground", |
| "related_bias_pin": "VPB", |
| "voltage_name": "VGND" |
| }, |
| "pg_pin,VNB": { |
| "pg_type": "nwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VNB" |
| }, |
| "pg_pin,VPB": { |
| "pg_type": "pwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VPB" |
| }, |
| "pg_pin,VPWR": { |
| "pg_type": "primary_power", |
| "related_bias_pin": "VNB", |
| "voltage_name": "VPWR" |
| }, |
| "pin,CLK": { |
| "capacitance": 0.002945, |
| "clock": "true", |
| "direction": "input", |
| "fall_capacitance": 0.002786, |
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| 0.01735, |
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| }, |
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| "min_pulse_width_high": 0.067645, |
| "min_pulse_width_low": 0.122571, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
| "rise_capacitance": 0.003103 |
| }, |
| "pin,D": { |
| "capacitance": 0.001929, |
| "clock": "false", |
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| "fall_capacitance": 0.001894, |
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| }, |
| "max_transition": 1.0, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
| "rise_capacitance": 0.001963, |
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| ] |
| }, |
| "related_pin": "CLK", |
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| }, |
| "sim_opt": "runlvl=5 accurate=1", |
| "timing_type": "setup_rising", |
| "violation_delay_degrade_pct": 10 |
| }, |
| { |
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| }, |
| "related_pin": "CLK", |
| "rise_constraint,vio_10_10_1": { |
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| ] |
| }, |
| "sim_opt": "runlvl=5 accurate=1", |
| "timing_type": "hold_rising", |
| "violation_delay_degrade_pct": 10 |
| } |
| ] |
| }, |
| "pin,Q": { |
| "direction": "output", |
| "function": "IQ", |
| "internal_power": [ |
| { |
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