tree 685f06739e8cb3749b7e245980d9bfa1f1cb0e96
parent d94c22085c9411f6e0643fbdcb97371de90c8238
parent c3d24b3b50d46c552c712cc770f48ffbbc0bd07f
author Tim 'mithro' Ansell <me@mith.ro> 1601658062 -0700
committer Tim 'mithro' Ansell <tansell@google.com> 1601658062 -0700

verilog: Fixing usage of cell reserved word.

`cell` is a Verilog reserved word.

Signed-off-by: Tim 'mithro' Ansell <tansell@google.com>