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| "related_pin": "CLK", |
| "rise_constraint,vio_10_10_1": { |
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| { |
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| "related_output_pin": "Q", |
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| "sim_opt": "runlvl=5 accurate=1", |
| "timing_type": "min_pulse_width", |
| "violation_delay_degrade_pct": 10 |
| } |
| ] |
| } |
| } |
