)]}'
{
  "commit": "fd4c4436958103d29fe1d12a5001a2cebfbbc582",
  "tree": "1868e77958d50c4e298ba9c9be5bc8dc11b84d77",
  "parents": [
    "fe214d2aa221ec93ca3edefec68464cb51c406c6",
    "8530db93614fd4feda9e46aef13d5427b9e56a4d"
  ],
  "author": {
    "name": "Tim \u0027mithro\u0027 Ansell",
    "email": "me@mith.ro",
    "time": "Fri Oct 02 10:01:02 2020 -0700"
  },
  "committer": {
    "name": "Tim \u0027mithro\u0027 Ansell",
    "email": "tansell@google.com",
    "time": "Fri Oct 02 10:01:02 2020 -0700"
  },
  "message": "verilog: Fixing usage of cell reserved word.\n\n`cell` is a Verilog reserved word.\n\nSigned-off-by: Tim \u0027mithro\u0027 Ansell \u003ctansell@google.com\u003e\n",
  "tree_diff": []
}