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foss-eda-tools / skywater-pdk / libs / sky130_fd_sc_ls / refs/heads/new-spice / . / cells / dlclkp / sky130_fd_sc_ls__dlclkp_2__ss_n40C_1v60_ccsnoise.lib.json
blob: 8c9ab8dfc3aa7b5d8a69fedf80389ee1dc9b5d96 [file] [log] [blame]
{
"area": 25.5744,
"cell_footprint": "sky130_fd_sc_ls__dlclkp",
"cell_leakage_power": 0.03038487,
"clock_gating_integrated_cell": "latch_posedge",
"driver_waveform_fall": "ramp",
"driver_waveform_rise": "ramp",
"leakage_power": [
{
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"when": "!GATE&CLK"
},
{
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"when": "GATE&!CLK"
},
{
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},
{
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}
],
"pg_pin,VGND": {
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"related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
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"physical_connection": "device_layer",
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},
"pg_pin,VPB": {
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},
"pg_pin,VPWR": {
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"related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
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