| { |
| "area": 25.5744, |
| "cell_footprint": "sky130_fd_sc_ls__dlclkp", |
| "cell_leakage_power": 0.02844299, |
| "clock_gating_integrated_cell": "latch_posedge", |
| "driver_waveform_fall": "ramp", |
| "driver_waveform_rise": "ramp", |
| "leakage_power": [ |
| { |
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| "when": "!GATE&!CLK" |
| }, |
| { |
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| }, |
| { |
| "value": 0.0302632, |
| "when": "GATE&!CLK" |
| }, |
| { |
| "value": 0.0291454, |
| "when": "GATE&CLK" |
| } |
| ], |
| "pg_pin,VGND": { |
| "pg_type": "primary_ground", |
| "related_bias_pin": "VPB", |
| "voltage_name": "VGND" |
| }, |
| "pg_pin,VNB": { |
| "pg_type": "nwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VNB" |
| }, |
| "pg_pin,VPB": { |
| "pg_type": "pwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VPB" |
| }, |
| "pg_pin,VPWR": { |
| "pg_type": "primary_power", |
| "related_bias_pin": "VNB", |
| "voltage_name": "VPWR" |
| }, |
| "pin,CLK": { |
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| "clock": "true", |
| "clock_gate_clock_pin": "true", |
| "direction": "input", |
| "fall_capacitance": 0.004197, |
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| }, |
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| "related_power_pin": "VPWR", |
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| }, |
| "pin,GATE": { |
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| "clock": "false", |
| "clock_gate_enable_pin": "true", |
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| }, |
| "related_pin": "CLK", |
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| "violation_delay_degrade_pct": 10 |
| }, |
| { |
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| }, |
| "sim_opt": "runlvl=5 accurate=1", |
| "timing_type": "hold_rising", |
| "violation_delay_degrade_pct": 10 |
| } |
| ] |
| }, |
| "pin,GCLK": { |
| "clock_gate_out_pin": "true", |
| "direction": "output", |
| "internal_power": { |
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| 0.0612939, |
| 0.0837091, |
| 0.1178437, |
| 0.1701239, |
| 0.2496907, |
| 0.3670378, |
| 0.5442081, |
| 0.8089812 |
| ], |
| [ |
| 0.0194471, |
| 0.0623072, |
| 0.08451, |
| 0.1186807, |
| 0.1706411, |
| 0.2492216, |
| 0.3679836, |
| 0.5458164, |
| 0.8095254 |
| ], |
| [ |
| 0.0219379, |
| 0.0637937, |
| 0.0855648, |
| 0.1193445, |
| 0.1709159, |
| 0.2492125, |
| 0.3679881, |
| 0.5446615, |
| 0.8096488 |
| ], |
| [ |
| 0.025977, |
| 0.066414, |
| 0.0872986, |
| 0.1205162, |
| 0.1716772, |
| 0.2506408, |
| 0.3666303, |
| 0.5442305, |
| 0.8086614 |
| ], |
| [ |
| 0.0315918, |
| 0.0706191, |
| 0.0906815, |
| 0.1230072, |
| 0.1728823, |
| 0.2514528, |
| 0.370368, |
| 0.543578, |
| 0.8076935 |
| ], |
| [ |
| 0.0394863, |
| 0.0778993, |
| 0.0967907, |
| 0.1269636, |
| 0.1756842, |
| 0.2524227, |
| 0.369435, |
| 0.5436719, |
| 0.8090948 |
| ], |
| [ |
| 0.0501636, |
| 0.0904784, |
| 0.1076916, |
| 0.1357889, |
| 0.180645, |
| 0.2544062, |
| 0.369309, |
| 0.5465781, |
| 0.8103762 |
| ], |
| [ |
| 0.0646162, |
| 0.1089887, |
| 0.1260015, |
| 0.1504392, |
| 0.1920002, |
| 0.2608747, |
| 0.3730229, |
| 0.5480794, |
| 0.8122921 |
| ], |
| [ |
| 0.0840429, |
| 0.1352627, |
| 0.1532581, |
| 0.1782553, |
| 0.2149495, |
| 0.2769307, |
| 0.3824963, |
| 0.5502977, |
| 0.8117148 |
| ] |
| ] |
| }, |
| "timing_sense": "positive_unate" |
| } |
| }, |
| "pin,M0": { |
| "direction": "internal", |
| "internal_node": "M0", |
| "related_ground_pin": "VNB", |
| "related_power_pin": "VPWR" |
| }, |
| "statetable,CLK GATE,M0": { |
| "table": [ |
| "L L : - : L", |
| "L H : - : H", |
| "H - : - : N" |
| ] |
| } |
| } |
