Updates to spice, PEX and PXI files as well as the addition of lvs reports
diff --git a/cells/a2111o/sky130_fd_sc_ls__a2111o_1.lvs.report b/cells/a2111o/sky130_fd_sc_ls__a2111o_1.lvs.report
new file mode 100644
index 0000000..d9e4221
--- /dev/null
+++ b/cells/a2111o/sky130_fd_sc_ls__a2111o_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__a2111o_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__a2111o_1.sp ('sky130_fd_sc_ls__a2111o_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/a2111o/sky130_fd_sc_ls__a2111o_1.spice ('sky130_fd_sc_ls__a2111o_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:46:32 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__a2111o_1 sky130_fd_sc_ls__a2111o_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__a2111o_1
+SOURCE CELL NAME: sky130_fd_sc_ls__a2111o_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 15 15
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 11 11
+
+ Instances: 4 4 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SPMP_2_1_1_1 (7 pins)
+ ------ ------
+ Total Inst: 7 7
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 4 4 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SPMP_2_1_1_1
+ ------- ------- --------- ---------
+ Total Inst: 7 7 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1 A2 B1 C1 D1 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a2111o/sky130_fd_sc_ls__a2111o_1.pex.spice b/cells/a2111o/sky130_fd_sc_ls__a2111o_1.pex.spice
index c899f98..72907cf 100644
--- a/cells/a2111o/sky130_fd_sc_ls__a2111o_1.pex.spice
+++ b/cells/a2111o/sky130_fd_sc_ls__a2111o_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a2111o_1.pex.spice
-* Created: Fri Aug 28 12:47:11 2020
+* Created: Wed Sep 2 10:46:34 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a2111o/sky130_fd_sc_ls__a2111o_1.pxi.spice b/cells/a2111o/sky130_fd_sc_ls__a2111o_1.pxi.spice
index bdce060..7d65030 100644
--- a/cells/a2111o/sky130_fd_sc_ls__a2111o_1.pxi.spice
+++ b/cells/a2111o/sky130_fd_sc_ls__a2111o_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a2111o_1.pxi.spice
-* Created: Fri Aug 28 12:47:11 2020
+* Created: Wed Sep 2 10:46:34 2020
*
x_PM_SKY130_FD_SC_LS__A2111O_1%A1 N_A1_c_74_n N_A1_c_75_n N_A1_c_81_n
+ N_A1_M1009_g N_A1_M1001_g A1 A1 N_A1_c_77_n N_A1_c_78_n N_A1_c_79_n
diff --git a/cells/a2111o/sky130_fd_sc_ls__a2111o_1.spice b/cells/a2111o/sky130_fd_sc_ls__a2111o_1.spice
index 92b3c2e..d9e3acd 100644
--- a/cells/a2111o/sky130_fd_sc_ls__a2111o_1.spice
+++ b/cells/a2111o/sky130_fd_sc_ls__a2111o_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a2111o_1.spice
-* Created: Fri Aug 28 12:47:11 2020
+* Created: Wed Sep 2 10:46:34 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a2111o/sky130_fd_sc_ls__a2111o_2.lvs.report b/cells/a2111o/sky130_fd_sc_ls__a2111o_2.lvs.report
new file mode 100644
index 0000000..acd1c0c
--- /dev/null
+++ b/cells/a2111o/sky130_fd_sc_ls__a2111o_2.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__a2111o_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__a2111o_2.sp ('sky130_fd_sc_ls__a2111o_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/a2111o/sky130_fd_sc_ls__a2111o_2.spice ('sky130_fd_sc_ls__a2111o_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:46:38 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__a2111o_2 sky130_fd_sc_ls__a2111o_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__a2111o_2
+SOURCE CELL NAME: sky130_fd_sc_ls__a2111o_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 15 15
+
+ Instances: 7 7 MN (4 pins)
+ 7 7 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 15 14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 11 11
+
+ Instances: 4 4 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SPMP_2_1_1_1 (7 pins)
+ ------ ------
+ Total Inst: 7 7
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 4 4 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SPMP_2_1_1_1
+ ------- ------- --------- ---------
+ Total Inst: 7 7 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D1 C1 B1 A2 A1 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a2111o/sky130_fd_sc_ls__a2111o_2.pex.spice b/cells/a2111o/sky130_fd_sc_ls__a2111o_2.pex.spice
index 9c33c65..3b14598 100644
--- a/cells/a2111o/sky130_fd_sc_ls__a2111o_2.pex.spice
+++ b/cells/a2111o/sky130_fd_sc_ls__a2111o_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a2111o_2.pex.spice
-* Created: Fri Aug 28 12:47:31 2020
+* Created: Wed Sep 2 10:46:40 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a2111o/sky130_fd_sc_ls__a2111o_2.pxi.spice b/cells/a2111o/sky130_fd_sc_ls__a2111o_2.pxi.spice
index d534317..4e5118c 100644
--- a/cells/a2111o/sky130_fd_sc_ls__a2111o_2.pxi.spice
+++ b/cells/a2111o/sky130_fd_sc_ls__a2111o_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a2111o_2.pxi.spice
-* Created: Fri Aug 28 12:47:31 2020
+* Created: Wed Sep 2 10:46:40 2020
*
x_PM_SKY130_FD_SC_LS__A2111O_2%A_91_244# N_A_91_244#_M1013_s N_A_91_244#_M1004_d
+ N_A_91_244#_M1008_d N_A_91_244#_M1002_s N_A_91_244#_c_94_n N_A_91_244#_M1009_g
diff --git a/cells/a2111o/sky130_fd_sc_ls__a2111o_2.spice b/cells/a2111o/sky130_fd_sc_ls__a2111o_2.spice
index 16d6129..97f91e8 100644
--- a/cells/a2111o/sky130_fd_sc_ls__a2111o_2.spice
+++ b/cells/a2111o/sky130_fd_sc_ls__a2111o_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a2111o_2.spice
-* Created: Fri Aug 28 12:47:31 2020
+* Created: Wed Sep 2 10:46:40 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a2111o/sky130_fd_sc_ls__a2111o_4.lvs.report b/cells/a2111o/sky130_fd_sc_ls__a2111o_4.lvs.report
new file mode 100644
index 0000000..192e4e8
--- /dev/null
+++ b/cells/a2111o/sky130_fd_sc_ls__a2111o_4.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__a2111o_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__a2111o_4.sp ('sky130_fd_sc_ls__a2111o_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/a2111o/sky130_fd_sc_ls__a2111o_4.spice ('sky130_fd_sc_ls__a2111o_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:46:44 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__a2111o_4 sky130_fd_sc_ls__a2111o_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__a2111o_4
+SOURCE CELL NAME: sky130_fd_sc_ls__a2111o_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 15 15
+
+ Instances: 14 14 MN (4 pins)
+ 14 14 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 29 28
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 11 11
+
+ Instances: 4 4 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SPMP_2_1_1_1 (7 pins)
+ ------ ------
+ Total Inst: 7 7
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 4 4 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SPMP_2_1_1_1
+ ------- ------- --------- ---------
+ Total Inst: 7 7 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 28 layout mos transistors were reduced to 12.
+ 16 mos transistors were deleted by parallel reduction.
+ 28 source mos transistors were reduced to 12.
+ 16 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D1 C1 B1 A1 A2 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a2111o/sky130_fd_sc_ls__a2111o_4.pex.spice b/cells/a2111o/sky130_fd_sc_ls__a2111o_4.pex.spice
index faf3965..1b427ed 100644
--- a/cells/a2111o/sky130_fd_sc_ls__a2111o_4.pex.spice
+++ b/cells/a2111o/sky130_fd_sc_ls__a2111o_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a2111o_4.pex.spice
-* Created: Fri Aug 28 12:47:51 2020
+* Created: Wed Sep 2 10:46:47 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a2111o/sky130_fd_sc_ls__a2111o_4.pxi.spice b/cells/a2111o/sky130_fd_sc_ls__a2111o_4.pxi.spice
index 399438f..c5bd887 100644
--- a/cells/a2111o/sky130_fd_sc_ls__a2111o_4.pxi.spice
+++ b/cells/a2111o/sky130_fd_sc_ls__a2111o_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a2111o_4.pxi.spice
-* Created: Fri Aug 28 12:47:51 2020
+* Created: Wed Sep 2 10:46:47 2020
*
x_PM_SKY130_FD_SC_LS__A2111O_4%A_137_260# N_A_137_260#_M1013_d
+ N_A_137_260#_M1003_s N_A_137_260#_M1008_s N_A_137_260#_M1015_s
diff --git a/cells/a2111o/sky130_fd_sc_ls__a2111o_4.spice b/cells/a2111o/sky130_fd_sc_ls__a2111o_4.spice
index 4a9156e..4e7c262 100644
--- a/cells/a2111o/sky130_fd_sc_ls__a2111o_4.spice
+++ b/cells/a2111o/sky130_fd_sc_ls__a2111o_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a2111o_4.spice
-* Created: Fri Aug 28 12:47:51 2020
+* Created: Wed Sep 2 10:46:47 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a2111oi/sky130_fd_sc_ls__a2111oi_1.lvs.report b/cells/a2111oi/sky130_fd_sc_ls__a2111oi_1.lvs.report
new file mode 100644
index 0000000..c7383ed
--- /dev/null
+++ b/cells/a2111oi/sky130_fd_sc_ls__a2111oi_1.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__a2111oi_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__a2111oi_1.sp ('sky130_fd_sc_ls__a2111oi_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/a2111oi/sky130_fd_sc_ls__a2111oi_1.spice ('sky130_fd_sc_ls__a2111oi_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:46:50 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__a2111oi_1 sky130_fd_sc_ls__a2111oi_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__a2111oi_1
+SOURCE CELL NAME: sky130_fd_sc_ls__a2111oi_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 14 14
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 10 10
+
+ Instances: 3 3 MN (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SPMP_2_1_1_1 (7 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 3 3 0 0 MN(NSHORT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SPMP_2_1_1_1
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D1 C1 B1 A1 A2 Y VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a2111oi/sky130_fd_sc_ls__a2111oi_1.pex.spice b/cells/a2111oi/sky130_fd_sc_ls__a2111oi_1.pex.spice
index ac5eb06..ee8e9f2 100644
--- a/cells/a2111oi/sky130_fd_sc_ls__a2111oi_1.pex.spice
+++ b/cells/a2111oi/sky130_fd_sc_ls__a2111oi_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a2111oi_1.pex.spice
-* Created: Fri Aug 28 12:48:11 2020
+* Created: Wed Sep 2 10:46:53 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a2111oi/sky130_fd_sc_ls__a2111oi_1.pxi.spice b/cells/a2111oi/sky130_fd_sc_ls__a2111oi_1.pxi.spice
index bb61bb0..e35e866 100644
--- a/cells/a2111oi/sky130_fd_sc_ls__a2111oi_1.pxi.spice
+++ b/cells/a2111oi/sky130_fd_sc_ls__a2111oi_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a2111oi_1.pxi.spice
-* Created: Fri Aug 28 12:48:11 2020
+* Created: Wed Sep 2 10:46:53 2020
*
x_PM_SKY130_FD_SC_LS__A2111OI_1%D1 N_D1_c_54_n N_D1_M1007_g N_D1_M1003_g D1
+ N_D1_c_56_n PM_SKY130_FD_SC_LS__A2111OI_1%D1
diff --git a/cells/a2111oi/sky130_fd_sc_ls__a2111oi_1.spice b/cells/a2111oi/sky130_fd_sc_ls__a2111oi_1.spice
index 2c1cde0..ecf346f 100644
--- a/cells/a2111oi/sky130_fd_sc_ls__a2111oi_1.spice
+++ b/cells/a2111oi/sky130_fd_sc_ls__a2111oi_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a2111oi_1.spice
-* Created: Fri Aug 28 12:48:11 2020
+* Created: Wed Sep 2 10:46:53 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a2111oi/sky130_fd_sc_ls__a2111oi_2.lvs.report b/cells/a2111oi/sky130_fd_sc_ls__a2111oi_2.lvs.report
new file mode 100644
index 0000000..2cfeca0
--- /dev/null
+++ b/cells/a2111oi/sky130_fd_sc_ls__a2111oi_2.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__a2111oi_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__a2111oi_2.sp ('sky130_fd_sc_ls__a2111oi_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/a2111oi/sky130_fd_sc_ls__a2111oi_2.spice ('sky130_fd_sc_ls__a2111oi_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:46:57 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__a2111oi_2 sky130_fd_sc_ls__a2111oi_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__a2111oi_2
+SOURCE CELL NAME: sky130_fd_sc_ls__a2111oi_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 14 14
+
+ Instances: 7 7 MN (4 pins)
+ 10 10 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 18 17
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 10 10
+
+ Instances: 3 3 MN (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SPMP_2_1_1_1 (7 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 3 3 0 0 MN(NSHORT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SPMP_2_1_1_1
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 14 layout mos transistors were reduced to 7.
+ 7 mos transistors were deleted by parallel reduction.
+ 14 source mos transistors were reduced to 7.
+ 7 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D1 C1 B1 A1 A2 Y VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a2111oi/sky130_fd_sc_ls__a2111oi_2.pex.spice b/cells/a2111oi/sky130_fd_sc_ls__a2111oi_2.pex.spice
index 4bb0969..34e9735 100644
--- a/cells/a2111oi/sky130_fd_sc_ls__a2111oi_2.pex.spice
+++ b/cells/a2111oi/sky130_fd_sc_ls__a2111oi_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a2111oi_2.pex.spice
-* Created: Fri Aug 28 12:48:27 2020
+* Created: Wed Sep 2 10:46:59 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a2111oi/sky130_fd_sc_ls__a2111oi_2.pxi.spice b/cells/a2111oi/sky130_fd_sc_ls__a2111oi_2.pxi.spice
index 3639a3f..80d833c 100644
--- a/cells/a2111oi/sky130_fd_sc_ls__a2111oi_2.pxi.spice
+++ b/cells/a2111oi/sky130_fd_sc_ls__a2111oi_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a2111oi_2.pxi.spice
-* Created: Fri Aug 28 12:48:27 2020
+* Created: Wed Sep 2 10:46:59 2020
*
x_PM_SKY130_FD_SC_LS__A2111OI_2%D1 N_D1_c_92_n N_D1_M1002_g N_D1_M1009_g
+ N_D1_c_93_n N_D1_M1016_g D1 D1 N_D1_c_91_n PM_SKY130_FD_SC_LS__A2111OI_2%D1
diff --git a/cells/a2111oi/sky130_fd_sc_ls__a2111oi_2.spice b/cells/a2111oi/sky130_fd_sc_ls__a2111oi_2.spice
index fc5ced9..ee9500d 100644
--- a/cells/a2111oi/sky130_fd_sc_ls__a2111oi_2.spice
+++ b/cells/a2111oi/sky130_fd_sc_ls__a2111oi_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a2111oi_2.spice
-* Created: Fri Aug 28 12:48:27 2020
+* Created: Wed Sep 2 10:46:59 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a2111oi/sky130_fd_sc_ls__a2111oi_4.lvs.report b/cells/a2111oi/sky130_fd_sc_ls__a2111oi_4.lvs.report
new file mode 100644
index 0000000..0ea876c
--- /dev/null
+++ b/cells/a2111oi/sky130_fd_sc_ls__a2111oi_4.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__a2111oi_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__a2111oi_4.sp ('sky130_fd_sc_ls__a2111oi_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/a2111oi/sky130_fd_sc_ls__a2111oi_4.spice ('sky130_fd_sc_ls__a2111oi_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:47:03 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__a2111oi_4 sky130_fd_sc_ls__a2111oi_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__a2111oi_4
+SOURCE CELL NAME: sky130_fd_sc_ls__a2111oi_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 14 14
+
+ Instances: 14 14 MN (4 pins)
+ 20 20 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 35 34
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 10 10
+
+ Instances: 3 3 MN (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SPMP_2_1_1_1 (7 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 3 3 0 0 MN(NSHORT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SPMP_2_1_1_1
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 34 layout mos transistors were reduced to 10.
+ 24 mos transistors were deleted by parallel reduction.
+ 34 source mos transistors were reduced to 10.
+ 24 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D1 C1 B1 A1 A2 Y VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a2111oi/sky130_fd_sc_ls__a2111oi_4.pex.spice b/cells/a2111oi/sky130_fd_sc_ls__a2111oi_4.pex.spice
index 0b34a7d..a064872 100644
--- a/cells/a2111oi/sky130_fd_sc_ls__a2111oi_4.pex.spice
+++ b/cells/a2111oi/sky130_fd_sc_ls__a2111oi_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a2111oi_4.pex.spice
-* Created: Fri Aug 28 12:48:46 2020
+* Created: Wed Sep 2 10:47:06 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a2111oi/sky130_fd_sc_ls__a2111oi_4.pxi.spice b/cells/a2111oi/sky130_fd_sc_ls__a2111oi_4.pxi.spice
index 2952cb0..83b4067 100644
--- a/cells/a2111oi/sky130_fd_sc_ls__a2111oi_4.pxi.spice
+++ b/cells/a2111oi/sky130_fd_sc_ls__a2111oi_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a2111oi_4.pxi.spice
-* Created: Fri Aug 28 12:48:46 2020
+* Created: Wed Sep 2 10:47:06 2020
*
x_PM_SKY130_FD_SC_LS__A2111OI_4%D1 N_D1_c_140_n N_D1_M1000_g N_D1_c_141_n
+ N_D1_M1006_g N_D1_c_142_n N_D1_M1024_g N_D1_c_136_n N_D1_M1013_g N_D1_c_137_n
diff --git a/cells/a2111oi/sky130_fd_sc_ls__a2111oi_4.spice b/cells/a2111oi/sky130_fd_sc_ls__a2111oi_4.spice
index 7e330cc..f818f5e 100644
--- a/cells/a2111oi/sky130_fd_sc_ls__a2111oi_4.spice
+++ b/cells/a2111oi/sky130_fd_sc_ls__a2111oi_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a2111oi_4.spice
-* Created: Fri Aug 28 12:48:46 2020
+* Created: Wed Sep 2 10:47:06 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a211o/sky130_fd_sc_ls__a211o_1.lvs.report b/cells/a211o/sky130_fd_sc_ls__a211o_1.lvs.report
new file mode 100644
index 0000000..58b0c8c
--- /dev/null
+++ b/cells/a211o/sky130_fd_sc_ls__a211o_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__a211o_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__a211o_1.sp ('sky130_fd_sc_ls__a211o_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/a211o/sky130_fd_sc_ls__a211o_1.spice ('sky130_fd_sc_ls__a211o_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:47:10 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__a211o_1 sky130_fd_sc_ls__a211o_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__a211o_1
+SOURCE CELL NAME: sky130_fd_sc_ls__a211o_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 3 3 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SPMP_2_1_1 (6 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 3 3 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SPMP_2_1_1
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A2 A1 B1 C1 X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a211o/sky130_fd_sc_ls__a211o_1.pex.spice b/cells/a211o/sky130_fd_sc_ls__a211o_1.pex.spice
index 58e76d3..4a8169d 100644
--- a/cells/a211o/sky130_fd_sc_ls__a211o_1.pex.spice
+++ b/cells/a211o/sky130_fd_sc_ls__a211o_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a211o_1.pex.spice
-* Created: Fri Aug 28 12:48:55 2020
+* Created: Wed Sep 2 10:47:13 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a211o/sky130_fd_sc_ls__a211o_1.pxi.spice b/cells/a211o/sky130_fd_sc_ls__a211o_1.pxi.spice
index 915ef23..21b3a5b 100644
--- a/cells/a211o/sky130_fd_sc_ls__a211o_1.pxi.spice
+++ b/cells/a211o/sky130_fd_sc_ls__a211o_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a211o_1.pxi.spice
-* Created: Fri Aug 28 12:48:55 2020
+* Created: Wed Sep 2 10:47:13 2020
*
x_PM_SKY130_FD_SC_LS__A211O_1%A_81_264# N_A_81_264#_M1008_d N_A_81_264#_M1006_d
+ N_A_81_264#_M1003_d N_A_81_264#_c_71_n N_A_81_264#_M1009_g N_A_81_264#_M1001_g
diff --git a/cells/a211o/sky130_fd_sc_ls__a211o_1.spice b/cells/a211o/sky130_fd_sc_ls__a211o_1.spice
index 63efbf4..d5e4337 100644
--- a/cells/a211o/sky130_fd_sc_ls__a211o_1.spice
+++ b/cells/a211o/sky130_fd_sc_ls__a211o_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a211o_1.spice
-* Created: Fri Aug 28 12:48:55 2020
+* Created: Wed Sep 2 10:47:13 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a211o/sky130_fd_sc_ls__a211o_2.lvs.report b/cells/a211o/sky130_fd_sc_ls__a211o_2.lvs.report
new file mode 100644
index 0000000..a71841f
--- /dev/null
+++ b/cells/a211o/sky130_fd_sc_ls__a211o_2.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__a211o_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__a211o_2.sp ('sky130_fd_sc_ls__a211o_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/a211o/sky130_fd_sc_ls__a211o_2.spice ('sky130_fd_sc_ls__a211o_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:47:16 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__a211o_2 sky130_fd_sc_ls__a211o_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__a211o_2
+SOURCE CELL NAME: sky130_fd_sc_ls__a211o_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 3 3 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SPMP_2_1_1 (6 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 3 3 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SPMP_2_1_1
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A2 A1 B1 C1 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a211o/sky130_fd_sc_ls__a211o_2.pex.spice b/cells/a211o/sky130_fd_sc_ls__a211o_2.pex.spice
index 220e4dd..0ef3a92 100644
--- a/cells/a211o/sky130_fd_sc_ls__a211o_2.pex.spice
+++ b/cells/a211o/sky130_fd_sc_ls__a211o_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a211o_2.pex.spice
-* Created: Fri Aug 28 12:49:04 2020
+* Created: Wed Sep 2 10:47:19 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a211o/sky130_fd_sc_ls__a211o_2.pxi.spice b/cells/a211o/sky130_fd_sc_ls__a211o_2.pxi.spice
index fe6ff17..f1369fd 100644
--- a/cells/a211o/sky130_fd_sc_ls__a211o_2.pxi.spice
+++ b/cells/a211o/sky130_fd_sc_ls__a211o_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a211o_2.pxi.spice
-* Created: Fri Aug 28 12:49:04 2020
+* Created: Wed Sep 2 10:47:19 2020
*
x_PM_SKY130_FD_SC_LS__A211O_2%A_85_270# N_A_85_270#_M1011_d N_A_85_270#_M1009_d
+ N_A_85_270#_M1000_d N_A_85_270#_c_75_n N_A_85_270#_c_84_n N_A_85_270#_M1004_g
diff --git a/cells/a211o/sky130_fd_sc_ls__a211o_2.spice b/cells/a211o/sky130_fd_sc_ls__a211o_2.spice
index 82c4494..5aaacda 100644
--- a/cells/a211o/sky130_fd_sc_ls__a211o_2.spice
+++ b/cells/a211o/sky130_fd_sc_ls__a211o_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a211o_2.spice
-* Created: Fri Aug 28 12:49:04 2020
+* Created: Wed Sep 2 10:47:19 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a211o/sky130_fd_sc_ls__a211o_4.lvs.report b/cells/a211o/sky130_fd_sc_ls__a211o_4.lvs.report
new file mode 100644
index 0000000..d910148
--- /dev/null
+++ b/cells/a211o/sky130_fd_sc_ls__a211o_4.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__a211o_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__a211o_4.sp ('sky130_fd_sc_ls__a211o_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/a211o/sky130_fd_sc_ls__a211o_4.spice ('sky130_fd_sc_ls__a211o_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:47:23 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__a211o_4 sky130_fd_sc_ls__a211o_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__a211o_4
+SOURCE CELL NAME: sky130_fd_sc_ls__a211o_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 12 12 MN (4 pins)
+ 12 12 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 25 24
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 3 3 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SPMP_2_1_1 (6 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 3 3 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SPMP_2_1_1
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 24 layout mos transistors were reduced to 10.
+ 14 mos transistors were deleted by parallel reduction.
+ 24 source mos transistors were reduced to 10.
+ 14 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1 C1 A1 A2 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a211o/sky130_fd_sc_ls__a211o_4.pex.spice b/cells/a211o/sky130_fd_sc_ls__a211o_4.pex.spice
index 6adccc4..85d24cb 100644
--- a/cells/a211o/sky130_fd_sc_ls__a211o_4.pex.spice
+++ b/cells/a211o/sky130_fd_sc_ls__a211o_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a211o_4.pex.spice
-* Created: Fri Aug 28 12:49:13 2020
+* Created: Wed Sep 2 10:47:26 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a211o/sky130_fd_sc_ls__a211o_4.pxi.spice b/cells/a211o/sky130_fd_sc_ls__a211o_4.pxi.spice
index 218697a..1aec779 100644
--- a/cells/a211o/sky130_fd_sc_ls__a211o_4.pxi.spice
+++ b/cells/a211o/sky130_fd_sc_ls__a211o_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a211o_4.pxi.spice
-* Created: Fri Aug 28 12:49:13 2020
+* Created: Wed Sep 2 10:47:26 2020
*
x_PM_SKY130_FD_SC_LS__A211O_4%A_105_280# N_A_105_280#_M1005_d
+ N_A_105_280#_M1021_s N_A_105_280#_M1002_d N_A_105_280#_M1004_d
diff --git a/cells/a211o/sky130_fd_sc_ls__a211o_4.spice b/cells/a211o/sky130_fd_sc_ls__a211o_4.spice
index 1ee363f..91a1fcb 100644
--- a/cells/a211o/sky130_fd_sc_ls__a211o_4.spice
+++ b/cells/a211o/sky130_fd_sc_ls__a211o_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a211o_4.spice
-* Created: Fri Aug 28 12:49:13 2020
+* Created: Wed Sep 2 10:47:26 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a211oi/sky130_fd_sc_ls__a211oi_1.lvs.report b/cells/a211oi/sky130_fd_sc_ls__a211oi_1.lvs.report
new file mode 100644
index 0000000..c610250
--- /dev/null
+++ b/cells/a211oi/sky130_fd_sc_ls__a211oi_1.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__a211oi_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__a211oi_1.sp ('sky130_fd_sc_ls__a211oi_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/a211oi/sky130_fd_sc_ls__a211oi_1.spice ('sky130_fd_sc_ls__a211oi_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:47:30 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__a211oi_1 sky130_fd_sc_ls__a211oi_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__a211oi_1
+SOURCE CELL NAME: sky130_fd_sc_ls__a211oi_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 12 12
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 9 9
+
+ Instances: 2 2 MN (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SPMP_2_1_1 (6 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SPMP_2_1_1
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A2 A1 B1 C1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a211oi/sky130_fd_sc_ls__a211oi_1.pex.spice b/cells/a211oi/sky130_fd_sc_ls__a211oi_1.pex.spice
index 8bc435f..86cdbef 100644
--- a/cells/a211oi/sky130_fd_sc_ls__a211oi_1.pex.spice
+++ b/cells/a211oi/sky130_fd_sc_ls__a211oi_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a211oi_1.pex.spice
-* Created: Fri Aug 28 12:49:29 2020
+* Created: Wed Sep 2 10:47:33 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a211oi/sky130_fd_sc_ls__a211oi_1.pxi.spice b/cells/a211oi/sky130_fd_sc_ls__a211oi_1.pxi.spice
index 07d36c6..444eab7 100644
--- a/cells/a211oi/sky130_fd_sc_ls__a211oi_1.pxi.spice
+++ b/cells/a211oi/sky130_fd_sc_ls__a211oi_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a211oi_1.pxi.spice
-* Created: Fri Aug 28 12:49:29 2020
+* Created: Wed Sep 2 10:47:33 2020
*
x_PM_SKY130_FD_SC_LS__A211OI_1%A2 N_A2_c_48_n N_A2_M1005_g N_A2_M1003_g A2
+ N_A2_c_50_n PM_SKY130_FD_SC_LS__A211OI_1%A2
diff --git a/cells/a211oi/sky130_fd_sc_ls__a211oi_1.spice b/cells/a211oi/sky130_fd_sc_ls__a211oi_1.spice
index 77bc1cf..c9e505e 100644
--- a/cells/a211oi/sky130_fd_sc_ls__a211oi_1.spice
+++ b/cells/a211oi/sky130_fd_sc_ls__a211oi_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a211oi_1.spice
-* Created: Fri Aug 28 12:49:29 2020
+* Created: Wed Sep 2 10:47:33 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a211oi/sky130_fd_sc_ls__a211oi_2.lvs.report b/cells/a211oi/sky130_fd_sc_ls__a211oi_2.lvs.report
new file mode 100644
index 0000000..3ffb1ab
--- /dev/null
+++ b/cells/a211oi/sky130_fd_sc_ls__a211oi_2.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__a211oi_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__a211oi_2.sp ('sky130_fd_sc_ls__a211oi_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/a211oi/sky130_fd_sc_ls__a211oi_2.spice ('sky130_fd_sc_ls__a211oi_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:47:36 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__a211oi_2 sky130_fd_sc_ls__a211oi_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__a211oi_2
+SOURCE CELL NAME: sky130_fd_sc_ls__a211oi_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 12 12
+
+ Instances: 6 6 MN (4 pins)
+ 8 8 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 15 14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 9 9
+
+ Instances: 2 2 MN (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SPMP_2_1_1 (6 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SPMP_2_1_1
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 12 layout mos transistors were reduced to 6.
+ 6 mos transistors were deleted by parallel reduction.
+ 12 source mos transistors were reduced to 6.
+ 6 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1 A2 B1 C1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a211oi/sky130_fd_sc_ls__a211oi_2.pex.spice b/cells/a211oi/sky130_fd_sc_ls__a211oi_2.pex.spice
index 8d08e38..d87ab55 100644
--- a/cells/a211oi/sky130_fd_sc_ls__a211oi_2.pex.spice
+++ b/cells/a211oi/sky130_fd_sc_ls__a211oi_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a211oi_2.pex.spice
-* Created: Fri Aug 28 12:49:49 2020
+* Created: Wed Sep 2 10:47:39 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a211oi/sky130_fd_sc_ls__a211oi_2.pxi.spice b/cells/a211oi/sky130_fd_sc_ls__a211oi_2.pxi.spice
index 7a09336..9b3edf1 100644
--- a/cells/a211oi/sky130_fd_sc_ls__a211oi_2.pxi.spice
+++ b/cells/a211oi/sky130_fd_sc_ls__a211oi_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a211oi_2.pxi.spice
-* Created: Fri Aug 28 12:49:49 2020
+* Created: Wed Sep 2 10:47:39 2020
*
x_PM_SKY130_FD_SC_LS__A211OI_2%A1 N_A1_c_79_n N_A1_M1011_g N_A1_c_75_n
+ N_A1_M1008_g N_A1_c_80_n N_A1_M1012_g N_A1_c_76_n N_A1_M1010_g A1 N_A1_c_78_n
diff --git a/cells/a211oi/sky130_fd_sc_ls__a211oi_2.spice b/cells/a211oi/sky130_fd_sc_ls__a211oi_2.spice
index 66029c8..a2bf20b 100644
--- a/cells/a211oi/sky130_fd_sc_ls__a211oi_2.spice
+++ b/cells/a211oi/sky130_fd_sc_ls__a211oi_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a211oi_2.spice
-* Created: Fri Aug 28 12:49:49 2020
+* Created: Wed Sep 2 10:47:39 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a211oi/sky130_fd_sc_ls__a211oi_4.lvs.report b/cells/a211oi/sky130_fd_sc_ls__a211oi_4.lvs.report
new file mode 100644
index 0000000..a25cf21
--- /dev/null
+++ b/cells/a211oi/sky130_fd_sc_ls__a211oi_4.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__a211oi_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__a211oi_4.sp ('sky130_fd_sc_ls__a211oi_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/a211oi/sky130_fd_sc_ls__a211oi_4.spice ('sky130_fd_sc_ls__a211oi_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:47:43 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__a211oi_4 sky130_fd_sc_ls__a211oi_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__a211oi_4
+SOURCE CELL NAME: sky130_fd_sc_ls__a211oi_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 12 12
+
+ Instances: 12 12 MN (4 pins)
+ 16 16 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 29 28
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 9 9
+
+ Instances: 2 2 MN (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SPMP_2_1_1 (6 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SPMP_2_1_1
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 28 layout mos transistors were reduced to 8.
+ 20 mos transistors were deleted by parallel reduction.
+ 28 source mos transistors were reduced to 8.
+ 20 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A2 A1 B1 C1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a211oi/sky130_fd_sc_ls__a211oi_4.pex.spice b/cells/a211oi/sky130_fd_sc_ls__a211oi_4.pex.spice
index e16495a..7684454 100644
--- a/cells/a211oi/sky130_fd_sc_ls__a211oi_4.pex.spice
+++ b/cells/a211oi/sky130_fd_sc_ls__a211oi_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a211oi_4.pex.spice
-* Created: Fri Aug 28 12:49:58 2020
+* Created: Wed Sep 2 10:47:46 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a211oi/sky130_fd_sc_ls__a211oi_4.pxi.spice b/cells/a211oi/sky130_fd_sc_ls__a211oi_4.pxi.spice
index 349a694..5b1e3ca 100644
--- a/cells/a211oi/sky130_fd_sc_ls__a211oi_4.pxi.spice
+++ b/cells/a211oi/sky130_fd_sc_ls__a211oi_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a211oi_4.pxi.spice
-* Created: Fri Aug 28 12:49:58 2020
+* Created: Wed Sep 2 10:47:46 2020
*
x_PM_SKY130_FD_SC_LS__A211OI_4%A2 N_A2_c_116_n N_A2_M1002_g N_A2_M1001_g
+ N_A2_c_117_n N_A2_M1006_g N_A2_M1011_g N_A2_c_118_n N_A2_M1013_g N_A2_M1012_g
diff --git a/cells/a211oi/sky130_fd_sc_ls__a211oi_4.spice b/cells/a211oi/sky130_fd_sc_ls__a211oi_4.spice
index ad726f8..06dd6c2 100644
--- a/cells/a211oi/sky130_fd_sc_ls__a211oi_4.spice
+++ b/cells/a211oi/sky130_fd_sc_ls__a211oi_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a211oi_4.spice
-* Created: Fri Aug 28 12:49:58 2020
+* Created: Wed Sep 2 10:47:46 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a21bo/sky130_fd_sc_ls__a21bo_1.lvs.report b/cells/a21bo/sky130_fd_sc_ls__a21bo_1.lvs.report
new file mode 100644
index 0000000..47d4ed5
--- /dev/null
+++ b/cells/a21bo/sky130_fd_sc_ls__a21bo_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__a21bo_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__a21bo_1.sp ('sky130_fd_sc_ls__a21bo_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/a21bo/sky130_fd_sc_ls__a21bo_1.spice ('sky130_fd_sc_ls__a21bo_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:47:50 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__a21bo_1 sky130_fd_sc_ls__a21bo_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__a21bo_1
+SOURCE CELL NAME: sky130_fd_sc_ls__a21bo_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 12 12
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 10 10
+
+ Instances: 3 3 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SPMP_2_1 (5 pins)
+ ------ ------
+ Total Inst: 7 7
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 3 3 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SPMP_2_1
+ ------- ------- --------- ---------
+ Total Inst: 7 7 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A2 A1 B1_N VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a21bo/sky130_fd_sc_ls__a21bo_1.pex.spice b/cells/a21bo/sky130_fd_sc_ls__a21bo_1.pex.spice
index d02b779..14ba991 100644
--- a/cells/a21bo/sky130_fd_sc_ls__a21bo_1.pex.spice
+++ b/cells/a21bo/sky130_fd_sc_ls__a21bo_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a21bo_1.pex.spice
-* Created: Fri Aug 28 12:50:07 2020
+* Created: Wed Sep 2 10:47:52 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a21bo/sky130_fd_sc_ls__a21bo_1.pxi.spice b/cells/a21bo/sky130_fd_sc_ls__a21bo_1.pxi.spice
index 2c92091..41bc304 100644
--- a/cells/a21bo/sky130_fd_sc_ls__a21bo_1.pxi.spice
+++ b/cells/a21bo/sky130_fd_sc_ls__a21bo_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a21bo_1.pxi.spice
-* Created: Fri Aug 28 12:50:07 2020
+* Created: Wed Sep 2 10:47:52 2020
*
x_PM_SKY130_FD_SC_LS__A21BO_1%A2 N_A2_c_74_n N_A2_c_75_n N_A2_c_80_n
+ N_A2_M1004_g N_A2_M1001_g N_A2_c_77_n A2 N_A2_c_78_n
diff --git a/cells/a21bo/sky130_fd_sc_ls__a21bo_1.spice b/cells/a21bo/sky130_fd_sc_ls__a21bo_1.spice
index d32e40a..76cd528 100644
--- a/cells/a21bo/sky130_fd_sc_ls__a21bo_1.spice
+++ b/cells/a21bo/sky130_fd_sc_ls__a21bo_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a21bo_1.spice
-* Created: Fri Aug 28 12:50:07 2020
+* Created: Wed Sep 2 10:47:52 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a21bo/sky130_fd_sc_ls__a21bo_2.lvs.report b/cells/a21bo/sky130_fd_sc_ls__a21bo_2.lvs.report
new file mode 100644
index 0000000..4b43df7
--- /dev/null
+++ b/cells/a21bo/sky130_fd_sc_ls__a21bo_2.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__a21bo_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__a21bo_2.sp ('sky130_fd_sc_ls__a21bo_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/a21bo/sky130_fd_sc_ls__a21bo_2.spice ('sky130_fd_sc_ls__a21bo_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:47:56 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__a21bo_2 sky130_fd_sc_ls__a21bo_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__a21bo_2
+SOURCE CELL NAME: sky130_fd_sc_ls__a21bo_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 12 12
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 10 10
+
+ Instances: 3 3 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SPMP_2_1 (5 pins)
+ ------ ------
+ Total Inst: 7 7
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 3 3 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SPMP_2_1
+ ------- ------- --------- ---------
+ Total Inst: 7 7 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1_N A1 A2 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a21bo/sky130_fd_sc_ls__a21bo_2.pex.spice b/cells/a21bo/sky130_fd_sc_ls__a21bo_2.pex.spice
index b9b0baf..a49e1d0 100644
--- a/cells/a21bo/sky130_fd_sc_ls__a21bo_2.pex.spice
+++ b/cells/a21bo/sky130_fd_sc_ls__a21bo_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a21bo_2.pex.spice
-* Created: Fri Aug 28 12:50:17 2020
+* Created: Wed Sep 2 10:47:59 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a21bo/sky130_fd_sc_ls__a21bo_2.pxi.spice b/cells/a21bo/sky130_fd_sc_ls__a21bo_2.pxi.spice
index 6137c38..9020c5c 100644
--- a/cells/a21bo/sky130_fd_sc_ls__a21bo_2.pxi.spice
+++ b/cells/a21bo/sky130_fd_sc_ls__a21bo_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a21bo_2.pxi.spice
-* Created: Fri Aug 28 12:50:17 2020
+* Created: Wed Sep 2 10:47:59 2020
*
x_PM_SKY130_FD_SC_LS__A21BO_2%B1_N N_B1_N_c_72_n N_B1_N_M1005_g N_B1_N_c_73_n
+ N_B1_N_M1009_g B1_N N_B1_N_c_74_n PM_SKY130_FD_SC_LS__A21BO_2%B1_N
diff --git a/cells/a21bo/sky130_fd_sc_ls__a21bo_2.spice b/cells/a21bo/sky130_fd_sc_ls__a21bo_2.spice
index 2c0a00b..7857c2c 100644
--- a/cells/a21bo/sky130_fd_sc_ls__a21bo_2.spice
+++ b/cells/a21bo/sky130_fd_sc_ls__a21bo_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a21bo_2.spice
-* Created: Fri Aug 28 12:50:17 2020
+* Created: Wed Sep 2 10:47:59 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a21bo/sky130_fd_sc_ls__a21bo_4.lvs.report b/cells/a21bo/sky130_fd_sc_ls__a21bo_4.lvs.report
new file mode 100644
index 0000000..65a219c
--- /dev/null
+++ b/cells/a21bo/sky130_fd_sc_ls__a21bo_4.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__a21bo_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__a21bo_4.sp ('sky130_fd_sc_ls__a21bo_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/a21bo/sky130_fd_sc_ls__a21bo_4.spice ('sky130_fd_sc_ls__a21bo_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:48:02 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__a21bo_4 sky130_fd_sc_ls__a21bo_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__a21bo_4
+SOURCE CELL NAME: sky130_fd_sc_ls__a21bo_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 12 12
+
+ Instances: 11 11 MN (4 pins)
+ 11 11 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 23 22
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 10 10
+
+ Instances: 3 3 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SPMP_2_1 (5 pins)
+ ------ ------
+ Total Inst: 7 7
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 3 3 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SPMP_2_1
+ ------- ------- --------- ---------
+ Total Inst: 7 7 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 20 layout mos transistors were reduced to 8.
+ 12 mos transistors were deleted by parallel reduction.
+ 20 source mos transistors were reduced to 8.
+ 12 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1_N A1 A2 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a21bo/sky130_fd_sc_ls__a21bo_4.pex.spice b/cells/a21bo/sky130_fd_sc_ls__a21bo_4.pex.spice
index b1fb8da..07a431f 100644
--- a/cells/a21bo/sky130_fd_sc_ls__a21bo_4.pex.spice
+++ b/cells/a21bo/sky130_fd_sc_ls__a21bo_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a21bo_4.pex.spice
-* Created: Fri Aug 28 12:50:32 2020
+* Created: Wed Sep 2 10:48:05 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a21bo/sky130_fd_sc_ls__a21bo_4.pxi.spice b/cells/a21bo/sky130_fd_sc_ls__a21bo_4.pxi.spice
index 564b1d6..7e56231 100644
--- a/cells/a21bo/sky130_fd_sc_ls__a21bo_4.pxi.spice
+++ b/cells/a21bo/sky130_fd_sc_ls__a21bo_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a21bo_4.pxi.spice
-* Created: Fri Aug 28 12:50:32 2020
+* Created: Wed Sep 2 10:48:05 2020
*
x_PM_SKY130_FD_SC_LS__A21BO_4%B1_N N_B1_N_c_117_n N_B1_N_c_123_n N_B1_N_M1019_g
+ N_B1_N_M1004_g N_B1_N_c_119_n B1_N N_B1_N_c_121_n
diff --git a/cells/a21bo/sky130_fd_sc_ls__a21bo_4.spice b/cells/a21bo/sky130_fd_sc_ls__a21bo_4.spice
index 476b941..4d629bf 100644
--- a/cells/a21bo/sky130_fd_sc_ls__a21bo_4.spice
+++ b/cells/a21bo/sky130_fd_sc_ls__a21bo_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a21bo_4.spice
-* Created: Fri Aug 28 12:50:32 2020
+* Created: Wed Sep 2 10:48:05 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a21boi/sky130_fd_sc_ls__a21boi_1.lvs.report b/cells/a21boi/sky130_fd_sc_ls__a21boi_1.lvs.report
new file mode 100644
index 0000000..480901c
--- /dev/null
+++ b/cells/a21boi/sky130_fd_sc_ls__a21boi_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__a21boi_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__a21boi_1.sp ('sky130_fd_sc_ls__a21boi_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/a21boi/sky130_fd_sc_ls__a21boi_1.spice ('sky130_fd_sc_ls__a21boi_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:48:09 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__a21boi_1 sky130_fd_sc_ls__a21boi_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__a21boi_1
+SOURCE CELL NAME: sky130_fd_sc_ls__a21boi_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 11 11
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 9 9
+
+ Instances: 2 2 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SPMP_2_1 (5 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SPMP_2_1
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1_N A1 A2 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a21boi/sky130_fd_sc_ls__a21boi_1.pex.spice b/cells/a21boi/sky130_fd_sc_ls__a21boi_1.pex.spice
index d21f202..9d39841 100644
--- a/cells/a21boi/sky130_fd_sc_ls__a21boi_1.pex.spice
+++ b/cells/a21boi/sky130_fd_sc_ls__a21boi_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a21boi_1.pex.spice
-* Created: Fri Aug 28 12:50:52 2020
+* Created: Wed Sep 2 10:48:11 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a21boi/sky130_fd_sc_ls__a21boi_1.pxi.spice b/cells/a21boi/sky130_fd_sc_ls__a21boi_1.pxi.spice
index 5f7383a..8015059 100644
--- a/cells/a21boi/sky130_fd_sc_ls__a21boi_1.pxi.spice
+++ b/cells/a21boi/sky130_fd_sc_ls__a21boi_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a21boi_1.pxi.spice
-* Created: Fri Aug 28 12:50:52 2020
+* Created: Wed Sep 2 10:48:11 2020
*
x_PM_SKY130_FD_SC_LS__A21BOI_1%B1_N N_B1_N_c_58_n N_B1_N_c_64_n N_B1_N_c_65_n
+ N_B1_N_M1005_g N_B1_N_c_59_n N_B1_N_c_60_n N_B1_N_M1002_g B1_N B1_N B1_N
diff --git a/cells/a21boi/sky130_fd_sc_ls__a21boi_1.spice b/cells/a21boi/sky130_fd_sc_ls__a21boi_1.spice
index 03df869..bb8aea2 100644
--- a/cells/a21boi/sky130_fd_sc_ls__a21boi_1.spice
+++ b/cells/a21boi/sky130_fd_sc_ls__a21boi_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a21boi_1.spice
-* Created: Fri Aug 28 12:50:52 2020
+* Created: Wed Sep 2 10:48:11 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a21boi/sky130_fd_sc_ls__a21boi_2.lvs.report b/cells/a21boi/sky130_fd_sc_ls__a21boi_2.lvs.report
new file mode 100644
index 0000000..6db23c8
--- /dev/null
+++ b/cells/a21boi/sky130_fd_sc_ls__a21boi_2.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__a21boi_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__a21boi_2.sp ('sky130_fd_sc_ls__a21boi_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/a21boi/sky130_fd_sc_ls__a21boi_2.spice ('sky130_fd_sc_ls__a21boi_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:48:15 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__a21boi_2 sky130_fd_sc_ls__a21boi_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__a21boi_2
+SOURCE CELL NAME: sky130_fd_sc_ls__a21boi_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 11 11
+
+ Instances: 7 7 MN (4 pins)
+ 7 7 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 15 14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 9 9
+
+ Instances: 2 2 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SPMP_2_1 (5 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SPMP_2_1
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 12 layout mos transistors were reduced to 6.
+ 6 mos transistors were deleted by parallel reduction.
+ 12 source mos transistors were reduced to 6.
+ 6 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1_N A1 A2 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a21boi/sky130_fd_sc_ls__a21boi_2.pex.spice b/cells/a21boi/sky130_fd_sc_ls__a21boi_2.pex.spice
index 609cfe3..8163b00 100644
--- a/cells/a21boi/sky130_fd_sc_ls__a21boi_2.pex.spice
+++ b/cells/a21boi/sky130_fd_sc_ls__a21boi_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a21boi_2.pex.spice
-* Created: Fri Aug 28 12:51:01 2020
+* Created: Wed Sep 2 10:48:17 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a21boi/sky130_fd_sc_ls__a21boi_2.pxi.spice b/cells/a21boi/sky130_fd_sc_ls__a21boi_2.pxi.spice
index 0803537..878a09e 100644
--- a/cells/a21boi/sky130_fd_sc_ls__a21boi_2.pxi.spice
+++ b/cells/a21boi/sky130_fd_sc_ls__a21boi_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a21boi_2.pxi.spice
-* Created: Fri Aug 28 12:51:01 2020
+* Created: Wed Sep 2 10:48:17 2020
*
x_PM_SKY130_FD_SC_LS__A21BOI_2%B1_N N_B1_N_c_80_n N_B1_N_M1002_g N_B1_N_M1000_g
+ N_B1_N_c_82_n B1_N PM_SKY130_FD_SC_LS__A21BOI_2%B1_N
diff --git a/cells/a21boi/sky130_fd_sc_ls__a21boi_2.spice b/cells/a21boi/sky130_fd_sc_ls__a21boi_2.spice
index 73669b1..75896b4 100644
--- a/cells/a21boi/sky130_fd_sc_ls__a21boi_2.spice
+++ b/cells/a21boi/sky130_fd_sc_ls__a21boi_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a21boi_2.spice
-* Created: Fri Aug 28 12:51:01 2020
+* Created: Wed Sep 2 10:48:17 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a21boi/sky130_fd_sc_ls__a21boi_4.lvs.report b/cells/a21boi/sky130_fd_sc_ls__a21boi_4.lvs.report
new file mode 100644
index 0000000..262d038
--- /dev/null
+++ b/cells/a21boi/sky130_fd_sc_ls__a21boi_4.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__a21boi_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__a21boi_4.sp ('sky130_fd_sc_ls__a21boi_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/a21boi/sky130_fd_sc_ls__a21boi_4.spice ('sky130_fd_sc_ls__a21boi_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:48:21 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__a21boi_4 sky130_fd_sc_ls__a21boi_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__a21boi_4
+SOURCE CELL NAME: sky130_fd_sc_ls__a21boi_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 11 11
+
+ Instances: 13 13 MN (4 pins)
+ 14 14 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 28 27
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 9 9
+
+ Instances: 2 2 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SPMP_2_1 (5 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SPMP_2_1
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 26 layout mos transistors were reduced to 7.
+ 19 mos transistors were deleted by parallel reduction.
+ 26 source mos transistors were reduced to 7.
+ 19 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1 A2 B1_N VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a21boi/sky130_fd_sc_ls__a21boi_4.pex.spice b/cells/a21boi/sky130_fd_sc_ls__a21boi_4.pex.spice
index d6e38dc..9db9632 100644
--- a/cells/a21boi/sky130_fd_sc_ls__a21boi_4.pex.spice
+++ b/cells/a21boi/sky130_fd_sc_ls__a21boi_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a21boi_4.pex.spice
-* Created: Fri Aug 28 12:51:10 2020
+* Created: Wed Sep 2 10:48:23 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a21boi/sky130_fd_sc_ls__a21boi_4.pxi.spice b/cells/a21boi/sky130_fd_sc_ls__a21boi_4.pxi.spice
index e96e0fb..2942d68 100644
--- a/cells/a21boi/sky130_fd_sc_ls__a21boi_4.pxi.spice
+++ b/cells/a21boi/sky130_fd_sc_ls__a21boi_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a21boi_4.pxi.spice
-* Created: Fri Aug 28 12:51:10 2020
+* Created: Wed Sep 2 10:48:23 2020
*
x_PM_SKY130_FD_SC_LS__A21BOI_4%A1 N_A1_c_125_n N_A1_M1002_g N_A1_M1000_g
+ N_A1_c_126_n N_A1_M1016_g N_A1_M1003_g N_A1_c_127_n N_A1_M1017_g N_A1_M1004_g
diff --git a/cells/a21boi/sky130_fd_sc_ls__a21boi_4.spice b/cells/a21boi/sky130_fd_sc_ls__a21boi_4.spice
index d745171..538d54b 100644
--- a/cells/a21boi/sky130_fd_sc_ls__a21boi_4.spice
+++ b/cells/a21boi/sky130_fd_sc_ls__a21boi_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a21boi_4.spice
-* Created: Fri Aug 28 12:51:10 2020
+* Created: Wed Sep 2 10:48:23 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a21o/sky130_fd_sc_ls__a21o_1.lvs.report b/cells/a21o/sky130_fd_sc_ls__a21o_1.lvs.report
new file mode 100644
index 0000000..ec8bfec
--- /dev/null
+++ b/cells/a21o/sky130_fd_sc_ls__a21o_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__a21o_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__a21o_1.sp ('sky130_fd_sc_ls__a21o_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/a21o/sky130_fd_sc_ls__a21o_1.spice ('sky130_fd_sc_ls__a21o_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:48:27 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__a21o_1 sky130_fd_sc_ls__a21o_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__a21o_1
+SOURCE CELL NAME: sky130_fd_sc_ls__a21o_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 11 11
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 9 9
+
+ Instances: 2 2 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SPMP_2_1 (5 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SPMP_2_1
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1 A1 A2 X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a21o/sky130_fd_sc_ls__a21o_1.pex.spice b/cells/a21o/sky130_fd_sc_ls__a21o_1.pex.spice
index 1e96f51..264ed99 100644
--- a/cells/a21o/sky130_fd_sc_ls__a21o_1.pex.spice
+++ b/cells/a21o/sky130_fd_sc_ls__a21o_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a21o_1.pex.spice
-* Created: Fri Aug 28 12:51:19 2020
+* Created: Wed Sep 2 10:48:30 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a21o/sky130_fd_sc_ls__a21o_1.pxi.spice b/cells/a21o/sky130_fd_sc_ls__a21o_1.pxi.spice
index 5652a1b..471e8c8 100644
--- a/cells/a21o/sky130_fd_sc_ls__a21o_1.pxi.spice
+++ b/cells/a21o/sky130_fd_sc_ls__a21o_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a21o_1.pxi.spice
-* Created: Fri Aug 28 12:51:19 2020
+* Created: Wed Sep 2 10:48:30 2020
*
x_PM_SKY130_FD_SC_LS__A21O_1%A_81_264# N_A_81_264#_M1004_d N_A_81_264#_M1002_s
+ N_A_81_264#_c_60_n N_A_81_264#_M1007_g N_A_81_264#_c_61_n N_A_81_264#_c_62_n
diff --git a/cells/a21o/sky130_fd_sc_ls__a21o_1.spice b/cells/a21o/sky130_fd_sc_ls__a21o_1.spice
index f1af338..9e3c4fa 100644
--- a/cells/a21o/sky130_fd_sc_ls__a21o_1.spice
+++ b/cells/a21o/sky130_fd_sc_ls__a21o_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a21o_1.spice
-* Created: Fri Aug 28 12:51:19 2020
+* Created: Wed Sep 2 10:48:30 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a21o/sky130_fd_sc_ls__a21o_2.lvs.report b/cells/a21o/sky130_fd_sc_ls__a21o_2.lvs.report
new file mode 100644
index 0000000..55d4b74
--- /dev/null
+++ b/cells/a21o/sky130_fd_sc_ls__a21o_2.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__a21o_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__a21o_2.sp ('sky130_fd_sc_ls__a21o_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/a21o/sky130_fd_sc_ls__a21o_2.spice ('sky130_fd_sc_ls__a21o_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:48:33 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__a21o_2 sky130_fd_sc_ls__a21o_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__a21o_2
+SOURCE CELL NAME: sky130_fd_sc_ls__a21o_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 11 11
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 9 9
+
+ Instances: 2 2 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SPMP_2_1 (5 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SPMP_2_1
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1 A1 A2 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a21o/sky130_fd_sc_ls__a21o_2.pex.spice b/cells/a21o/sky130_fd_sc_ls__a21o_2.pex.spice
index a100f38..4d1e879 100644
--- a/cells/a21o/sky130_fd_sc_ls__a21o_2.pex.spice
+++ b/cells/a21o/sky130_fd_sc_ls__a21o_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a21o_2.pex.spice
-* Created: Fri Aug 28 12:51:35 2020
+* Created: Wed Sep 2 10:48:36 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a21o/sky130_fd_sc_ls__a21o_2.pxi.spice b/cells/a21o/sky130_fd_sc_ls__a21o_2.pxi.spice
index 364b55b..7cbe092 100644
--- a/cells/a21o/sky130_fd_sc_ls__a21o_2.pxi.spice
+++ b/cells/a21o/sky130_fd_sc_ls__a21o_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a21o_2.pxi.spice
-* Created: Fri Aug 28 12:51:35 2020
+* Created: Wed Sep 2 10:48:36 2020
*
x_PM_SKY130_FD_SC_LS__A21O_2%A_84_244# N_A_84_244#_M1002_d N_A_84_244#_M1005_s
+ N_A_84_244#_c_67_n N_A_84_244#_M1003_g N_A_84_244#_c_60_n N_A_84_244#_M1000_g
diff --git a/cells/a21o/sky130_fd_sc_ls__a21o_2.spice b/cells/a21o/sky130_fd_sc_ls__a21o_2.spice
index 34ad7dd..26a6bdf 100644
--- a/cells/a21o/sky130_fd_sc_ls__a21o_2.spice
+++ b/cells/a21o/sky130_fd_sc_ls__a21o_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a21o_2.spice
-* Created: Fri Aug 28 12:51:35 2020
+* Created: Wed Sep 2 10:48:36 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a21o/sky130_fd_sc_ls__a21o_4.lvs.report b/cells/a21o/sky130_fd_sc_ls__a21o_4.lvs.report
new file mode 100644
index 0000000..1160ace
--- /dev/null
+++ b/cells/a21o/sky130_fd_sc_ls__a21o_4.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__a21o_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__a21o_4.sp ('sky130_fd_sc_ls__a21o_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/a21o/sky130_fd_sc_ls__a21o_4.spice ('sky130_fd_sc_ls__a21o_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:48:39 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__a21o_4 sky130_fd_sc_ls__a21o_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__a21o_4
+SOURCE CELL NAME: sky130_fd_sc_ls__a21o_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 11 11
+
+ Instances: 10 10 MN (4 pins)
+ 10 10 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 21 20
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 9 9
+
+ Instances: 2 2 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SPMP_2_1 (5 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SPMP_2_1
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 20 layout mos transistors were reduced to 8.
+ 12 mos transistors were deleted by parallel reduction.
+ 20 source mos transistors were reduced to 8.
+ 12 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1 A1 A2 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a21o/sky130_fd_sc_ls__a21o_4.pex.spice b/cells/a21o/sky130_fd_sc_ls__a21o_4.pex.spice
index 8fedf78..322c724 100644
--- a/cells/a21o/sky130_fd_sc_ls__a21o_4.pex.spice
+++ b/cells/a21o/sky130_fd_sc_ls__a21o_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a21o_4.pex.spice
-* Created: Fri Aug 28 12:51:55 2020
+* Created: Wed Sep 2 10:48:42 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a21o/sky130_fd_sc_ls__a21o_4.pxi.spice b/cells/a21o/sky130_fd_sc_ls__a21o_4.pxi.spice
index 5977bb9..2fc3295 100644
--- a/cells/a21o/sky130_fd_sc_ls__a21o_4.pxi.spice
+++ b/cells/a21o/sky130_fd_sc_ls__a21o_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a21o_4.pxi.spice
-* Created: Fri Aug 28 12:51:55 2020
+* Created: Wed Sep 2 10:48:42 2020
*
x_PM_SKY130_FD_SC_LS__A21O_4%A_91_48# N_A_91_48#_M1008_d N_A_91_48#_M1006_s
+ N_A_91_48#_M1004_d N_A_91_48#_M1000_g N_A_91_48#_c_120_n N_A_91_48#_M1002_g
diff --git a/cells/a21o/sky130_fd_sc_ls__a21o_4.spice b/cells/a21o/sky130_fd_sc_ls__a21o_4.spice
index 8866ee4..e69970e 100644
--- a/cells/a21o/sky130_fd_sc_ls__a21o_4.spice
+++ b/cells/a21o/sky130_fd_sc_ls__a21o_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a21o_4.spice
-* Created: Fri Aug 28 12:51:55 2020
+* Created: Wed Sep 2 10:48:42 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a21oi/sky130_fd_sc_ls__a21oi_1.lvs.report b/cells/a21oi/sky130_fd_sc_ls__a21oi_1.lvs.report
new file mode 100644
index 0000000..24e257b
--- /dev/null
+++ b/cells/a21oi/sky130_fd_sc_ls__a21oi_1.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__a21oi_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__a21oi_1.sp ('sky130_fd_sc_ls__a21oi_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/a21oi/sky130_fd_sc_ls__a21oi_1.spice ('sky130_fd_sc_ls__a21oi_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:48:45 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__a21oi_1 sky130_fd_sc_ls__a21oi_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__a21oi_1
+SOURCE CELL NAME: sky130_fd_sc_ls__a21oi_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 10 10
+
+ Instances: 3 3 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 7 6
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 8 8
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SPMP_2_1 (5 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SPMP_2_1
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A2 A1 B1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a21oi/sky130_fd_sc_ls__a21oi_1.pex.spice b/cells/a21oi/sky130_fd_sc_ls__a21oi_1.pex.spice
index 09d3dd4..a9b9fde 100644
--- a/cells/a21oi/sky130_fd_sc_ls__a21oi_1.pex.spice
+++ b/cells/a21oi/sky130_fd_sc_ls__a21oi_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a21oi_1.pex.spice
-* Created: Fri Aug 28 12:52:04 2020
+* Created: Wed Sep 2 10:48:48 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a21oi/sky130_fd_sc_ls__a21oi_1.pxi.spice b/cells/a21oi/sky130_fd_sc_ls__a21oi_1.pxi.spice
index 31454ec..6bd3582 100644
--- a/cells/a21oi/sky130_fd_sc_ls__a21oi_1.pxi.spice
+++ b/cells/a21oi/sky130_fd_sc_ls__a21oi_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a21oi_1.pxi.spice
-* Created: Fri Aug 28 12:52:04 2020
+* Created: Wed Sep 2 10:48:48 2020
*
x_PM_SKY130_FD_SC_LS__A21OI_1%A2 N_A2_c_36_n N_A2_M1003_g N_A2_c_37_n
+ N_A2_M1005_g A2 PM_SKY130_FD_SC_LS__A21OI_1%A2
diff --git a/cells/a21oi/sky130_fd_sc_ls__a21oi_1.spice b/cells/a21oi/sky130_fd_sc_ls__a21oi_1.spice
index 7e06710..7defad7 100644
--- a/cells/a21oi/sky130_fd_sc_ls__a21oi_1.spice
+++ b/cells/a21oi/sky130_fd_sc_ls__a21oi_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a21oi_1.spice
-* Created: Fri Aug 28 12:52:04 2020
+* Created: Wed Sep 2 10:48:48 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a21oi/sky130_fd_sc_ls__a21oi_2.lvs.report b/cells/a21oi/sky130_fd_sc_ls__a21oi_2.lvs.report
new file mode 100644
index 0000000..8e534da
--- /dev/null
+++ b/cells/a21oi/sky130_fd_sc_ls__a21oi_2.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__a21oi_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__a21oi_2.sp ('sky130_fd_sc_ls__a21oi_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/a21oi/sky130_fd_sc_ls__a21oi_2.spice ('sky130_fd_sc_ls__a21oi_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:48:52 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__a21oi_2 sky130_fd_sc_ls__a21oi_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__a21oi_2
+SOURCE CELL NAME: sky130_fd_sc_ls__a21oi_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 10 10
+
+ Instances: 5 5 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 12 11
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 8 8
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SPMP_2_1 (5 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SPMP_2_1
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 10 layout mos transistors were reduced to 5.
+ 5 mos transistors were deleted by parallel reduction.
+ 10 source mos transistors were reduced to 5.
+ 5 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1 A2 A1 Y VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a21oi/sky130_fd_sc_ls__a21oi_2.pex.spice b/cells/a21oi/sky130_fd_sc_ls__a21oi_2.pex.spice
index fd3e70c..c23aae3 100644
--- a/cells/a21oi/sky130_fd_sc_ls__a21oi_2.pex.spice
+++ b/cells/a21oi/sky130_fd_sc_ls__a21oi_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a21oi_2.pex.spice
-* Created: Fri Aug 28 12:52:13 2020
+* Created: Wed Sep 2 10:48:55 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a21oi/sky130_fd_sc_ls__a21oi_2.pxi.spice b/cells/a21oi/sky130_fd_sc_ls__a21oi_2.pxi.spice
index e83e801..ab5194c 100644
--- a/cells/a21oi/sky130_fd_sc_ls__a21oi_2.pxi.spice
+++ b/cells/a21oi/sky130_fd_sc_ls__a21oi_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a21oi_2.pxi.spice
-* Created: Fri Aug 28 12:52:13 2020
+* Created: Wed Sep 2 10:48:55 2020
*
x_PM_SKY130_FD_SC_LS__A21OI_2%B1 N_B1_M1008_g N_B1_c_70_n N_B1_c_76_n
+ N_B1_M1007_g N_B1_c_71_n N_B1_c_78_n N_B1_M1009_g N_B1_c_72_n B1 N_B1_c_74_n
diff --git a/cells/a21oi/sky130_fd_sc_ls__a21oi_2.spice b/cells/a21oi/sky130_fd_sc_ls__a21oi_2.spice
index 0211a3d..5f1d933 100644
--- a/cells/a21oi/sky130_fd_sc_ls__a21oi_2.spice
+++ b/cells/a21oi/sky130_fd_sc_ls__a21oi_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a21oi_2.spice
-* Created: Fri Aug 28 12:52:13 2020
+* Created: Wed Sep 2 10:48:55 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a21oi/sky130_fd_sc_ls__a21oi_4.lvs.report b/cells/a21oi/sky130_fd_sc_ls__a21oi_4.lvs.report
new file mode 100644
index 0000000..f09930d
--- /dev/null
+++ b/cells/a21oi/sky130_fd_sc_ls__a21oi_4.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__a21oi_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__a21oi_4.sp ('sky130_fd_sc_ls__a21oi_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/a21oi/sky130_fd_sc_ls__a21oi_4.spice ('sky130_fd_sc_ls__a21oi_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:48:58 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__a21oi_4 sky130_fd_sc_ls__a21oi_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__a21oi_4
+SOURCE CELL NAME: sky130_fd_sc_ls__a21oi_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 10 10
+
+ Instances: 10 10 MN (4 pins)
+ 12 12 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 23 22
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 8 8
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SPMP_2_1 (5 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SPMP_2_1
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 22 layout mos transistors were reduced to 6.
+ 16 mos transistors were deleted by parallel reduction.
+ 22 source mos transistors were reduced to 6.
+ 16 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A2 A1 B1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a21oi/sky130_fd_sc_ls__a21oi_4.pex.spice b/cells/a21oi/sky130_fd_sc_ls__a21oi_4.pex.spice
index 41aa671..70b39b2 100644
--- a/cells/a21oi/sky130_fd_sc_ls__a21oi_4.pex.spice
+++ b/cells/a21oi/sky130_fd_sc_ls__a21oi_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a21oi_4.pex.spice
-* Created: Fri Aug 28 12:52:22 2020
+* Created: Wed Sep 2 10:49:01 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a21oi/sky130_fd_sc_ls__a21oi_4.pxi.spice b/cells/a21oi/sky130_fd_sc_ls__a21oi_4.pxi.spice
index 33fb01e..3bcb816 100644
--- a/cells/a21oi/sky130_fd_sc_ls__a21oi_4.pxi.spice
+++ b/cells/a21oi/sky130_fd_sc_ls__a21oi_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a21oi_4.pxi.spice
-* Created: Fri Aug 28 12:52:22 2020
+* Created: Wed Sep 2 10:49:01 2020
*
x_PM_SKY130_FD_SC_LS__A21OI_4%A2 N_A2_c_100_n N_A2_M1002_g N_A2_M1001_g
+ N_A2_c_101_n N_A2_M1003_g N_A2_M1013_g N_A2_c_102_n N_A2_M1005_g N_A2_M1014_g
diff --git a/cells/a21oi/sky130_fd_sc_ls__a21oi_4.spice b/cells/a21oi/sky130_fd_sc_ls__a21oi_4.spice
index e447fdb..54ce6da 100644
--- a/cells/a21oi/sky130_fd_sc_ls__a21oi_4.spice
+++ b/cells/a21oi/sky130_fd_sc_ls__a21oi_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a21oi_4.spice
-* Created: Fri Aug 28 12:52:22 2020
+* Created: Wed Sep 2 10:49:01 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a221o/sky130_fd_sc_ls__a221o_1.lvs.report b/cells/a221o/sky130_fd_sc_ls__a221o_1.lvs.report
new file mode 100644
index 0000000..2ef41cc
--- /dev/null
+++ b/cells/a221o/sky130_fd_sc_ls__a221o_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__a221o_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__a221o_1.sp ('sky130_fd_sc_ls__a221o_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/a221o/sky130_fd_sc_ls__a221o_1.spice ('sky130_fd_sc_ls__a221o_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:49:05 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__a221o_1 sky130_fd_sc_ls__a221o_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__a221o_1
+SOURCE CELL NAME: sky130_fd_sc_ls__a221o_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 15 15
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 11 11
+
+ Instances: 2 2 MN (4 pins)
+ 1 1 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ 1 1 SPMP_2_2_1 (7 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ 1 1 0 0 SPMP_2_2_1
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A2 A1 B1 B2 C1 X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a221o/sky130_fd_sc_ls__a221o_1.pex.spice b/cells/a221o/sky130_fd_sc_ls__a221o_1.pex.spice
index ee395c8..868346f 100644
--- a/cells/a221o/sky130_fd_sc_ls__a221o_1.pex.spice
+++ b/cells/a221o/sky130_fd_sc_ls__a221o_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a221o_1.pex.spice
-* Created: Fri Aug 28 12:52:39 2020
+* Created: Wed Sep 2 10:49:08 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a221o/sky130_fd_sc_ls__a221o_1.pxi.spice b/cells/a221o/sky130_fd_sc_ls__a221o_1.pxi.spice
index d8d5f9c..ffbc50d 100644
--- a/cells/a221o/sky130_fd_sc_ls__a221o_1.pxi.spice
+++ b/cells/a221o/sky130_fd_sc_ls__a221o_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a221o_1.pxi.spice
-* Created: Fri Aug 28 12:52:39 2020
+* Created: Wed Sep 2 10:49:08 2020
*
x_PM_SKY130_FD_SC_LS__A221O_1%A_148_260# N_A_148_260#_M1003_d
+ N_A_148_260#_M1001_d N_A_148_260#_M1009_d N_A_148_260#_c_69_n
diff --git a/cells/a221o/sky130_fd_sc_ls__a221o_1.spice b/cells/a221o/sky130_fd_sc_ls__a221o_1.spice
index 9c2e74d..6753f0f 100644
--- a/cells/a221o/sky130_fd_sc_ls__a221o_1.spice
+++ b/cells/a221o/sky130_fd_sc_ls__a221o_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a221o_1.spice
-* Created: Fri Aug 28 12:52:39 2020
+* Created: Wed Sep 2 10:49:08 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a221o/sky130_fd_sc_ls__a221o_2.lvs.report b/cells/a221o/sky130_fd_sc_ls__a221o_2.lvs.report
new file mode 100644
index 0000000..4eae89b
--- /dev/null
+++ b/cells/a221o/sky130_fd_sc_ls__a221o_2.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__a221o_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__a221o_2.sp ('sky130_fd_sc_ls__a221o_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/a221o/sky130_fd_sc_ls__a221o_2.spice ('sky130_fd_sc_ls__a221o_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:49:11 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__a221o_2 sky130_fd_sc_ls__a221o_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__a221o_2
+SOURCE CELL NAME: sky130_fd_sc_ls__a221o_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 15 15
+
+ Instances: 7 7 MN (4 pins)
+ 7 7 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 15 14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 11 11
+
+ Instances: 2 2 MN (4 pins)
+ 1 1 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ 1 1 SPMP_2_2_1 (7 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ 1 1 0 0 SPMP_2_2_1
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A2 A1 B1 B2 C1 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a221o/sky130_fd_sc_ls__a221o_2.pex.spice b/cells/a221o/sky130_fd_sc_ls__a221o_2.pex.spice
index 33afefe..e79e118 100644
--- a/cells/a221o/sky130_fd_sc_ls__a221o_2.pex.spice
+++ b/cells/a221o/sky130_fd_sc_ls__a221o_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a221o_2.pex.spice
-* Created: Fri Aug 28 12:52:58 2020
+* Created: Wed Sep 2 10:49:14 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a221o/sky130_fd_sc_ls__a221o_2.pxi.spice b/cells/a221o/sky130_fd_sc_ls__a221o_2.pxi.spice
index b46ab23..1805f82 100644
--- a/cells/a221o/sky130_fd_sc_ls__a221o_2.pxi.spice
+++ b/cells/a221o/sky130_fd_sc_ls__a221o_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a221o_2.pxi.spice
-* Created: Fri Aug 28 12:52:58 2020
+* Created: Wed Sep 2 10:49:14 2020
*
x_PM_SKY130_FD_SC_LS__A221O_2%A_89_260# N_A_89_260#_M1011_d N_A_89_260#_M1009_d
+ N_A_89_260#_M1005_d N_A_89_260#_c_95_n N_A_89_260#_M1007_g N_A_89_260#_M1012_g
diff --git a/cells/a221o/sky130_fd_sc_ls__a221o_2.spice b/cells/a221o/sky130_fd_sc_ls__a221o_2.spice
index 310bcc3..5ab3c88 100644
--- a/cells/a221o/sky130_fd_sc_ls__a221o_2.spice
+++ b/cells/a221o/sky130_fd_sc_ls__a221o_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a221o_2.spice
-* Created: Fri Aug 28 12:52:58 2020
+* Created: Wed Sep 2 10:49:14 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a221o/sky130_fd_sc_ls__a221o_4.lvs.report b/cells/a221o/sky130_fd_sc_ls__a221o_4.lvs.report
new file mode 100644
index 0000000..0b3fe36
--- /dev/null
+++ b/cells/a221o/sky130_fd_sc_ls__a221o_4.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__a221o_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__a221o_4.sp ('sky130_fd_sc_ls__a221o_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/a221o/sky130_fd_sc_ls__a221o_4.spice ('sky130_fd_sc_ls__a221o_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:49:17 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__a221o_4 sky130_fd_sc_ls__a221o_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__a221o_4
+SOURCE CELL NAME: sky130_fd_sc_ls__a221o_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 15 15
+
+ Instances: 14 14 MN (4 pins)
+ 14 14 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 29 28
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 11 11
+
+ Instances: 2 2 MN (4 pins)
+ 1 1 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ 1 1 SPMP_2_2_1 (7 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ 1 1 0 0 SPMP_2_2_1
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 28 layout mos transistors were reduced to 12.
+ 16 mos transistors were deleted by parallel reduction.
+ 28 source mos transistors were reduced to 12.
+ 16 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1 A2 C1 B2 B1 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a221o/sky130_fd_sc_ls__a221o_4.pex.spice b/cells/a221o/sky130_fd_sc_ls__a221o_4.pex.spice
index 2904117..9297bdc 100644
--- a/cells/a221o/sky130_fd_sc_ls__a221o_4.pex.spice
+++ b/cells/a221o/sky130_fd_sc_ls__a221o_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a221o_4.pex.spice
-* Created: Fri Aug 28 12:53:08 2020
+* Created: Wed Sep 2 10:49:20 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a221o/sky130_fd_sc_ls__a221o_4.pxi.spice b/cells/a221o/sky130_fd_sc_ls__a221o_4.pxi.spice
index 54b4fd2..969f8a2 100644
--- a/cells/a221o/sky130_fd_sc_ls__a221o_4.pxi.spice
+++ b/cells/a221o/sky130_fd_sc_ls__a221o_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a221o_4.pxi.spice
-* Created: Fri Aug 28 12:53:08 2020
+* Created: Wed Sep 2 10:49:20 2020
*
x_PM_SKY130_FD_SC_LS__A221O_4%A1 N_A1_M1004_g N_A1_c_160_n N_A1_c_161_n
+ N_A1_c_172_n N_A1_M1000_g N_A1_c_162_n N_A1_c_163_n N_A1_M1006_g N_A1_c_165_n
diff --git a/cells/a221o/sky130_fd_sc_ls__a221o_4.spice b/cells/a221o/sky130_fd_sc_ls__a221o_4.spice
index 719b59d..612dc31 100644
--- a/cells/a221o/sky130_fd_sc_ls__a221o_4.spice
+++ b/cells/a221o/sky130_fd_sc_ls__a221o_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a221o_4.spice
-* Created: Fri Aug 28 12:53:08 2020
+* Created: Wed Sep 2 10:49:20 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a221oi/sky130_fd_sc_ls__a221oi_1.lvs.report b/cells/a221oi/sky130_fd_sc_ls__a221oi_1.lvs.report
new file mode 100644
index 0000000..fcc4358
--- /dev/null
+++ b/cells/a221oi/sky130_fd_sc_ls__a221oi_1.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__a221oi_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__a221oi_1.sp ('sky130_fd_sc_ls__a221oi_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/a221oi/sky130_fd_sc_ls__a221oi_1.spice ('sky130_fd_sc_ls__a221oi_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:49:23 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__a221oi_1 sky130_fd_sc_ls__a221oi_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__a221oi_1
+SOURCE CELL NAME: sky130_fd_sc_ls__a221oi_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 14 14
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 10 10
+
+ Instances: 1 1 MN (4 pins)
+ 2 2 SMN2 (4 pins)
+ 1 1 SPMP_2_2_1 (7 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 2 2 0 0 SMN2
+ 1 1 0 0 SPMP_2_2_1
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB C1 B2 B1 A1 A2 Y VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a221oi/sky130_fd_sc_ls__a221oi_1.pex.spice b/cells/a221oi/sky130_fd_sc_ls__a221oi_1.pex.spice
index 921ff2e..beb2fd7 100644
--- a/cells/a221oi/sky130_fd_sc_ls__a221oi_1.pex.spice
+++ b/cells/a221oi/sky130_fd_sc_ls__a221oi_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a221oi_1.pex.spice
-* Created: Fri Aug 28 12:53:17 2020
+* Created: Wed Sep 2 10:49:26 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a221oi/sky130_fd_sc_ls__a221oi_1.pxi.spice b/cells/a221oi/sky130_fd_sc_ls__a221oi_1.pxi.spice
index eddc3ba..66b5d15 100644
--- a/cells/a221oi/sky130_fd_sc_ls__a221oi_1.pxi.spice
+++ b/cells/a221oi/sky130_fd_sc_ls__a221oi_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a221oi_1.pxi.spice
-* Created: Fri Aug 28 12:53:17 2020
+* Created: Wed Sep 2 10:49:26 2020
*
x_PM_SKY130_FD_SC_LS__A221OI_1%C1 N_C1_c_56_n N_C1_M1006_g N_C1_M1003_g C1
+ N_C1_c_54_n N_C1_c_55_n PM_SKY130_FD_SC_LS__A221OI_1%C1
diff --git a/cells/a221oi/sky130_fd_sc_ls__a221oi_1.spice b/cells/a221oi/sky130_fd_sc_ls__a221oi_1.spice
index 2360974..3d77205 100644
--- a/cells/a221oi/sky130_fd_sc_ls__a221oi_1.spice
+++ b/cells/a221oi/sky130_fd_sc_ls__a221oi_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a221oi_1.spice
-* Created: Fri Aug 28 12:53:17 2020
+* Created: Wed Sep 2 10:49:26 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a221oi/sky130_fd_sc_ls__a221oi_2.lvs.report b/cells/a221oi/sky130_fd_sc_ls__a221oi_2.lvs.report
new file mode 100644
index 0000000..c7cfbdc
--- /dev/null
+++ b/cells/a221oi/sky130_fd_sc_ls__a221oi_2.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__a221oi_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__a221oi_2.sp ('sky130_fd_sc_ls__a221oi_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/a221oi/sky130_fd_sc_ls__a221oi_2.spice ('sky130_fd_sc_ls__a221oi_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:49:30 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__a221oi_2 sky130_fd_sc_ls__a221oi_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__a221oi_2
+SOURCE CELL NAME: sky130_fd_sc_ls__a221oi_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 14 14
+
+ Instances: 10 10 MN (4 pins)
+ 10 10 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 21 20
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 10 10
+
+ Instances: 1 1 MN (4 pins)
+ 2 2 SMN2 (4 pins)
+ 1 1 SPMP_2_2_1 (7 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 2 2 0 0 SMN2
+ 1 1 0 0 SPMP_2_2_1
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 20 layout mos transistors were reduced to 10.
+ 10 mos transistors were deleted by parallel reduction.
+ 20 source mos transistors were reduced to 10.
+ 10 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB C1 B1 B2 A1 A2 Y VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a221oi/sky130_fd_sc_ls__a221oi_2.pex.spice b/cells/a221oi/sky130_fd_sc_ls__a221oi_2.pex.spice
index 4c53912..0258572 100644
--- a/cells/a221oi/sky130_fd_sc_ls__a221oi_2.pex.spice
+++ b/cells/a221oi/sky130_fd_sc_ls__a221oi_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a221oi_2.pex.spice
-* Created: Fri Aug 28 12:53:26 2020
+* Created: Wed Sep 2 10:49:32 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a221oi/sky130_fd_sc_ls__a221oi_2.pxi.spice b/cells/a221oi/sky130_fd_sc_ls__a221oi_2.pxi.spice
index 6b9561e..dc22044 100644
--- a/cells/a221oi/sky130_fd_sc_ls__a221oi_2.pxi.spice
+++ b/cells/a221oi/sky130_fd_sc_ls__a221oi_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a221oi_2.pxi.spice
-* Created: Fri Aug 28 12:53:26 2020
+* Created: Wed Sep 2 10:49:32 2020
*
x_PM_SKY130_FD_SC_LS__A221OI_2%C1 N_C1_c_102_n N_C1_M1016_g N_C1_M1015_g
+ N_C1_c_103_n N_C1_M1017_g N_C1_M1019_g C1 N_C1_c_100_n N_C1_c_101_n
diff --git a/cells/a221oi/sky130_fd_sc_ls__a221oi_2.spice b/cells/a221oi/sky130_fd_sc_ls__a221oi_2.spice
index 6ab754e..caa231f 100644
--- a/cells/a221oi/sky130_fd_sc_ls__a221oi_2.spice
+++ b/cells/a221oi/sky130_fd_sc_ls__a221oi_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a221oi_2.spice
-* Created: Fri Aug 28 12:53:26 2020
+* Created: Wed Sep 2 10:49:32 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a221oi/sky130_fd_sc_ls__a221oi_4.lvs.report b/cells/a221oi/sky130_fd_sc_ls__a221oi_4.lvs.report
new file mode 100644
index 0000000..abadb47
--- /dev/null
+++ b/cells/a221oi/sky130_fd_sc_ls__a221oi_4.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__a221oi_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__a221oi_4.sp ('sky130_fd_sc_ls__a221oi_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/a221oi/sky130_fd_sc_ls__a221oi_4.spice ('sky130_fd_sc_ls__a221oi_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:49:36 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__a221oi_4 sky130_fd_sc_ls__a221oi_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__a221oi_4
+SOURCE CELL NAME: sky130_fd_sc_ls__a221oi_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 14 14
+
+ Instances: 20 20 MN (4 pins)
+ 20 20 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 41 40
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 10 10
+
+ Instances: 1 1 MN (4 pins)
+ 2 2 SMN2 (4 pins)
+ 1 1 SPMP_2_2_1 (7 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 2 2 0 0 SMN2
+ 1 1 0 0 SPMP_2_2_1
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 40 layout mos transistors were reduced to 10.
+ 30 mos transistors were deleted by parallel reduction.
+ 40 source mos transistors were reduced to 10.
+ 30 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB C1 A2 A1 B1 B2 Y VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a221oi/sky130_fd_sc_ls__a221oi_4.pex.spice b/cells/a221oi/sky130_fd_sc_ls__a221oi_4.pex.spice
index a404b63..1572ac3 100644
--- a/cells/a221oi/sky130_fd_sc_ls__a221oi_4.pex.spice
+++ b/cells/a221oi/sky130_fd_sc_ls__a221oi_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a221oi_4.pex.spice
-* Created: Fri Aug 28 12:53:42 2020
+* Created: Wed Sep 2 10:49:39 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a221oi/sky130_fd_sc_ls__a221oi_4.pxi.spice b/cells/a221oi/sky130_fd_sc_ls__a221oi_4.pxi.spice
index 4c0812c..719fe72 100644
--- a/cells/a221oi/sky130_fd_sc_ls__a221oi_4.pxi.spice
+++ b/cells/a221oi/sky130_fd_sc_ls__a221oi_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a221oi_4.pxi.spice
-* Created: Fri Aug 28 12:53:42 2020
+* Created: Wed Sep 2 10:49:39 2020
*
x_PM_SKY130_FD_SC_LS__A221OI_4%C1 N_C1_c_158_n N_C1_M1000_g N_C1_M1014_g
+ N_C1_c_159_n N_C1_M1011_g N_C1_M1024_g N_C1_c_160_n N_C1_M1035_g N_C1_M1028_g
diff --git a/cells/a221oi/sky130_fd_sc_ls__a221oi_4.spice b/cells/a221oi/sky130_fd_sc_ls__a221oi_4.spice
index ac178e3..c54bb09 100644
--- a/cells/a221oi/sky130_fd_sc_ls__a221oi_4.spice
+++ b/cells/a221oi/sky130_fd_sc_ls__a221oi_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a221oi_4.spice
-* Created: Fri Aug 28 12:53:42 2020
+* Created: Wed Sep 2 10:49:39 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a222o/sky130_fd_sc_ls__a222o_1.lvs.report b/cells/a222o/sky130_fd_sc_ls__a222o_1.lvs.report
new file mode 100644
index 0000000..c8e2267
--- /dev/null
+++ b/cells/a222o/sky130_fd_sc_ls__a222o_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__a222o_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__a222o_1.sp ('sky130_fd_sc_ls__a222o_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/a222o/sky130_fd_sc_ls__a222o_1.spice ('sky130_fd_sc_ls__a222o_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:49:43 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__a222o_1 sky130_fd_sc_ls__a222o_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__a222o_1
+SOURCE CELL NAME: sky130_fd_sc_ls__a222o_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 11 11
+
+ Nets: 17 17
+
+ Instances: 7 7 MN (4 pins)
+ 7 7 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 15 14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 11 11
+
+ Nets: 12 12
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 3 3 SMN2 (4 pins)
+ 1 1 SPMP_2_2_2 (8 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 11 11 0 0
+
+ Nets: 12 12 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 3 3 0 0 SMN2
+ 1 1 0 0 SPMP_2_2_2
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB C1 C2 B2 B1 A1 A2 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a222o/sky130_fd_sc_ls__a222o_1.pex.spice b/cells/a222o/sky130_fd_sc_ls__a222o_1.pex.spice
index 435aafa..55de8e2 100644
--- a/cells/a222o/sky130_fd_sc_ls__a222o_1.pex.spice
+++ b/cells/a222o/sky130_fd_sc_ls__a222o_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a222o_1.pex.spice
-* Created: Fri Aug 28 12:54:02 2020
+* Created: Wed Sep 2 10:49:46 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a222o/sky130_fd_sc_ls__a222o_1.pxi.spice b/cells/a222o/sky130_fd_sc_ls__a222o_1.pxi.spice
index b099352..43ea2d6 100644
--- a/cells/a222o/sky130_fd_sc_ls__a222o_1.pxi.spice
+++ b/cells/a222o/sky130_fd_sc_ls__a222o_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a222o_1.pxi.spice
-* Created: Fri Aug 28 12:54:02 2020
+* Created: Wed Sep 2 10:49:46 2020
*
x_PM_SKY130_FD_SC_LS__A222O_1%C1 N_C1_c_85_n N_C1_c_90_n N_C1_M1009_g
+ N_C1_M1006_g C1 C1 N_C1_c_86_n N_C1_c_87_n N_C1_c_88_n
diff --git a/cells/a222o/sky130_fd_sc_ls__a222o_1.spice b/cells/a222o/sky130_fd_sc_ls__a222o_1.spice
index 8ea34d8..2fed47f 100644
--- a/cells/a222o/sky130_fd_sc_ls__a222o_1.spice
+++ b/cells/a222o/sky130_fd_sc_ls__a222o_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a222o_1.spice
-* Created: Fri Aug 28 12:54:02 2020
+* Created: Wed Sep 2 10:49:46 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a222o/sky130_fd_sc_ls__a222o_2.lvs.report b/cells/a222o/sky130_fd_sc_ls__a222o_2.lvs.report
new file mode 100644
index 0000000..1a678f9
--- /dev/null
+++ b/cells/a222o/sky130_fd_sc_ls__a222o_2.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__a222o_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__a222o_2.sp ('sky130_fd_sc_ls__a222o_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/a222o/sky130_fd_sc_ls__a222o_2.spice ('sky130_fd_sc_ls__a222o_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:49:49 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__a222o_2 sky130_fd_sc_ls__a222o_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__a222o_2
+SOURCE CELL NAME: sky130_fd_sc_ls__a222o_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 11 11
+
+ Nets: 17 17
+
+ Instances: 8 8 MN (4 pins)
+ 8 8 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 17 16
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 11 11
+
+ Nets: 12 12
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 3 3 SMN2 (4 pins)
+ 1 1 SPMP_2_2_2 (8 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 11 11 0 0
+
+ Nets: 12 12 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 3 3 0 0 SMN2
+ 1 1 0 0 SPMP_2_2_2
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB C1 C2 A1 B1 B2 A2 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a222o/sky130_fd_sc_ls__a222o_2.pex.spice b/cells/a222o/sky130_fd_sc_ls__a222o_2.pex.spice
index 6b3e4a9..6650da7 100644
--- a/cells/a222o/sky130_fd_sc_ls__a222o_2.pex.spice
+++ b/cells/a222o/sky130_fd_sc_ls__a222o_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a222o_2.pex.spice
-* Created: Fri Aug 28 12:54:12 2020
+* Created: Wed Sep 2 10:49:52 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a222o/sky130_fd_sc_ls__a222o_2.pxi.spice b/cells/a222o/sky130_fd_sc_ls__a222o_2.pxi.spice
index 50c88fa..5110677 100644
--- a/cells/a222o/sky130_fd_sc_ls__a222o_2.pxi.spice
+++ b/cells/a222o/sky130_fd_sc_ls__a222o_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a222o_2.pxi.spice
-* Created: Fri Aug 28 12:54:12 2020
+* Created: Wed Sep 2 10:49:52 2020
*
x_PM_SKY130_FD_SC_LS__A222O_2%C1 N_C1_M1001_g N_C1_M1013_g N_C1_c_91_n
+ N_C1_c_95_n C1 N_C1_c_92_n N_C1_c_93_n PM_SKY130_FD_SC_LS__A222O_2%C1
diff --git a/cells/a222o/sky130_fd_sc_ls__a222o_2.spice b/cells/a222o/sky130_fd_sc_ls__a222o_2.spice
index bc1da91..a4cd8a2 100644
--- a/cells/a222o/sky130_fd_sc_ls__a222o_2.spice
+++ b/cells/a222o/sky130_fd_sc_ls__a222o_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a222o_2.spice
-* Created: Fri Aug 28 12:54:12 2020
+* Created: Wed Sep 2 10:49:52 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a222oi/sky130_fd_sc_ls__a222oi_1.lvs.report b/cells/a222oi/sky130_fd_sc_ls__a222oi_1.lvs.report
new file mode 100644
index 0000000..c1deb5a
--- /dev/null
+++ b/cells/a222oi/sky130_fd_sc_ls__a222oi_1.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__a222oi_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__a222oi_1.sp ('sky130_fd_sc_ls__a222oi_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/a222oi/sky130_fd_sc_ls__a222oi_1.spice ('sky130_fd_sc_ls__a222oi_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:49:56 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__a222oi_1 sky130_fd_sc_ls__a222oi_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__a222oi_1
+SOURCE CELL NAME: sky130_fd_sc_ls__a222oi_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 11 11
+
+ Nets: 16 16
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 11 11
+
+ Nets: 11 11
+
+ Instances: 3 3 SMN2 (4 pins)
+ 1 1 SPMP_2_2_2 (8 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 11 11 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 3 3 0 0 SMN2
+ 1 1 0 0 SPMP_2_2_2
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB C1 C2 B2 B1 A1 A2 Y VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a222oi/sky130_fd_sc_ls__a222oi_1.pex.spice b/cells/a222oi/sky130_fd_sc_ls__a222oi_1.pex.spice
index 0a481c1..adc71bb 100644
--- a/cells/a222oi/sky130_fd_sc_ls__a222oi_1.pex.spice
+++ b/cells/a222oi/sky130_fd_sc_ls__a222oi_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a222oi_1.pex.spice
-* Created: Fri Aug 28 12:54:21 2020
+* Created: Wed Sep 2 10:49:58 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a222oi/sky130_fd_sc_ls__a222oi_1.pxi.spice b/cells/a222oi/sky130_fd_sc_ls__a222oi_1.pxi.spice
index 0df9f56..9554fa0 100644
--- a/cells/a222oi/sky130_fd_sc_ls__a222oi_1.pxi.spice
+++ b/cells/a222oi/sky130_fd_sc_ls__a222oi_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a222oi_1.pxi.spice
-* Created: Fri Aug 28 12:54:21 2020
+* Created: Wed Sep 2 10:49:58 2020
*
x_PM_SKY130_FD_SC_LS__A222OI_1%C1 N_C1_c_70_n N_C1_c_75_n N_C1_M1009_g
+ N_C1_M1002_g C1 N_C1_c_71_n N_C1_c_72_n N_C1_c_73_n
diff --git a/cells/a222oi/sky130_fd_sc_ls__a222oi_1.spice b/cells/a222oi/sky130_fd_sc_ls__a222oi_1.spice
index 0f041b9..33a13c1 100644
--- a/cells/a222oi/sky130_fd_sc_ls__a222oi_1.spice
+++ b/cells/a222oi/sky130_fd_sc_ls__a222oi_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a222oi_1.spice
-* Created: Fri Aug 28 12:54:21 2020
+* Created: Wed Sep 2 10:49:58 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a222oi/sky130_fd_sc_ls__a222oi_2.lvs.report b/cells/a222oi/sky130_fd_sc_ls__a222oi_2.lvs.report
new file mode 100644
index 0000000..7181062
--- /dev/null
+++ b/cells/a222oi/sky130_fd_sc_ls__a222oi_2.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__a222oi_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__a222oi_2.sp ('sky130_fd_sc_ls__a222oi_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/a222oi/sky130_fd_sc_ls__a222oi_2.spice ('sky130_fd_sc_ls__a222oi_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:50:02 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__a222oi_2 sky130_fd_sc_ls__a222oi_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__a222oi_2
+SOURCE CELL NAME: sky130_fd_sc_ls__a222oi_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 11 11
+
+ Nets: 16 16
+
+ Instances: 12 12 MN (4 pins)
+ 12 12 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 25 24
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 11 11
+
+ Nets: 11 11
+
+ Instances: 3 3 SMN2 (4 pins)
+ 1 1 SPMP_2_2_2 (8 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 11 11 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 3 3 0 0 SMN2
+ 1 1 0 0 SPMP_2_2_2
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 24 layout mos transistors were reduced to 12.
+ 12 mos transistors were deleted by parallel reduction.
+ 24 source mos transistors were reduced to 12.
+ 12 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB C2 C1 B1 B2 A1 A2 Y VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a222oi/sky130_fd_sc_ls__a222oi_2.pex.spice b/cells/a222oi/sky130_fd_sc_ls__a222oi_2.pex.spice
index 0024462..f587d6a 100644
--- a/cells/a222oi/sky130_fd_sc_ls__a222oi_2.pex.spice
+++ b/cells/a222oi/sky130_fd_sc_ls__a222oi_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a222oi_2.pex.spice
-* Created: Fri Aug 28 12:54:30 2020
+* Created: Wed Sep 2 10:50:05 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a222oi/sky130_fd_sc_ls__a222oi_2.pxi.spice b/cells/a222oi/sky130_fd_sc_ls__a222oi_2.pxi.spice
index 779edbc..3f7975c 100644
--- a/cells/a222oi/sky130_fd_sc_ls__a222oi_2.pxi.spice
+++ b/cells/a222oi/sky130_fd_sc_ls__a222oi_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a222oi_2.pxi.spice
-* Created: Fri Aug 28 12:54:30 2020
+* Created: Wed Sep 2 10:50:05 2020
*
x_PM_SKY130_FD_SC_LS__A222OI_2%C2 N_C2_c_126_n N_C2_c_136_n N_C2_M1010_g
+ N_C2_M1006_g N_C2_c_137_n N_C2_M1016_g N_C2_M1008_g N_C2_c_128_n N_C2_c_129_n
diff --git a/cells/a222oi/sky130_fd_sc_ls__a222oi_2.spice b/cells/a222oi/sky130_fd_sc_ls__a222oi_2.spice
index df60b4a..147b43e 100644
--- a/cells/a222oi/sky130_fd_sc_ls__a222oi_2.spice
+++ b/cells/a222oi/sky130_fd_sc_ls__a222oi_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a222oi_2.spice
-* Created: Fri Aug 28 12:54:30 2020
+* Created: Wed Sep 2 10:50:05 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a22o/sky130_fd_sc_ls__a22o_1.lvs.report b/cells/a22o/sky130_fd_sc_ls__a22o_1.lvs.report
new file mode 100644
index 0000000..6a5690d
--- /dev/null
+++ b/cells/a22o/sky130_fd_sc_ls__a22o_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__a22o_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__a22o_1.sp ('sky130_fd_sc_ls__a22o_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/a22o/sky130_fd_sc_ls__a22o_1.spice ('sky130_fd_sc_ls__a22o_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:50:08 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__a22o_1 sky130_fd_sc_ls__a22o_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__a22o_1
+SOURCE CELL NAME: sky130_fd_sc_ls__a22o_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ 1 1 SPMP_2_2 (6 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ 1 1 0 0 SPMP_2_2
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A2 B2 B1 A1 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a22o/sky130_fd_sc_ls__a22o_1.pex.spice b/cells/a22o/sky130_fd_sc_ls__a22o_1.pex.spice
index 8f7ba8c..4de8848 100644
--- a/cells/a22o/sky130_fd_sc_ls__a22o_1.pex.spice
+++ b/cells/a22o/sky130_fd_sc_ls__a22o_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a22o_1.pex.spice
-* Created: Fri Aug 28 12:54:46 2020
+* Created: Wed Sep 2 10:50:11 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a22o/sky130_fd_sc_ls__a22o_1.pxi.spice b/cells/a22o/sky130_fd_sc_ls__a22o_1.pxi.spice
index 51204be..d118d4b 100644
--- a/cells/a22o/sky130_fd_sc_ls__a22o_1.pxi.spice
+++ b/cells/a22o/sky130_fd_sc_ls__a22o_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a22o_1.pxi.spice
-* Created: Fri Aug 28 12:54:46 2020
+* Created: Wed Sep 2 10:50:11 2020
*
x_PM_SKY130_FD_SC_LS__A22O_1%A2 N_A2_c_57_n N_A2_c_58_n N_A2_c_63_n N_A2_M1004_g
+ N_A2_M1000_g A2 N_A2_c_61_n PM_SKY130_FD_SC_LS__A22O_1%A2
diff --git a/cells/a22o/sky130_fd_sc_ls__a22o_1.spice b/cells/a22o/sky130_fd_sc_ls__a22o_1.spice
index be93c91..5b216ba 100644
--- a/cells/a22o/sky130_fd_sc_ls__a22o_1.spice
+++ b/cells/a22o/sky130_fd_sc_ls__a22o_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a22o_1.spice
-* Created: Fri Aug 28 12:54:46 2020
+* Created: Wed Sep 2 10:50:11 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a22o/sky130_fd_sc_ls__a22o_2.lvs.report b/cells/a22o/sky130_fd_sc_ls__a22o_2.lvs.report
new file mode 100644
index 0000000..7934362
--- /dev/null
+++ b/cells/a22o/sky130_fd_sc_ls__a22o_2.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__a22o_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__a22o_2.sp ('sky130_fd_sc_ls__a22o_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/a22o/sky130_fd_sc_ls__a22o_2.spice ('sky130_fd_sc_ls__a22o_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:50:15 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__a22o_2 sky130_fd_sc_ls__a22o_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__a22o_2
+SOURCE CELL NAME: sky130_fd_sc_ls__a22o_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ 1 1 SPMP_2_2 (6 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ 1 1 0 0 SPMP_2_2
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1 B1 B2 A2 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a22o/sky130_fd_sc_ls__a22o_2.pex.spice b/cells/a22o/sky130_fd_sc_ls__a22o_2.pex.spice
index 989c333..727c11e 100644
--- a/cells/a22o/sky130_fd_sc_ls__a22o_2.pex.spice
+++ b/cells/a22o/sky130_fd_sc_ls__a22o_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a22o_2.pex.spice
-* Created: Fri Aug 28 12:55:06 2020
+* Created: Wed Sep 2 10:50:18 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a22o/sky130_fd_sc_ls__a22o_2.pxi.spice b/cells/a22o/sky130_fd_sc_ls__a22o_2.pxi.spice
index d7e98d7..2a0eee2 100644
--- a/cells/a22o/sky130_fd_sc_ls__a22o_2.pxi.spice
+++ b/cells/a22o/sky130_fd_sc_ls__a22o_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a22o_2.pxi.spice
-* Created: Fri Aug 28 12:55:06 2020
+* Created: Wed Sep 2 10:50:18 2020
*
x_PM_SKY130_FD_SC_LS__A22O_2%A_81_48# N_A_81_48#_M1007_d N_A_81_48#_M1001_d
+ N_A_81_48#_c_66_n N_A_81_48#_M1008_g N_A_81_48#_c_73_n N_A_81_48#_M1002_g
diff --git a/cells/a22o/sky130_fd_sc_ls__a22o_2.spice b/cells/a22o/sky130_fd_sc_ls__a22o_2.spice
index 238c583..8bb3b5e 100644
--- a/cells/a22o/sky130_fd_sc_ls__a22o_2.spice
+++ b/cells/a22o/sky130_fd_sc_ls__a22o_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a22o_2.spice
-* Created: Fri Aug 28 12:55:06 2020
+* Created: Wed Sep 2 10:50:18 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a22o/sky130_fd_sc_ls__a22o_4.lvs.report b/cells/a22o/sky130_fd_sc_ls__a22o_4.lvs.report
new file mode 100644
index 0000000..3056a0f
--- /dev/null
+++ b/cells/a22o/sky130_fd_sc_ls__a22o_4.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__a22o_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__a22o_4.sp ('sky130_fd_sc_ls__a22o_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/a22o/sky130_fd_sc_ls__a22o_4.spice ('sky130_fd_sc_ls__a22o_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:50:21 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__a22o_4 sky130_fd_sc_ls__a22o_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__a22o_4
+SOURCE CELL NAME: sky130_fd_sc_ls__a22o_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 12 12 MN (4 pins)
+ 12 12 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 25 24
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ 1 1 SPMP_2_2 (6 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ 1 1 0 0 SPMP_2_2
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 24 layout mos transistors were reduced to 10.
+ 14 mos transistors were deleted by parallel reduction.
+ 24 source mos transistors were reduced to 10.
+ 14 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B2 B1 A1 A2 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a22o/sky130_fd_sc_ls__a22o_4.pex.spice b/cells/a22o/sky130_fd_sc_ls__a22o_4.pex.spice
index b03d81b..2ffa7a9 100644
--- a/cells/a22o/sky130_fd_sc_ls__a22o_4.pex.spice
+++ b/cells/a22o/sky130_fd_sc_ls__a22o_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a22o_4.pex.spice
-* Created: Fri Aug 28 12:55:16 2020
+* Created: Wed Sep 2 10:50:24 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a22o/sky130_fd_sc_ls__a22o_4.pxi.spice b/cells/a22o/sky130_fd_sc_ls__a22o_4.pxi.spice
index 3f1a3ee..bf4f3c1 100644
--- a/cells/a22o/sky130_fd_sc_ls__a22o_4.pxi.spice
+++ b/cells/a22o/sky130_fd_sc_ls__a22o_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a22o_4.pxi.spice
-* Created: Fri Aug 28 12:55:16 2020
+* Created: Wed Sep 2 10:50:24 2020
*
x_PM_SKY130_FD_SC_LS__A22O_4%A_95_306# N_A_95_306#_M1000_d N_A_95_306#_M1003_d
+ N_A_95_306#_M1009_d N_A_95_306#_M1014_d N_A_95_306#_c_147_n
diff --git a/cells/a22o/sky130_fd_sc_ls__a22o_4.spice b/cells/a22o/sky130_fd_sc_ls__a22o_4.spice
index 5e778fe..11821b3 100644
--- a/cells/a22o/sky130_fd_sc_ls__a22o_4.spice
+++ b/cells/a22o/sky130_fd_sc_ls__a22o_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a22o_4.spice
-* Created: Fri Aug 28 12:55:16 2020
+* Created: Wed Sep 2 10:50:24 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a22oi/sky130_fd_sc_ls__a22oi_1.lvs.report b/cells/a22oi/sky130_fd_sc_ls__a22oi_1.lvs.report
new file mode 100644
index 0000000..d544f5f
--- /dev/null
+++ b/cells/a22oi/sky130_fd_sc_ls__a22oi_1.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__a22oi_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__a22oi_1.sp ('sky130_fd_sc_ls__a22oi_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/a22oi/sky130_fd_sc_ls__a22oi_1.spice ('sky130_fd_sc_ls__a22oi_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:50:28 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__a22oi_1 sky130_fd_sc_ls__a22oi_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__a22oi_1
+SOURCE CELL NAME: sky130_fd_sc_ls__a22oi_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 12 12
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 9 9
+
+ Instances: 2 2 SMN2 (4 pins)
+ 1 1 SPMP_2_2 (6 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 2 2 0 0 SMN2
+ 1 1 0 0 SPMP_2_2
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B2 B1 A1 A2 Y VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a22oi/sky130_fd_sc_ls__a22oi_1.pex.spice b/cells/a22oi/sky130_fd_sc_ls__a22oi_1.pex.spice
index f0b5313..8d86fc7 100644
--- a/cells/a22oi/sky130_fd_sc_ls__a22oi_1.pex.spice
+++ b/cells/a22oi/sky130_fd_sc_ls__a22oi_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a22oi_1.pex.spice
-* Created: Fri Aug 28 12:55:25 2020
+* Created: Wed Sep 2 10:50:31 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a22oi/sky130_fd_sc_ls__a22oi_1.pxi.spice b/cells/a22oi/sky130_fd_sc_ls__a22oi_1.pxi.spice
index a3e3b09..25ab2fc 100644
--- a/cells/a22oi/sky130_fd_sc_ls__a22oi_1.pxi.spice
+++ b/cells/a22oi/sky130_fd_sc_ls__a22oi_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a22oi_1.pxi.spice
-* Created: Fri Aug 28 12:55:25 2020
+* Created: Wed Sep 2 10:50:31 2020
*
x_PM_SKY130_FD_SC_LS__A22OI_1%B2 N_B2_c_49_n N_B2_M1004_g N_B2_M1001_g
+ N_B2_c_46_n N_B2_c_47_n B2 B2 PM_SKY130_FD_SC_LS__A22OI_1%B2
diff --git a/cells/a22oi/sky130_fd_sc_ls__a22oi_1.spice b/cells/a22oi/sky130_fd_sc_ls__a22oi_1.spice
index 1dd6843..f7e9aa5 100644
--- a/cells/a22oi/sky130_fd_sc_ls__a22oi_1.spice
+++ b/cells/a22oi/sky130_fd_sc_ls__a22oi_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a22oi_1.spice
-* Created: Fri Aug 28 12:55:25 2020
+* Created: Wed Sep 2 10:50:31 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a22oi/sky130_fd_sc_ls__a22oi_2.lvs.report b/cells/a22oi/sky130_fd_sc_ls__a22oi_2.lvs.report
new file mode 100644
index 0000000..379c0a9
--- /dev/null
+++ b/cells/a22oi/sky130_fd_sc_ls__a22oi_2.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__a22oi_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__a22oi_2.sp ('sky130_fd_sc_ls__a22oi_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/a22oi/sky130_fd_sc_ls__a22oi_2.spice ('sky130_fd_sc_ls__a22oi_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:50:34 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__a22oi_2 sky130_fd_sc_ls__a22oi_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__a22oi_2
+SOURCE CELL NAME: sky130_fd_sc_ls__a22oi_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 12 12
+
+ Instances: 8 8 MN (4 pins)
+ 8 8 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 17 16
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 9 9
+
+ Instances: 2 2 SMN2 (4 pins)
+ 1 1 SPMP_2_2 (6 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 2 2 0 0 SMN2
+ 1 1 0 0 SPMP_2_2
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 16 layout mos transistors were reduced to 8.
+ 8 mos transistors were deleted by parallel reduction.
+ 16 source mos transistors were reduced to 8.
+ 8 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1 A2 B1 B2 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a22oi/sky130_fd_sc_ls__a22oi_2.pex.spice b/cells/a22oi/sky130_fd_sc_ls__a22oi_2.pex.spice
index 882fc39..ad26e45 100644
--- a/cells/a22oi/sky130_fd_sc_ls__a22oi_2.pex.spice
+++ b/cells/a22oi/sky130_fd_sc_ls__a22oi_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a22oi_2.pex.spice
-* Created: Fri Aug 28 12:55:34 2020
+* Created: Wed Sep 2 10:50:37 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a22oi/sky130_fd_sc_ls__a22oi_2.pxi.spice b/cells/a22oi/sky130_fd_sc_ls__a22oi_2.pxi.spice
index 3569c0b..a84d290 100644
--- a/cells/a22oi/sky130_fd_sc_ls__a22oi_2.pxi.spice
+++ b/cells/a22oi/sky130_fd_sc_ls__a22oi_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a22oi_2.pxi.spice
-* Created: Fri Aug 28 12:55:34 2020
+* Created: Wed Sep 2 10:50:37 2020
*
x_PM_SKY130_FD_SC_LS__A22OI_2%A1 N_A1_M1001_g N_A1_c_81_n N_A1_M1002_g
+ N_A1_M1014_g N_A1_c_87_n N_A1_M1008_g N_A1_c_83_n N_A1_c_89_n N_A1_c_96_p
diff --git a/cells/a22oi/sky130_fd_sc_ls__a22oi_2.spice b/cells/a22oi/sky130_fd_sc_ls__a22oi_2.spice
index d15ea67..6674860 100644
--- a/cells/a22oi/sky130_fd_sc_ls__a22oi_2.spice
+++ b/cells/a22oi/sky130_fd_sc_ls__a22oi_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a22oi_2.spice
-* Created: Fri Aug 28 12:55:34 2020
+* Created: Wed Sep 2 10:50:37 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a22oi/sky130_fd_sc_ls__a22oi_4.lvs.report b/cells/a22oi/sky130_fd_sc_ls__a22oi_4.lvs.report
new file mode 100644
index 0000000..2ec4d11
--- /dev/null
+++ b/cells/a22oi/sky130_fd_sc_ls__a22oi_4.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__a22oi_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__a22oi_4.sp ('sky130_fd_sc_ls__a22oi_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/a22oi/sky130_fd_sc_ls__a22oi_4.spice ('sky130_fd_sc_ls__a22oi_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:50:41 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__a22oi_4 sky130_fd_sc_ls__a22oi_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__a22oi_4
+SOURCE CELL NAME: sky130_fd_sc_ls__a22oi_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 12 12
+
+ Instances: 16 16 MN (4 pins)
+ 16 16 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 33 32
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 9 9
+
+ Instances: 2 2 SMN2 (4 pins)
+ 1 1 SPMP_2_2 (6 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 2 2 0 0 SMN2
+ 1 1 0 0 SPMP_2_2
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 32 layout mos transistors were reduced to 8.
+ 24 mos transistors were deleted by parallel reduction.
+ 32 source mos transistors were reduced to 8.
+ 24 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B2 B1 A1 A2 Y VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a22oi/sky130_fd_sc_ls__a22oi_4.pex.spice b/cells/a22oi/sky130_fd_sc_ls__a22oi_4.pex.spice
index 63adc85..4f23838 100644
--- a/cells/a22oi/sky130_fd_sc_ls__a22oi_4.pex.spice
+++ b/cells/a22oi/sky130_fd_sc_ls__a22oi_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a22oi_4.pex.spice
-* Created: Fri Aug 28 12:55:50 2020
+* Created: Wed Sep 2 10:50:44 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a22oi/sky130_fd_sc_ls__a22oi_4.pxi.spice b/cells/a22oi/sky130_fd_sc_ls__a22oi_4.pxi.spice
index 7647071..f598937 100644
--- a/cells/a22oi/sky130_fd_sc_ls__a22oi_4.pxi.spice
+++ b/cells/a22oi/sky130_fd_sc_ls__a22oi_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a22oi_4.pxi.spice
-* Created: Fri Aug 28 12:55:50 2020
+* Created: Wed Sep 2 10:50:44 2020
*
x_PM_SKY130_FD_SC_LS__A22OI_4%B2 N_B2_c_125_n N_B2_M1005_g N_B2_M1007_g
+ N_B2_M1013_g N_B2_c_126_n N_B2_M1010_g N_B2_M1017_g N_B2_c_127_n N_B2_M1011_g
diff --git a/cells/a22oi/sky130_fd_sc_ls__a22oi_4.spice b/cells/a22oi/sky130_fd_sc_ls__a22oi_4.spice
index a87dd3c..ba13e42 100644
--- a/cells/a22oi/sky130_fd_sc_ls__a22oi_4.spice
+++ b/cells/a22oi/sky130_fd_sc_ls__a22oi_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a22oi_4.spice
-* Created: Fri Aug 28 12:55:50 2020
+* Created: Wed Sep 2 10:50:44 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a2bb2o/sky130_fd_sc_ls__a2bb2o_1.lvs.report b/cells/a2bb2o/sky130_fd_sc_ls__a2bb2o_1.lvs.report
new file mode 100644
index 0000000..24ffdb3
--- /dev/null
+++ b/cells/a2bb2o/sky130_fd_sc_ls__a2bb2o_1.lvs.report
@@ -0,0 +1,470 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__a2bb2o_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__a2bb2o_1.sp ('sky130_fd_sc_ls__a2bb2o_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/a2bb2o/sky130_fd_sc_ls__a2bb2o_1.spice ('sky130_fd_sc_ls__a2bb2o_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:50:47 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__a2bb2o_1 sky130_fd_sc_ls__a2bb2o_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__a2bb2o_1
+SOURCE CELL NAME: sky130_fd_sc_ls__a2bb2o_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 14 14
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 11 11
+
+ Instances: 4 4 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMP_2_1 (5 pins)
+ ------ ------
+ Total Inst: 8 8
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 4 4 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMP_2_1
+ ------- ------- --------- ---------
+ Total Inst: 8 8 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1_N A2_N B2 B1 X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a2bb2o/sky130_fd_sc_ls__a2bb2o_1.pex.spice b/cells/a2bb2o/sky130_fd_sc_ls__a2bb2o_1.pex.spice
index 7ac55a1..8ea2859 100644
--- a/cells/a2bb2o/sky130_fd_sc_ls__a2bb2o_1.pex.spice
+++ b/cells/a2bb2o/sky130_fd_sc_ls__a2bb2o_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a2bb2o_1.pex.spice
-* Created: Fri Aug 28 12:56:10 2020
+* Created: Wed Sep 2 10:50:50 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a2bb2o/sky130_fd_sc_ls__a2bb2o_1.pxi.spice b/cells/a2bb2o/sky130_fd_sc_ls__a2bb2o_1.pxi.spice
index f10d371..fde908b 100644
--- a/cells/a2bb2o/sky130_fd_sc_ls__a2bb2o_1.pxi.spice
+++ b/cells/a2bb2o/sky130_fd_sc_ls__a2bb2o_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a2bb2o_1.pxi.spice
-* Created: Fri Aug 28 12:56:10 2020
+* Created: Wed Sep 2 10:50:50 2020
*
x_PM_SKY130_FD_SC_LS__A2BB2O_1%A_93_264# N_A_93_264#_M1001_d N_A_93_264#_M1004_s
+ N_A_93_264#_c_81_n N_A_93_264#_M1010_g N_A_93_264#_M1007_g N_A_93_264#_c_83_n
diff --git a/cells/a2bb2o/sky130_fd_sc_ls__a2bb2o_1.spice b/cells/a2bb2o/sky130_fd_sc_ls__a2bb2o_1.spice
index 18e347f..408d2b5 100644
--- a/cells/a2bb2o/sky130_fd_sc_ls__a2bb2o_1.spice
+++ b/cells/a2bb2o/sky130_fd_sc_ls__a2bb2o_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a2bb2o_1.spice
-* Created: Fri Aug 28 12:56:10 2020
+* Created: Wed Sep 2 10:50:50 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a2bb2o/sky130_fd_sc_ls__a2bb2o_2.lvs.report b/cells/a2bb2o/sky130_fd_sc_ls__a2bb2o_2.lvs.report
new file mode 100644
index 0000000..6b15135
--- /dev/null
+++ b/cells/a2bb2o/sky130_fd_sc_ls__a2bb2o_2.lvs.report
@@ -0,0 +1,475 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__a2bb2o_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__a2bb2o_2.sp ('sky130_fd_sc_ls__a2bb2o_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/a2bb2o/sky130_fd_sc_ls__a2bb2o_2.spice ('sky130_fd_sc_ls__a2bb2o_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:50:54 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__a2bb2o_2 sky130_fd_sc_ls__a2bb2o_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__a2bb2o_2
+SOURCE CELL NAME: sky130_fd_sc_ls__a2bb2o_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 14 14
+
+ Instances: 7 7 MN (4 pins)
+ 7 7 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 15 14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 11 11
+
+ Instances: 4 4 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMP_2_1 (5 pins)
+ ------ ------
+ Total Inst: 8 8
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 4 4 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMP_2_1
+ ------- ------- --------- ---------
+ Total Inst: 8 8 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1 B2 A2_N A1_N VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a2bb2o/sky130_fd_sc_ls__a2bb2o_2.pex.spice b/cells/a2bb2o/sky130_fd_sc_ls__a2bb2o_2.pex.spice
index 06283be..1bc5d06 100644
--- a/cells/a2bb2o/sky130_fd_sc_ls__a2bb2o_2.pex.spice
+++ b/cells/a2bb2o/sky130_fd_sc_ls__a2bb2o_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a2bb2o_2.pex.spice
-* Created: Fri Aug 28 12:56:19 2020
+* Created: Wed Sep 2 10:50:57 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a2bb2o/sky130_fd_sc_ls__a2bb2o_2.pxi.spice b/cells/a2bb2o/sky130_fd_sc_ls__a2bb2o_2.pxi.spice
index 892d2e8..6fa0149 100644
--- a/cells/a2bb2o/sky130_fd_sc_ls__a2bb2o_2.pxi.spice
+++ b/cells/a2bb2o/sky130_fd_sc_ls__a2bb2o_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a2bb2o_2.pxi.spice
-* Created: Fri Aug 28 12:56:19 2020
+* Created: Wed Sep 2 10:50:57 2020
*
x_PM_SKY130_FD_SC_LS__A2BB2O_2%B1 N_B1_c_89_n N_B1_c_95_n N_B1_M1011_g
+ N_B1_c_90_n N_B1_M1007_g N_B1_c_91_n N_B1_c_92_n B1
diff --git a/cells/a2bb2o/sky130_fd_sc_ls__a2bb2o_2.spice b/cells/a2bb2o/sky130_fd_sc_ls__a2bb2o_2.spice
index e91e4be..2dfa0f8 100644
--- a/cells/a2bb2o/sky130_fd_sc_ls__a2bb2o_2.spice
+++ b/cells/a2bb2o/sky130_fd_sc_ls__a2bb2o_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a2bb2o_2.spice
-* Created: Fri Aug 28 12:56:19 2020
+* Created: Wed Sep 2 10:50:57 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a2bb2o/sky130_fd_sc_ls__a2bb2o_4.lvs.report b/cells/a2bb2o/sky130_fd_sc_ls__a2bb2o_4.lvs.report
new file mode 100644
index 0000000..87fd009
--- /dev/null
+++ b/cells/a2bb2o/sky130_fd_sc_ls__a2bb2o_4.lvs.report
@@ -0,0 +1,475 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__a2bb2o_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__a2bb2o_4.sp ('sky130_fd_sc_ls__a2bb2o_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/a2bb2o/sky130_fd_sc_ls__a2bb2o_4.spice ('sky130_fd_sc_ls__a2bb2o_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:51:00 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__a2bb2o_4 sky130_fd_sc_ls__a2bb2o_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__a2bb2o_4
+SOURCE CELL NAME: sky130_fd_sc_ls__a2bb2o_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 14 14
+
+ Instances: 11 11 MN (4 pins)
+ 12 12 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 24 23
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 11 11
+
+ Instances: 4 4 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMP_2_1 (5 pins)
+ ------ ------
+ Total Inst: 8 8
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 4 4 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMP_2_1
+ ------- ------- --------- ---------
+ Total Inst: 8 8 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 18 layout mos transistors were reduced to 7.
+ 11 mos transistors were deleted by parallel reduction.
+ 18 source mos transistors were reduced to 7.
+ 11 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1_N A2_N B2 B1 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a2bb2o/sky130_fd_sc_ls__a2bb2o_4.pex.spice b/cells/a2bb2o/sky130_fd_sc_ls__a2bb2o_4.pex.spice
index 0431006..34d3d9e 100644
--- a/cells/a2bb2o/sky130_fd_sc_ls__a2bb2o_4.pex.spice
+++ b/cells/a2bb2o/sky130_fd_sc_ls__a2bb2o_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a2bb2o_4.pex.spice
-* Created: Fri Aug 28 12:56:28 2020
+* Created: Wed Sep 2 10:51:03 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a2bb2o/sky130_fd_sc_ls__a2bb2o_4.pxi.spice b/cells/a2bb2o/sky130_fd_sc_ls__a2bb2o_4.pxi.spice
index ce8334b..d0ecc5b 100644
--- a/cells/a2bb2o/sky130_fd_sc_ls__a2bb2o_4.pxi.spice
+++ b/cells/a2bb2o/sky130_fd_sc_ls__a2bb2o_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a2bb2o_4.pxi.spice
-* Created: Fri Aug 28 12:56:28 2020
+* Created: Wed Sep 2 10:51:03 2020
*
x_PM_SKY130_FD_SC_LS__A2BB2O_4%A_162_48# N_A_162_48#_M1015_d N_A_162_48#_M1002_s
+ N_A_162_48#_M1006_d N_A_162_48#_M1001_g N_A_162_48#_c_157_n
diff --git a/cells/a2bb2o/sky130_fd_sc_ls__a2bb2o_4.spice b/cells/a2bb2o/sky130_fd_sc_ls__a2bb2o_4.spice
index d8013f7..56ae14f 100644
--- a/cells/a2bb2o/sky130_fd_sc_ls__a2bb2o_4.spice
+++ b/cells/a2bb2o/sky130_fd_sc_ls__a2bb2o_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a2bb2o_4.spice
-* Created: Fri Aug 28 12:56:28 2020
+* Created: Wed Sep 2 10:51:03 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a2bb2oi/sky130_fd_sc_ls__a2bb2oi_1.lvs.report b/cells/a2bb2oi/sky130_fd_sc_ls__a2bb2oi_1.lvs.report
new file mode 100644
index 0000000..f937983
--- /dev/null
+++ b/cells/a2bb2oi/sky130_fd_sc_ls__a2bb2oi_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__a2bb2oi_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__a2bb2oi_1.sp ('sky130_fd_sc_ls__a2bb2oi_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/a2bb2oi/sky130_fd_sc_ls__a2bb2oi_1.spice ('sky130_fd_sc_ls__a2bb2oi_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:51:07 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__a2bb2oi_1 sky130_fd_sc_ls__a2bb2oi_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__a2bb2oi_1
+SOURCE CELL NAME: sky130_fd_sc_ls__a2bb2oi_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 3 3 MN (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMP_2_1 (5 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 3 3 0 0 MN(NSHORT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMP_2_1
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1_N A2_N B2 B1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a2bb2oi/sky130_fd_sc_ls__a2bb2oi_1.pex.spice b/cells/a2bb2oi/sky130_fd_sc_ls__a2bb2oi_1.pex.spice
index f0d4eee..4ea1d6e 100644
--- a/cells/a2bb2oi/sky130_fd_sc_ls__a2bb2oi_1.pex.spice
+++ b/cells/a2bb2oi/sky130_fd_sc_ls__a2bb2oi_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a2bb2oi_1.pex.spice
-* Created: Fri Aug 28 12:56:38 2020
+* Created: Wed Sep 2 10:51:10 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a2bb2oi/sky130_fd_sc_ls__a2bb2oi_1.pxi.spice b/cells/a2bb2oi/sky130_fd_sc_ls__a2bb2oi_1.pxi.spice
index ada10ac..9dfb3a3 100644
--- a/cells/a2bb2oi/sky130_fd_sc_ls__a2bb2oi_1.pxi.spice
+++ b/cells/a2bb2oi/sky130_fd_sc_ls__a2bb2oi_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a2bb2oi_1.pxi.spice
-* Created: Fri Aug 28 12:56:38 2020
+* Created: Wed Sep 2 10:51:10 2020
*
x_PM_SKY130_FD_SC_LS__A2BB2OI_1%A1_N N_A1_N_c_61_n N_A1_N_c_66_n N_A1_N_M1004_g
+ N_A1_N_M1008_g A1_N N_A1_N_c_63_n N_A1_N_c_64_n
diff --git a/cells/a2bb2oi/sky130_fd_sc_ls__a2bb2oi_1.spice b/cells/a2bb2oi/sky130_fd_sc_ls__a2bb2oi_1.spice
index 715301f..00108ee 100644
--- a/cells/a2bb2oi/sky130_fd_sc_ls__a2bb2oi_1.spice
+++ b/cells/a2bb2oi/sky130_fd_sc_ls__a2bb2oi_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a2bb2oi_1.spice
-* Created: Fri Aug 28 12:56:38 2020
+* Created: Wed Sep 2 10:51:10 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a2bb2oi/sky130_fd_sc_ls__a2bb2oi_2.lvs.report b/cells/a2bb2oi/sky130_fd_sc_ls__a2bb2oi_2.lvs.report
new file mode 100644
index 0000000..b0ec8e1
--- /dev/null
+++ b/cells/a2bb2oi/sky130_fd_sc_ls__a2bb2oi_2.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__a2bb2oi_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__a2bb2oi_2.sp ('sky130_fd_sc_ls__a2bb2oi_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/a2bb2oi/sky130_fd_sc_ls__a2bb2oi_2.spice ('sky130_fd_sc_ls__a2bb2oi_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:51:13 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__a2bb2oi_2 sky130_fd_sc_ls__a2bb2oi_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__a2bb2oi_2
+SOURCE CELL NAME: sky130_fd_sc_ls__a2bb2oi_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 8 8 MN (4 pins)
+ 8 8 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 17 16
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 3 3 MN (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMP_2_1 (5 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 3 3 0 0 MN(NSHORT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMP_2_1
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 12 layout mos transistors were reduced to 6.
+ 6 mos transistors were deleted by parallel reduction.
+ 12 source mos transistors were reduced to 6.
+ 6 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1_N A2_N B2 B1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a2bb2oi/sky130_fd_sc_ls__a2bb2oi_2.pex.spice b/cells/a2bb2oi/sky130_fd_sc_ls__a2bb2oi_2.pex.spice
index 53863dd..9306326 100644
--- a/cells/a2bb2oi/sky130_fd_sc_ls__a2bb2oi_2.pex.spice
+++ b/cells/a2bb2oi/sky130_fd_sc_ls__a2bb2oi_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a2bb2oi_2.pex.spice
-* Created: Fri Aug 28 12:56:53 2020
+* Created: Wed Sep 2 10:51:16 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a2bb2oi/sky130_fd_sc_ls__a2bb2oi_2.pxi.spice b/cells/a2bb2oi/sky130_fd_sc_ls__a2bb2oi_2.pxi.spice
index ae8f0af..43fcaa2 100644
--- a/cells/a2bb2oi/sky130_fd_sc_ls__a2bb2oi_2.pxi.spice
+++ b/cells/a2bb2oi/sky130_fd_sc_ls__a2bb2oi_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a2bb2oi_2.pxi.spice
-* Created: Fri Aug 28 12:56:53 2020
+* Created: Wed Sep 2 10:51:16 2020
*
x_PM_SKY130_FD_SC_LS__A2BB2OI_2%A1_N N_A1_N_c_94_n N_A1_N_c_95_n N_A1_N_c_96_n
+ N_A1_N_c_101_n N_A1_N_M1005_g N_A1_N_M1010_g A1_N N_A1_N_c_98_n N_A1_N_c_99_n
diff --git a/cells/a2bb2oi/sky130_fd_sc_ls__a2bb2oi_2.spice b/cells/a2bb2oi/sky130_fd_sc_ls__a2bb2oi_2.spice
index bfa92d3..dd5a0ed 100644
--- a/cells/a2bb2oi/sky130_fd_sc_ls__a2bb2oi_2.spice
+++ b/cells/a2bb2oi/sky130_fd_sc_ls__a2bb2oi_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a2bb2oi_2.spice
-* Created: Fri Aug 28 12:56:53 2020
+* Created: Wed Sep 2 10:51:16 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a2bb2oi/sky130_fd_sc_ls__a2bb2oi_4.lvs.report b/cells/a2bb2oi/sky130_fd_sc_ls__a2bb2oi_4.lvs.report
new file mode 100644
index 0000000..1ba3a82
--- /dev/null
+++ b/cells/a2bb2oi/sky130_fd_sc_ls__a2bb2oi_4.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__a2bb2oi_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__a2bb2oi_4.sp ('sky130_fd_sc_ls__a2bb2oi_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/a2bb2oi/sky130_fd_sc_ls__a2bb2oi_4.spice ('sky130_fd_sc_ls__a2bb2oi_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:51:20 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__a2bb2oi_4 sky130_fd_sc_ls__a2bb2oi_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__a2bb2oi_4
+SOURCE CELL NAME: sky130_fd_sc_ls__a2bb2oi_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 14 14 MN (4 pins)
+ 16 16 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 31 30
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 3 3 MN (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMP_2_1 (5 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 3 3 0 0 MN(NSHORT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMP_2_1
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 28 layout mos transistors were reduced to 8.
+ 20 mos transistors were deleted by parallel reduction.
+ 28 source mos transistors were reduced to 8.
+ 20 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A2_N A1_N B2 B1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a2bb2oi/sky130_fd_sc_ls__a2bb2oi_4.pex.spice b/cells/a2bb2oi/sky130_fd_sc_ls__a2bb2oi_4.pex.spice
index 894d6b4..05b4e21 100644
--- a/cells/a2bb2oi/sky130_fd_sc_ls__a2bb2oi_4.pex.spice
+++ b/cells/a2bb2oi/sky130_fd_sc_ls__a2bb2oi_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a2bb2oi_4.pex.spice
-* Created: Fri Aug 28 12:57:13 2020
+* Created: Wed Sep 2 10:51:23 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a2bb2oi/sky130_fd_sc_ls__a2bb2oi_4.pxi.spice b/cells/a2bb2oi/sky130_fd_sc_ls__a2bb2oi_4.pxi.spice
index 719ef24..fceced8 100644
--- a/cells/a2bb2oi/sky130_fd_sc_ls__a2bb2oi_4.pxi.spice
+++ b/cells/a2bb2oi/sky130_fd_sc_ls__a2bb2oi_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a2bb2oi_4.pxi.spice
-* Created: Fri Aug 28 12:57:13 2020
+* Created: Wed Sep 2 10:51:23 2020
*
x_PM_SKY130_FD_SC_LS__A2BB2OI_4%A2_N N_A2_N_c_147_n N_A2_N_M1026_g
+ N_A2_N_c_148_n N_A2_N_M1027_g N_A2_N_c_142_n N_A2_N_c_143_n N_A2_N_c_144_n
diff --git a/cells/a2bb2oi/sky130_fd_sc_ls__a2bb2oi_4.spice b/cells/a2bb2oi/sky130_fd_sc_ls__a2bb2oi_4.spice
index 3528b84..c6d6714 100644
--- a/cells/a2bb2oi/sky130_fd_sc_ls__a2bb2oi_4.spice
+++ b/cells/a2bb2oi/sky130_fd_sc_ls__a2bb2oi_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a2bb2oi_4.spice
-* Created: Fri Aug 28 12:57:13 2020
+* Created: Wed Sep 2 10:51:23 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a311o/sky130_fd_sc_ls__a311o_1.lvs.report b/cells/a311o/sky130_fd_sc_ls__a311o_1.lvs.report
new file mode 100644
index 0000000..8e3bf2c
--- /dev/null
+++ b/cells/a311o/sky130_fd_sc_ls__a311o_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__a311o_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__a311o_1.sp ('sky130_fd_sc_ls__a311o_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/a311o/sky130_fd_sc_ls__a311o_1.spice ('sky130_fd_sc_ls__a311o_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:51:26 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__a311o_1 sky130_fd_sc_ls__a311o_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__a311o_1
+SOURCE CELL NAME: sky130_fd_sc_ls__a311o_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 15 15
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 11 11
+
+ Instances: 3 3 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMN3 (5 pins)
+ 1 1 SPMP_3_1_1 (7 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 3 3 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN3
+ 1 1 0 0 SPMP_3_1_1
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A3 A2 A1 B1 C1 X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a311o/sky130_fd_sc_ls__a311o_1.pex.spice b/cells/a311o/sky130_fd_sc_ls__a311o_1.pex.spice
index a3cf469..ee42e95 100644
--- a/cells/a311o/sky130_fd_sc_ls__a311o_1.pex.spice
+++ b/cells/a311o/sky130_fd_sc_ls__a311o_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a311o_1.pex.spice
-* Created: Fri Aug 28 12:57:23 2020
+* Created: Wed Sep 2 10:51:29 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a311o/sky130_fd_sc_ls__a311o_1.pxi.spice b/cells/a311o/sky130_fd_sc_ls__a311o_1.pxi.spice
index 6532dc1..48f0d20 100644
--- a/cells/a311o/sky130_fd_sc_ls__a311o_1.pxi.spice
+++ b/cells/a311o/sky130_fd_sc_ls__a311o_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a311o_1.pxi.spice
-* Created: Fri Aug 28 12:57:23 2020
+* Created: Wed Sep 2 10:51:29 2020
*
x_PM_SKY130_FD_SC_LS__A311O_1%A_89_270# N_A_89_270#_M1004_d N_A_89_270#_M1000_d
+ N_A_89_270#_M1007_d N_A_89_270#_c_75_n N_A_89_270#_M1010_g N_A_89_270#_c_76_n
diff --git a/cells/a311o/sky130_fd_sc_ls__a311o_1.spice b/cells/a311o/sky130_fd_sc_ls__a311o_1.spice
index 984db75..fa17f14 100644
--- a/cells/a311o/sky130_fd_sc_ls__a311o_1.spice
+++ b/cells/a311o/sky130_fd_sc_ls__a311o_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a311o_1.spice
-* Created: Fri Aug 28 12:57:23 2020
+* Created: Wed Sep 2 10:51:29 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a311o/sky130_fd_sc_ls__a311o_2.lvs.report b/cells/a311o/sky130_fd_sc_ls__a311o_2.lvs.report
new file mode 100644
index 0000000..4375d1d
--- /dev/null
+++ b/cells/a311o/sky130_fd_sc_ls__a311o_2.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__a311o_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__a311o_2.sp ('sky130_fd_sc_ls__a311o_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/a311o/sky130_fd_sc_ls__a311o_2.spice ('sky130_fd_sc_ls__a311o_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:51:33 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__a311o_2 sky130_fd_sc_ls__a311o_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__a311o_2
+SOURCE CELL NAME: sky130_fd_sc_ls__a311o_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 15 15
+
+ Instances: 7 7 MN (4 pins)
+ 7 7 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 15 14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 11 11
+
+ Instances: 3 3 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMN3 (5 pins)
+ 1 1 SPMP_3_1_1 (7 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 3 3 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN3
+ 1 1 0 0 SPMP_3_1_1
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A3 A2 A1 B1 C1 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a311o/sky130_fd_sc_ls__a311o_2.pex.spice b/cells/a311o/sky130_fd_sc_ls__a311o_2.pex.spice
index f4d0894..1600e29 100644
--- a/cells/a311o/sky130_fd_sc_ls__a311o_2.pex.spice
+++ b/cells/a311o/sky130_fd_sc_ls__a311o_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a311o_2.pex.spice
-* Created: Fri Aug 28 12:57:32 2020
+* Created: Wed Sep 2 10:51:35 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a311o/sky130_fd_sc_ls__a311o_2.pxi.spice b/cells/a311o/sky130_fd_sc_ls__a311o_2.pxi.spice
index 1d19e6d..f5197be 100644
--- a/cells/a311o/sky130_fd_sc_ls__a311o_2.pxi.spice
+++ b/cells/a311o/sky130_fd_sc_ls__a311o_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a311o_2.pxi.spice
-* Created: Fri Aug 28 12:57:32 2020
+* Created: Wed Sep 2 10:51:35 2020
*
x_PM_SKY130_FD_SC_LS__A311O_2%A_21_270# N_A_21_270#_M1012_d N_A_21_270#_M1008_d
+ N_A_21_270#_M1002_d N_A_21_270#_c_93_n N_A_21_270#_M1007_g N_A_21_270#_M1003_g
diff --git a/cells/a311o/sky130_fd_sc_ls__a311o_2.spice b/cells/a311o/sky130_fd_sc_ls__a311o_2.spice
index 7d7cafb..11a1138 100644
--- a/cells/a311o/sky130_fd_sc_ls__a311o_2.spice
+++ b/cells/a311o/sky130_fd_sc_ls__a311o_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a311o_2.spice
-* Created: Fri Aug 28 12:57:32 2020
+* Created: Wed Sep 2 10:51:35 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a311o/sky130_fd_sc_ls__a311o_4.lvs.report b/cells/a311o/sky130_fd_sc_ls__a311o_4.lvs.report
new file mode 100644
index 0000000..6a0f942
--- /dev/null
+++ b/cells/a311o/sky130_fd_sc_ls__a311o_4.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__a311o_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__a311o_4.sp ('sky130_fd_sc_ls__a311o_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/a311o/sky130_fd_sc_ls__a311o_4.spice ('sky130_fd_sc_ls__a311o_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:51:39 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__a311o_4 sky130_fd_sc_ls__a311o_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__a311o_4
+SOURCE CELL NAME: sky130_fd_sc_ls__a311o_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 15 15
+
+ Instances: 14 14 MN (4 pins)
+ 14 14 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 29 28
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 11 11
+
+ Instances: 3 3 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMN3 (5 pins)
+ 1 1 SPMP_3_1_1 (7 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 3 3 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN3
+ 1 1 0 0 SPMP_3_1_1
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 28 layout mos transistors were reduced to 12.
+ 16 mos transistors were deleted by parallel reduction.
+ 28 source mos transistors were reduced to 12.
+ 16 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB C1 B1 A3 A1 A2 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a311o/sky130_fd_sc_ls__a311o_4.pex.spice b/cells/a311o/sky130_fd_sc_ls__a311o_4.pex.spice
index 58b8a0d..efa8d8b 100644
--- a/cells/a311o/sky130_fd_sc_ls__a311o_4.pex.spice
+++ b/cells/a311o/sky130_fd_sc_ls__a311o_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a311o_4.pex.spice
-* Created: Fri Aug 28 12:57:42 2020
+* Created: Wed Sep 2 10:51:42 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a311o/sky130_fd_sc_ls__a311o_4.pxi.spice b/cells/a311o/sky130_fd_sc_ls__a311o_4.pxi.spice
index 18fab96..357da70 100644
--- a/cells/a311o/sky130_fd_sc_ls__a311o_4.pxi.spice
+++ b/cells/a311o/sky130_fd_sc_ls__a311o_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a311o_4.pxi.spice
-* Created: Fri Aug 28 12:57:42 2020
+* Created: Wed Sep 2 10:51:42 2020
*
x_PM_SKY130_FD_SC_LS__A311O_4%C1 N_C1_c_142_n N_C1_M1002_g N_C1_M1015_g
+ N_C1_c_143_n N_C1_M1008_g N_C1_M1024_g C1 N_C1_c_141_n
diff --git a/cells/a311o/sky130_fd_sc_ls__a311o_4.spice b/cells/a311o/sky130_fd_sc_ls__a311o_4.spice
index a6d51de..4fd2cb2 100644
--- a/cells/a311o/sky130_fd_sc_ls__a311o_4.spice
+++ b/cells/a311o/sky130_fd_sc_ls__a311o_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a311o_4.spice
-* Created: Fri Aug 28 12:57:42 2020
+* Created: Wed Sep 2 10:51:42 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a311oi/sky130_fd_sc_ls__a311oi_1.lvs.report b/cells/a311oi/sky130_fd_sc_ls__a311oi_1.lvs.report
new file mode 100644
index 0000000..7305b8e
--- /dev/null
+++ b/cells/a311oi/sky130_fd_sc_ls__a311oi_1.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__a311oi_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__a311oi_1.sp ('sky130_fd_sc_ls__a311oi_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/a311oi/sky130_fd_sc_ls__a311oi_1.spice ('sky130_fd_sc_ls__a311oi_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:51:45 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__a311oi_1 sky130_fd_sc_ls__a311oi_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__a311oi_1
+SOURCE CELL NAME: sky130_fd_sc_ls__a311oi_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 14 14
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 10 10
+
+ Instances: 2 2 MN (4 pins)
+ 1 1 SMN3 (5 pins)
+ 1 1 SPMP_3_1_1 (7 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 1 1 0 0 SMN3
+ 1 1 0 0 SPMP_3_1_1
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A3 A2 A1 B1 C1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a311oi/sky130_fd_sc_ls__a311oi_1.pex.spice b/cells/a311oi/sky130_fd_sc_ls__a311oi_1.pex.spice
index 36800dc..93059fa 100644
--- a/cells/a311oi/sky130_fd_sc_ls__a311oi_1.pex.spice
+++ b/cells/a311oi/sky130_fd_sc_ls__a311oi_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a311oi_1.pex.spice
-* Created: Fri Aug 28 12:57:57 2020
+* Created: Wed Sep 2 10:51:48 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a311oi/sky130_fd_sc_ls__a311oi_1.pxi.spice b/cells/a311oi/sky130_fd_sc_ls__a311oi_1.pxi.spice
index 1402817..ab91a58 100644
--- a/cells/a311oi/sky130_fd_sc_ls__a311oi_1.pxi.spice
+++ b/cells/a311oi/sky130_fd_sc_ls__a311oi_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a311oi_1.pxi.spice
-* Created: Fri Aug 28 12:57:57 2020
+* Created: Wed Sep 2 10:51:48 2020
*
x_PM_SKY130_FD_SC_LS__A311OI_1%A3 N_A3_c_60_n N_A3_M1007_g N_A3_M1002_g
+ N_A3_c_57_n N_A3_c_58_n A3 A3 PM_SKY130_FD_SC_LS__A311OI_1%A3
diff --git a/cells/a311oi/sky130_fd_sc_ls__a311oi_1.spice b/cells/a311oi/sky130_fd_sc_ls__a311oi_1.spice
index 6453129..bb21d16 100644
--- a/cells/a311oi/sky130_fd_sc_ls__a311oi_1.spice
+++ b/cells/a311oi/sky130_fd_sc_ls__a311oi_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a311oi_1.spice
-* Created: Fri Aug 28 12:57:57 2020
+* Created: Wed Sep 2 10:51:48 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a311oi/sky130_fd_sc_ls__a311oi_2.lvs.report b/cells/a311oi/sky130_fd_sc_ls__a311oi_2.lvs.report
new file mode 100644
index 0000000..05d9cb6
--- /dev/null
+++ b/cells/a311oi/sky130_fd_sc_ls__a311oi_2.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__a311oi_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__a311oi_2.sp ('sky130_fd_sc_ls__a311oi_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/a311oi/sky130_fd_sc_ls__a311oi_2.spice ('sky130_fd_sc_ls__a311oi_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:51:52 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__a311oi_2 sky130_fd_sc_ls__a311oi_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__a311oi_2
+SOURCE CELL NAME: sky130_fd_sc_ls__a311oi_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 14 14
+
+ Instances: 8 8 MN (4 pins)
+ 10 10 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 19 18
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 10 10
+
+ Instances: 2 2 MN (4 pins)
+ 1 1 SMN3 (5 pins)
+ 1 1 SPMP_3_1_1 (7 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 1 1 0 0 SMN3
+ 1 1 0 0 SPMP_3_1_1
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 16 layout mos transistors were reduced to 8.
+ 8 mos transistors were deleted by parallel reduction.
+ 16 source mos transistors were reduced to 8.
+ 8 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A3 A2 A1 B1 C1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a311oi/sky130_fd_sc_ls__a311oi_2.pex.spice b/cells/a311oi/sky130_fd_sc_ls__a311oi_2.pex.spice
index 2573c86..5163752 100644
--- a/cells/a311oi/sky130_fd_sc_ls__a311oi_2.pex.spice
+++ b/cells/a311oi/sky130_fd_sc_ls__a311oi_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a311oi_2.pex.spice
-* Created: Fri Aug 28 12:58:17 2020
+* Created: Wed Sep 2 10:51:55 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a311oi/sky130_fd_sc_ls__a311oi_2.pxi.spice b/cells/a311oi/sky130_fd_sc_ls__a311oi_2.pxi.spice
index 19fc668..6d9f65b 100644
--- a/cells/a311oi/sky130_fd_sc_ls__a311oi_2.pxi.spice
+++ b/cells/a311oi/sky130_fd_sc_ls__a311oi_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a311oi_2.pxi.spice
-* Created: Fri Aug 28 12:58:17 2020
+* Created: Wed Sep 2 10:51:55 2020
*
x_PM_SKY130_FD_SC_LS__A311OI_2%A3 N_A3_c_93_n N_A3_M1007_g N_A3_c_89_n
+ N_A3_M1004_g N_A3_c_90_n N_A3_M1005_g N_A3_c_94_n N_A3_M1008_g A3 N_A3_c_92_n
diff --git a/cells/a311oi/sky130_fd_sc_ls__a311oi_2.spice b/cells/a311oi/sky130_fd_sc_ls__a311oi_2.spice
index a10385d..4741178 100644
--- a/cells/a311oi/sky130_fd_sc_ls__a311oi_2.spice
+++ b/cells/a311oi/sky130_fd_sc_ls__a311oi_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a311oi_2.spice
-* Created: Fri Aug 28 12:58:17 2020
+* Created: Wed Sep 2 10:51:55 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a311oi/sky130_fd_sc_ls__a311oi_4.lvs.report b/cells/a311oi/sky130_fd_sc_ls__a311oi_4.lvs.report
new file mode 100644
index 0000000..561669e
--- /dev/null
+++ b/cells/a311oi/sky130_fd_sc_ls__a311oi_4.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__a311oi_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__a311oi_4.sp ('sky130_fd_sc_ls__a311oi_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/a311oi/sky130_fd_sc_ls__a311oi_4.spice ('sky130_fd_sc_ls__a311oi_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:51:59 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__a311oi_4 sky130_fd_sc_ls__a311oi_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__a311oi_4
+SOURCE CELL NAME: sky130_fd_sc_ls__a311oi_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 14 14
+
+ Instances: 16 16 MN (4 pins)
+ 20 20 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 37 36
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 10 10
+
+ Instances: 2 2 MN (4 pins)
+ 1 1 SMN3 (5 pins)
+ 1 1 SPMP_3_1_1 (7 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 1 1 0 0 SMN3
+ 1 1 0 0 SPMP_3_1_1
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 36 layout mos transistors were reduced to 10.
+ 26 mos transistors were deleted by parallel reduction.
+ 36 source mos transistors were reduced to 10.
+ 26 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A3 A2 A1 B1 C1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a311oi/sky130_fd_sc_ls__a311oi_4.pex.spice b/cells/a311oi/sky130_fd_sc_ls__a311oi_4.pex.spice
index dabe87a..396afc1 100644
--- a/cells/a311oi/sky130_fd_sc_ls__a311oi_4.pex.spice
+++ b/cells/a311oi/sky130_fd_sc_ls__a311oi_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a311oi_4.pex.spice
-* Created: Fri Aug 28 12:58:27 2020
+* Created: Wed Sep 2 10:52:02 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a311oi/sky130_fd_sc_ls__a311oi_4.pxi.spice b/cells/a311oi/sky130_fd_sc_ls__a311oi_4.pxi.spice
index 2310d46..7f780b3 100644
--- a/cells/a311oi/sky130_fd_sc_ls__a311oi_4.pxi.spice
+++ b/cells/a311oi/sky130_fd_sc_ls__a311oi_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a311oi_4.pxi.spice
-* Created: Fri Aug 28 12:58:27 2020
+* Created: Wed Sep 2 10:52:02 2020
*
x_PM_SKY130_FD_SC_LS__A311OI_4%A3 N_A3_c_155_n N_A3_M1000_g N_A3_M1003_g
+ N_A3_c_156_n N_A3_M1008_g N_A3_M1018_g N_A3_M1023_g N_A3_c_157_n N_A3_M1028_g
diff --git a/cells/a311oi/sky130_fd_sc_ls__a311oi_4.spice b/cells/a311oi/sky130_fd_sc_ls__a311oi_4.spice
index a9bb443..b1f2b4c 100644
--- a/cells/a311oi/sky130_fd_sc_ls__a311oi_4.spice
+++ b/cells/a311oi/sky130_fd_sc_ls__a311oi_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a311oi_4.spice
-* Created: Fri Aug 28 12:58:27 2020
+* Created: Wed Sep 2 10:52:02 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a31o/sky130_fd_sc_ls__a31o_1.lvs.report b/cells/a31o/sky130_fd_sc_ls__a31o_1.lvs.report
new file mode 100644
index 0000000..1a29d4d
--- /dev/null
+++ b/cells/a31o/sky130_fd_sc_ls__a31o_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__a31o_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__a31o_1.sp ('sky130_fd_sc_ls__a31o_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/a31o/sky130_fd_sc_ls__a31o_1.spice ('sky130_fd_sc_ls__a31o_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:52:06 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__a31o_1 sky130_fd_sc_ls__a31o_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__a31o_1
+SOURCE CELL NAME: sky130_fd_sc_ls__a31o_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 2 2 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMN3 (5 pins)
+ 1 1 SPMP_3_1 (6 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN3
+ 1 1 0 0 SPMP_3_1
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A3 A2 A1 B1 X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a31o/sky130_fd_sc_ls__a31o_1.pex.spice b/cells/a31o/sky130_fd_sc_ls__a31o_1.pex.spice
index c08a003..33282ca 100644
--- a/cells/a31o/sky130_fd_sc_ls__a31o_1.pex.spice
+++ b/cells/a31o/sky130_fd_sc_ls__a31o_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a31o_1.pex.spice
-* Created: Fri Aug 28 12:58:36 2020
+* Created: Wed Sep 2 10:52:09 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a31o/sky130_fd_sc_ls__a31o_1.pxi.spice b/cells/a31o/sky130_fd_sc_ls__a31o_1.pxi.spice
index 1770989..1481f86 100644
--- a/cells/a31o/sky130_fd_sc_ls__a31o_1.pxi.spice
+++ b/cells/a31o/sky130_fd_sc_ls__a31o_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a31o_1.pxi.spice
-* Created: Fri Aug 28 12:58:36 2020
+* Created: Wed Sep 2 10:52:09 2020
*
x_PM_SKY130_FD_SC_LS__A31O_1%A_81_270# N_A_81_270#_M1009_d N_A_81_270#_M1004_d
+ N_A_81_270#_c_57_n N_A_81_270#_M1006_g N_A_81_270#_c_58_n N_A_81_270#_M1005_g
diff --git a/cells/a31o/sky130_fd_sc_ls__a31o_1.spice b/cells/a31o/sky130_fd_sc_ls__a31o_1.spice
index 8d1c88a..009a818 100644
--- a/cells/a31o/sky130_fd_sc_ls__a31o_1.spice
+++ b/cells/a31o/sky130_fd_sc_ls__a31o_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a31o_1.spice
-* Created: Fri Aug 28 12:58:36 2020
+* Created: Wed Sep 2 10:52:09 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a31o/sky130_fd_sc_ls__a31o_2.lvs.report b/cells/a31o/sky130_fd_sc_ls__a31o_2.lvs.report
new file mode 100644
index 0000000..af2cbde
--- /dev/null
+++ b/cells/a31o/sky130_fd_sc_ls__a31o_2.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__a31o_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__a31o_2.sp ('sky130_fd_sc_ls__a31o_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/a31o/sky130_fd_sc_ls__a31o_2.spice ('sky130_fd_sc_ls__a31o_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:52:12 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__a31o_2 sky130_fd_sc_ls__a31o_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__a31o_2
+SOURCE CELL NAME: sky130_fd_sc_ls__a31o_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 2 2 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMN3 (5 pins)
+ 1 1 SPMP_3_1 (6 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN3
+ 1 1 0 0 SPMP_3_1
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A3 A2 A1 B1 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a31o/sky130_fd_sc_ls__a31o_2.pex.spice b/cells/a31o/sky130_fd_sc_ls__a31o_2.pex.spice
index 3b5beae..f699a13 100644
--- a/cells/a31o/sky130_fd_sc_ls__a31o_2.pex.spice
+++ b/cells/a31o/sky130_fd_sc_ls__a31o_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a31o_2.pex.spice
-* Created: Fri Aug 28 12:58:46 2020
+* Created: Wed Sep 2 10:52:15 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a31o/sky130_fd_sc_ls__a31o_2.pxi.spice b/cells/a31o/sky130_fd_sc_ls__a31o_2.pxi.spice
index d12a68e..7492ece 100644
--- a/cells/a31o/sky130_fd_sc_ls__a31o_2.pxi.spice
+++ b/cells/a31o/sky130_fd_sc_ls__a31o_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a31o_2.pxi.spice
-* Created: Fri Aug 28 12:58:46 2020
+* Created: Wed Sep 2 10:52:15 2020
*
x_PM_SKY130_FD_SC_LS__A31O_2%A_97_296# N_A_97_296#_M1009_d N_A_97_296#_M1003_d
+ N_A_97_296#_M1006_g N_A_97_296#_c_62_n N_A_97_296#_M1002_g N_A_97_296#_M1007_g
diff --git a/cells/a31o/sky130_fd_sc_ls__a31o_2.spice b/cells/a31o/sky130_fd_sc_ls__a31o_2.spice
index 56cefa0..93cd3b6 100644
--- a/cells/a31o/sky130_fd_sc_ls__a31o_2.spice
+++ b/cells/a31o/sky130_fd_sc_ls__a31o_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a31o_2.spice
-* Created: Fri Aug 28 12:58:46 2020
+* Created: Wed Sep 2 10:52:15 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a31o/sky130_fd_sc_ls__a31o_4.lvs.report b/cells/a31o/sky130_fd_sc_ls__a31o_4.lvs.report
new file mode 100644
index 0000000..8ca7ff8
--- /dev/null
+++ b/cells/a31o/sky130_fd_sc_ls__a31o_4.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__a31o_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__a31o_4.sp ('sky130_fd_sc_ls__a31o_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/a31o/sky130_fd_sc_ls__a31o_4.spice ('sky130_fd_sc_ls__a31o_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:52:18 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__a31o_4 sky130_fd_sc_ls__a31o_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__a31o_4
+SOURCE CELL NAME: sky130_fd_sc_ls__a31o_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 12 12 MN (4 pins)
+ 12 12 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 25 24
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 2 2 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMN3 (5 pins)
+ 1 1 SPMP_3_1 (6 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN3
+ 1 1 0 0 SPMP_3_1
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 24 layout mos transistors were reduced to 10.
+ 14 mos transistors were deleted by parallel reduction.
+ 24 source mos transistors were reduced to 10.
+ 14 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1 A1 A2 A3 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a31o/sky130_fd_sc_ls__a31o_4.pex.spice b/cells/a31o/sky130_fd_sc_ls__a31o_4.pex.spice
index 9004340..99bb9ae 100644
--- a/cells/a31o/sky130_fd_sc_ls__a31o_4.pex.spice
+++ b/cells/a31o/sky130_fd_sc_ls__a31o_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a31o_4.pex.spice
-* Created: Fri Aug 28 12:59:01 2020
+* Created: Wed Sep 2 10:52:21 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a31o/sky130_fd_sc_ls__a31o_4.pxi.spice b/cells/a31o/sky130_fd_sc_ls__a31o_4.pxi.spice
index 0d04bb4..aceae38 100644
--- a/cells/a31o/sky130_fd_sc_ls__a31o_4.pxi.spice
+++ b/cells/a31o/sky130_fd_sc_ls__a31o_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a31o_4.pxi.spice
-* Created: Fri Aug 28 12:59:01 2020
+* Created: Wed Sep 2 10:52:21 2020
*
x_PM_SKY130_FD_SC_LS__A31O_4%A_83_274# N_A_83_274#_M1002_d N_A_83_274#_M1006_d
+ N_A_83_274#_M1013_d N_A_83_274#_M1001_s N_A_83_274#_c_140_n
diff --git a/cells/a31o/sky130_fd_sc_ls__a31o_4.spice b/cells/a31o/sky130_fd_sc_ls__a31o_4.spice
index 84676fa..e1b9647 100644
--- a/cells/a31o/sky130_fd_sc_ls__a31o_4.spice
+++ b/cells/a31o/sky130_fd_sc_ls__a31o_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a31o_4.spice
-* Created: Fri Aug 28 12:59:01 2020
+* Created: Wed Sep 2 10:52:21 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a31oi/sky130_fd_sc_ls__a31oi_1.lvs.report b/cells/a31oi/sky130_fd_sc_ls__a31oi_1.lvs.report
new file mode 100644
index 0000000..6e90255
--- /dev/null
+++ b/cells/a31oi/sky130_fd_sc_ls__a31oi_1.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__a31oi_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__a31oi_1.sp ('sky130_fd_sc_ls__a31oi_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/a31oi/sky130_fd_sc_ls__a31oi_1.spice ('sky130_fd_sc_ls__a31oi_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:52:25 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__a31oi_1 sky130_fd_sc_ls__a31oi_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__a31oi_1
+SOURCE CELL NAME: sky130_fd_sc_ls__a31oi_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 12 12
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 9 9
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 SMN3 (5 pins)
+ 1 1 SPMP_3_1 (6 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 SMN3
+ 1 1 0 0 SPMP_3_1
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A3 A2 A1 B1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a31oi/sky130_fd_sc_ls__a31oi_1.pex.spice b/cells/a31oi/sky130_fd_sc_ls__a31oi_1.pex.spice
index 291f93e..8d6245e 100644
--- a/cells/a31oi/sky130_fd_sc_ls__a31oi_1.pex.spice
+++ b/cells/a31oi/sky130_fd_sc_ls__a31oi_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a31oi_1.pex.spice
-* Created: Fri Aug 28 12:59:21 2020
+* Created: Wed Sep 2 10:52:28 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a31oi/sky130_fd_sc_ls__a31oi_1.pxi.spice b/cells/a31oi/sky130_fd_sc_ls__a31oi_1.pxi.spice
index 036d182..e2dd0d5 100644
--- a/cells/a31oi/sky130_fd_sc_ls__a31oi_1.pxi.spice
+++ b/cells/a31oi/sky130_fd_sc_ls__a31oi_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a31oi_1.pxi.spice
-* Created: Fri Aug 28 12:59:21 2020
+* Created: Wed Sep 2 10:52:28 2020
*
x_PM_SKY130_FD_SC_LS__A31OI_1%A3 N_A3_c_44_n N_A3_M1006_g N_A3_c_45_n
+ N_A3_M1007_g N_A3_c_46_n A3 PM_SKY130_FD_SC_LS__A31OI_1%A3
diff --git a/cells/a31oi/sky130_fd_sc_ls__a31oi_1.spice b/cells/a31oi/sky130_fd_sc_ls__a31oi_1.spice
index 413f8b1..b9ebaed 100644
--- a/cells/a31oi/sky130_fd_sc_ls__a31oi_1.spice
+++ b/cells/a31oi/sky130_fd_sc_ls__a31oi_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a31oi_1.spice
-* Created: Fri Aug 28 12:59:21 2020
+* Created: Wed Sep 2 10:52:28 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a31oi/sky130_fd_sc_ls__a31oi_2.lvs.report b/cells/a31oi/sky130_fd_sc_ls__a31oi_2.lvs.report
new file mode 100644
index 0000000..d68aef2
--- /dev/null
+++ b/cells/a31oi/sky130_fd_sc_ls__a31oi_2.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__a31oi_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__a31oi_2.sp ('sky130_fd_sc_ls__a31oi_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/a31oi/sky130_fd_sc_ls__a31oi_2.spice ('sky130_fd_sc_ls__a31oi_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:52:31 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__a31oi_2 sky130_fd_sc_ls__a31oi_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__a31oi_2
+SOURCE CELL NAME: sky130_fd_sc_ls__a31oi_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 12 12
+
+ Instances: 7 7 MN (4 pins)
+ 8 8 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 16 15
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 9 9
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 SMN3 (5 pins)
+ 1 1 SPMP_3_1 (6 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 SMN3
+ 1 1 0 0 SPMP_3_1
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 14 layout mos transistors were reduced to 7.
+ 7 mos transistors were deleted by parallel reduction.
+ 14 source mos transistors were reduced to 7.
+ 7 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A3 A2 B1 A1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a31oi/sky130_fd_sc_ls__a31oi_2.pex.spice b/cells/a31oi/sky130_fd_sc_ls__a31oi_2.pex.spice
index 6656eb6..8634da0 100644
--- a/cells/a31oi/sky130_fd_sc_ls__a31oi_2.pex.spice
+++ b/cells/a31oi/sky130_fd_sc_ls__a31oi_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a31oi_2.pex.spice
-* Created: Fri Aug 28 12:59:31 2020
+* Created: Wed Sep 2 10:52:34 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a31oi/sky130_fd_sc_ls__a31oi_2.pxi.spice b/cells/a31oi/sky130_fd_sc_ls__a31oi_2.pxi.spice
index 41e58d7..0197cbe 100644
--- a/cells/a31oi/sky130_fd_sc_ls__a31oi_2.pxi.spice
+++ b/cells/a31oi/sky130_fd_sc_ls__a31oi_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a31oi_2.pxi.spice
-* Created: Fri Aug 28 12:59:31 2020
+* Created: Wed Sep 2 10:52:34 2020
*
x_PM_SKY130_FD_SC_LS__A31OI_2%A3 N_A3_c_71_n N_A3_M1008_g N_A3_c_72_n
+ N_A3_M1000_g N_A3_c_73_n N_A3_M1012_g N_A3_c_74_n N_A3_M1007_g N_A3_c_75_n
diff --git a/cells/a31oi/sky130_fd_sc_ls__a31oi_2.spice b/cells/a31oi/sky130_fd_sc_ls__a31oi_2.spice
index 1fb8bd0..d6bc914 100644
--- a/cells/a31oi/sky130_fd_sc_ls__a31oi_2.spice
+++ b/cells/a31oi/sky130_fd_sc_ls__a31oi_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a31oi_2.spice
-* Created: Fri Aug 28 12:59:31 2020
+* Created: Wed Sep 2 10:52:34 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a31oi/sky130_fd_sc_ls__a31oi_4.lvs.report b/cells/a31oi/sky130_fd_sc_ls__a31oi_4.lvs.report
new file mode 100644
index 0000000..ec52f36
--- /dev/null
+++ b/cells/a31oi/sky130_fd_sc_ls__a31oi_4.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__a31oi_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__a31oi_4.sp ('sky130_fd_sc_ls__a31oi_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/a31oi/sky130_fd_sc_ls__a31oi_4.spice ('sky130_fd_sc_ls__a31oi_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:52:38 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__a31oi_4 sky130_fd_sc_ls__a31oi_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__a31oi_4
+SOURCE CELL NAME: sky130_fd_sc_ls__a31oi_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 12 12
+
+ Instances: 14 14 MN (4 pins)
+ 16 16 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 31 30
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 9 9
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 SMN3 (5 pins)
+ 1 1 SPMP_3_1 (6 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 SMN3
+ 1 1 0 0 SPMP_3_1
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 30 layout mos transistors were reduced to 8.
+ 22 mos transistors were deleted by parallel reduction.
+ 30 source mos transistors were reduced to 8.
+ 22 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A3 A2 A1 B1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a31oi/sky130_fd_sc_ls__a31oi_4.pex.spice b/cells/a31oi/sky130_fd_sc_ls__a31oi_4.pex.spice
index 07508fe..a6db8da 100644
--- a/cells/a31oi/sky130_fd_sc_ls__a31oi_4.pex.spice
+++ b/cells/a31oi/sky130_fd_sc_ls__a31oi_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a31oi_4.pex.spice
-* Created: Fri Aug 28 12:59:40 2020
+* Created: Wed Sep 2 10:52:41 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a31oi/sky130_fd_sc_ls__a31oi_4.pxi.spice b/cells/a31oi/sky130_fd_sc_ls__a31oi_4.pxi.spice
index 9c307d1..50d6b2f 100644
--- a/cells/a31oi/sky130_fd_sc_ls__a31oi_4.pxi.spice
+++ b/cells/a31oi/sky130_fd_sc_ls__a31oi_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a31oi_4.pxi.spice
-* Created: Fri Aug 28 12:59:40 2020
+* Created: Wed Sep 2 10:52:41 2020
*
x_PM_SKY130_FD_SC_LS__A31OI_4%A3 N_A3_c_129_n N_A3_M1001_g N_A3_M1009_g
+ N_A3_M1011_g N_A3_c_130_n N_A3_M1015_g N_A3_M1026_g N_A3_c_131_n N_A3_M1016_g
diff --git a/cells/a31oi/sky130_fd_sc_ls__a31oi_4.spice b/cells/a31oi/sky130_fd_sc_ls__a31oi_4.spice
index 03092c9..edf7b39 100644
--- a/cells/a31oi/sky130_fd_sc_ls__a31oi_4.spice
+++ b/cells/a31oi/sky130_fd_sc_ls__a31oi_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a31oi_4.spice
-* Created: Fri Aug 28 12:59:40 2020
+* Created: Wed Sep 2 10:52:41 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a32o/sky130_fd_sc_ls__a32o_1.lvs.report b/cells/a32o/sky130_fd_sc_ls__a32o_1.lvs.report
new file mode 100644
index 0000000..811a6b4
--- /dev/null
+++ b/cells/a32o/sky130_fd_sc_ls__a32o_1.lvs.report
@@ -0,0 +1,470 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__a32o_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__a32o_1.sp ('sky130_fd_sc_ls__a32o_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/a32o/sky130_fd_sc_ls__a32o_1.spice ('sky130_fd_sc_ls__a32o_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:52:44 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__a32o_1 sky130_fd_sc_ls__a32o_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__a32o_1
+SOURCE CELL NAME: sky130_fd_sc_ls__a32o_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 15 15
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 11 11
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ 1 1 SPMP_3_2 (7 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMN3
+ 1 1 0 0 SPMP_3_2
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A3 A2 A1 B1 B2 X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a32o/sky130_fd_sc_ls__a32o_1.pex.spice b/cells/a32o/sky130_fd_sc_ls__a32o_1.pex.spice
index 9f32946..d30b937 100644
--- a/cells/a32o/sky130_fd_sc_ls__a32o_1.pex.spice
+++ b/cells/a32o/sky130_fd_sc_ls__a32o_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a32o_1.pex.spice
-* Created: Fri Aug 28 12:59:50 2020
+* Created: Wed Sep 2 10:52:47 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a32o/sky130_fd_sc_ls__a32o_1.pxi.spice b/cells/a32o/sky130_fd_sc_ls__a32o_1.pxi.spice
index 366c58d..961f1b9 100644
--- a/cells/a32o/sky130_fd_sc_ls__a32o_1.pxi.spice
+++ b/cells/a32o/sky130_fd_sc_ls__a32o_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a32o_1.pxi.spice
-* Created: Fri Aug 28 12:59:50 2020
+* Created: Wed Sep 2 10:52:47 2020
*
x_PM_SKY130_FD_SC_LS__A32O_1%A_84_48# N_A_84_48#_M1011_d N_A_84_48#_M1010_d
+ N_A_84_48#_M1009_g N_A_84_48#_c_55_n N_A_84_48#_M1003_g N_A_84_48#_c_56_n
diff --git a/cells/a32o/sky130_fd_sc_ls__a32o_1.spice b/cells/a32o/sky130_fd_sc_ls__a32o_1.spice
index 6690a45..b59762c 100644
--- a/cells/a32o/sky130_fd_sc_ls__a32o_1.spice
+++ b/cells/a32o/sky130_fd_sc_ls__a32o_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a32o_1.spice
-* Created: Fri Aug 28 12:59:50 2020
+* Created: Wed Sep 2 10:52:47 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a32o/sky130_fd_sc_ls__a32o_2.lvs.report b/cells/a32o/sky130_fd_sc_ls__a32o_2.lvs.report
new file mode 100644
index 0000000..e87ae6b
--- /dev/null
+++ b/cells/a32o/sky130_fd_sc_ls__a32o_2.lvs.report
@@ -0,0 +1,475 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__a32o_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__a32o_2.sp ('sky130_fd_sc_ls__a32o_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/a32o/sky130_fd_sc_ls__a32o_2.spice ('sky130_fd_sc_ls__a32o_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:52:51 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__a32o_2 sky130_fd_sc_ls__a32o_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__a32o_2
+SOURCE CELL NAME: sky130_fd_sc_ls__a32o_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 15 15
+
+ Instances: 7 7 MN (4 pins)
+ 7 7 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 15 14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 11 11
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ 1 1 SPMP_3_2 (7 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMN3
+ 1 1 0 0 SPMP_3_2
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A3 A2 A1 B1 B2 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a32o/sky130_fd_sc_ls__a32o_2.pex.spice b/cells/a32o/sky130_fd_sc_ls__a32o_2.pex.spice
index 2cf604c..64fd456 100644
--- a/cells/a32o/sky130_fd_sc_ls__a32o_2.pex.spice
+++ b/cells/a32o/sky130_fd_sc_ls__a32o_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a32o_2.pex.spice
-* Created: Fri Aug 28 13:00:06 2020
+* Created: Wed Sep 2 10:52:53 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a32o/sky130_fd_sc_ls__a32o_2.pxi.spice b/cells/a32o/sky130_fd_sc_ls__a32o_2.pxi.spice
index 7105336..a7b5c35 100644
--- a/cells/a32o/sky130_fd_sc_ls__a32o_2.pxi.spice
+++ b/cells/a32o/sky130_fd_sc_ls__a32o_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a32o_2.pxi.spice
-* Created: Fri Aug 28 13:00:06 2020
+* Created: Wed Sep 2 10:52:53 2020
*
x_PM_SKY130_FD_SC_LS__A32O_2%A_45_264# N_A_45_264#_M1013_d N_A_45_264#_M1008_d
+ N_A_45_264#_c_78_n N_A_45_264#_M1009_g N_A_45_264#_M1001_g N_A_45_264#_c_79_n
diff --git a/cells/a32o/sky130_fd_sc_ls__a32o_2.spice b/cells/a32o/sky130_fd_sc_ls__a32o_2.spice
index 02e2087..21ceec3 100644
--- a/cells/a32o/sky130_fd_sc_ls__a32o_2.spice
+++ b/cells/a32o/sky130_fd_sc_ls__a32o_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a32o_2.spice
-* Created: Fri Aug 28 13:00:06 2020
+* Created: Wed Sep 2 10:52:53 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a32o/sky130_fd_sc_ls__a32o_4.lvs.report b/cells/a32o/sky130_fd_sc_ls__a32o_4.lvs.report
new file mode 100644
index 0000000..6a44eaa
--- /dev/null
+++ b/cells/a32o/sky130_fd_sc_ls__a32o_4.lvs.report
@@ -0,0 +1,475 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__a32o_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__a32o_4.sp ('sky130_fd_sc_ls__a32o_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/a32o/sky130_fd_sc_ls__a32o_4.spice ('sky130_fd_sc_ls__a32o_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:52:57 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__a32o_4 sky130_fd_sc_ls__a32o_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__a32o_4
+SOURCE CELL NAME: sky130_fd_sc_ls__a32o_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 15 15
+
+ Instances: 14 14 MN (4 pins)
+ 14 14 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 29 28
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 11 11
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ 1 1 SPMP_3_2 (7 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMN3
+ 1 1 0 0 SPMP_3_2
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 28 layout mos transistors were reduced to 12.
+ 16 mos transistors were deleted by parallel reduction.
+ 28 source mos transistors were reduced to 12.
+ 16 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B2 B1 A2 A1 A3 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a32o/sky130_fd_sc_ls__a32o_4.pex.spice b/cells/a32o/sky130_fd_sc_ls__a32o_4.pex.spice
index 4b06b1f..797ea86 100644
--- a/cells/a32o/sky130_fd_sc_ls__a32o_4.pex.spice
+++ b/cells/a32o/sky130_fd_sc_ls__a32o_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a32o_4.pex.spice
-* Created: Fri Aug 28 13:00:26 2020
+* Created: Wed Sep 2 10:53:00 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a32o/sky130_fd_sc_ls__a32o_4.pxi.spice b/cells/a32o/sky130_fd_sc_ls__a32o_4.pxi.spice
index 7688623..028260b 100644
--- a/cells/a32o/sky130_fd_sc_ls__a32o_4.pxi.spice
+++ b/cells/a32o/sky130_fd_sc_ls__a32o_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a32o_4.pxi.spice
-* Created: Fri Aug 28 13:00:26 2020
+* Created: Wed Sep 2 10:53:00 2020
*
x_PM_SKY130_FD_SC_LS__A32O_4%A_83_283# N_A_83_283#_M1013_s N_A_83_283#_M1022_d
+ N_A_83_283#_M1001_s N_A_83_283#_M1024_s N_A_83_283#_c_146_n
diff --git a/cells/a32o/sky130_fd_sc_ls__a32o_4.spice b/cells/a32o/sky130_fd_sc_ls__a32o_4.spice
index 422924f..f565a5d 100644
--- a/cells/a32o/sky130_fd_sc_ls__a32o_4.spice
+++ b/cells/a32o/sky130_fd_sc_ls__a32o_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a32o_4.spice
-* Created: Fri Aug 28 13:00:26 2020
+* Created: Wed Sep 2 10:53:00 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a32oi/sky130_fd_sc_ls__a32oi_1.lvs.report b/cells/a32oi/sky130_fd_sc_ls__a32oi_1.lvs.report
new file mode 100644
index 0000000..57a5c9b
--- /dev/null
+++ b/cells/a32oi/sky130_fd_sc_ls__a32oi_1.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__a32oi_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__a32oi_1.sp ('sky130_fd_sc_ls__a32oi_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/a32oi/sky130_fd_sc_ls__a32oi_1.spice ('sky130_fd_sc_ls__a32oi_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:53:03 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__a32oi_1 sky130_fd_sc_ls__a32oi_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__a32oi_1
+SOURCE CELL NAME: sky130_fd_sc_ls__a32oi_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 14 14
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 10 10
+
+ Instances: 1 1 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ 1 1 SPMP_3_2 (7 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 SMN2
+ 1 1 0 0 SMN3
+ 1 1 0 0 SPMP_3_2
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B2 B1 A1 A2 A3 Y VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a32oi/sky130_fd_sc_ls__a32oi_1.pex.spice b/cells/a32oi/sky130_fd_sc_ls__a32oi_1.pex.spice
index e6a2c90..a9700f6 100644
--- a/cells/a32oi/sky130_fd_sc_ls__a32oi_1.pex.spice
+++ b/cells/a32oi/sky130_fd_sc_ls__a32oi_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a32oi_1.pex.spice
-* Created: Fri Aug 28 13:00:35 2020
+* Created: Wed Sep 2 10:53:06 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a32oi/sky130_fd_sc_ls__a32oi_1.pxi.spice b/cells/a32oi/sky130_fd_sc_ls__a32oi_1.pxi.spice
index ba030e6..759b92b 100644
--- a/cells/a32oi/sky130_fd_sc_ls__a32oi_1.pxi.spice
+++ b/cells/a32oi/sky130_fd_sc_ls__a32oi_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a32oi_1.pxi.spice
-* Created: Fri Aug 28 13:00:35 2020
+* Created: Wed Sep 2 10:53:06 2020
*
x_PM_SKY130_FD_SC_LS__A32OI_1%B2 N_B2_c_46_n N_B2_M1006_g N_B2_c_47_n
+ N_B2_M1002_g B2 PM_SKY130_FD_SC_LS__A32OI_1%B2
diff --git a/cells/a32oi/sky130_fd_sc_ls__a32oi_1.spice b/cells/a32oi/sky130_fd_sc_ls__a32oi_1.spice
index b5bf50a..321f11b 100644
--- a/cells/a32oi/sky130_fd_sc_ls__a32oi_1.spice
+++ b/cells/a32oi/sky130_fd_sc_ls__a32oi_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a32oi_1.spice
-* Created: Fri Aug 28 13:00:35 2020
+* Created: Wed Sep 2 10:53:06 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a32oi/sky130_fd_sc_ls__a32oi_2.lvs.report b/cells/a32oi/sky130_fd_sc_ls__a32oi_2.lvs.report
new file mode 100644
index 0000000..a561f72
--- /dev/null
+++ b/cells/a32oi/sky130_fd_sc_ls__a32oi_2.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__a32oi_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__a32oi_2.sp ('sky130_fd_sc_ls__a32oi_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/a32oi/sky130_fd_sc_ls__a32oi_2.spice ('sky130_fd_sc_ls__a32oi_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:53:10 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__a32oi_2 sky130_fd_sc_ls__a32oi_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__a32oi_2
+SOURCE CELL NAME: sky130_fd_sc_ls__a32oi_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 14 14
+
+ Instances: 10 10 MN (4 pins)
+ 10 10 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 21 20
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 10 10
+
+ Instances: 1 1 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ 1 1 SPMP_3_2 (7 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 SMN2
+ 1 1 0 0 SMN3
+ 1 1 0 0 SPMP_3_2
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 20 layout mos transistors were reduced to 10.
+ 10 mos transistors were deleted by parallel reduction.
+ 20 source mos transistors were reduced to 10.
+ 10 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B2 B1 A1 A2 A3 Y VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a32oi/sky130_fd_sc_ls__a32oi_2.pex.spice b/cells/a32oi/sky130_fd_sc_ls__a32oi_2.pex.spice
index f46d5c3..58be508 100644
--- a/cells/a32oi/sky130_fd_sc_ls__a32oi_2.pex.spice
+++ b/cells/a32oi/sky130_fd_sc_ls__a32oi_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a32oi_2.pex.spice
-* Created: Fri Aug 28 13:00:45 2020
+* Created: Wed Sep 2 10:53:12 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a32oi/sky130_fd_sc_ls__a32oi_2.pxi.spice b/cells/a32oi/sky130_fd_sc_ls__a32oi_2.pxi.spice
index 506a6e4..cda6025 100644
--- a/cells/a32oi/sky130_fd_sc_ls__a32oi_2.pxi.spice
+++ b/cells/a32oi/sky130_fd_sc_ls__a32oi_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a32oi_2.pxi.spice
-* Created: Fri Aug 28 13:00:45 2020
+* Created: Wed Sep 2 10:53:12 2020
*
x_PM_SKY130_FD_SC_LS__A32OI_2%B2 N_B2_M1010_g N_B2_c_104_n N_B2_M1007_g
+ N_B2_M1016_g N_B2_c_105_n N_B2_M1009_g N_B2_c_101_n B2 N_B2_c_102_n
diff --git a/cells/a32oi/sky130_fd_sc_ls__a32oi_2.spice b/cells/a32oi/sky130_fd_sc_ls__a32oi_2.spice
index fa21b28..c4e73fa 100644
--- a/cells/a32oi/sky130_fd_sc_ls__a32oi_2.spice
+++ b/cells/a32oi/sky130_fd_sc_ls__a32oi_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a32oi_2.spice
-* Created: Fri Aug 28 13:00:45 2020
+* Created: Wed Sep 2 10:53:12 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a32oi/sky130_fd_sc_ls__a32oi_4.lvs.report b/cells/a32oi/sky130_fd_sc_ls__a32oi_4.lvs.report
new file mode 100644
index 0000000..0efcbc3
--- /dev/null
+++ b/cells/a32oi/sky130_fd_sc_ls__a32oi_4.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__a32oi_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__a32oi_4.sp ('sky130_fd_sc_ls__a32oi_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/a32oi/sky130_fd_sc_ls__a32oi_4.spice ('sky130_fd_sc_ls__a32oi_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:53:16 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__a32oi_4 sky130_fd_sc_ls__a32oi_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__a32oi_4
+SOURCE CELL NAME: sky130_fd_sc_ls__a32oi_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 14 14
+
+ Instances: 20 20 MN (4 pins)
+ 20 20 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 41 40
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 10 10
+
+ Instances: 1 1 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ 1 1 SPMP_3_2 (7 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 SMN2
+ 1 1 0 0 SMN3
+ 1 1 0 0 SPMP_3_2
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 40 layout mos transistors were reduced to 10.
+ 30 mos transistors were deleted by parallel reduction.
+ 40 source mos transistors were reduced to 10.
+ 30 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B2 B1 A1 A2 A3 Y VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a32oi/sky130_fd_sc_ls__a32oi_4.pex.spice b/cells/a32oi/sky130_fd_sc_ls__a32oi_4.pex.spice
index 6fa21cc..03d6f10 100644
--- a/cells/a32oi/sky130_fd_sc_ls__a32oi_4.pex.spice
+++ b/cells/a32oi/sky130_fd_sc_ls__a32oi_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a32oi_4.pex.spice
-* Created: Fri Aug 28 13:00:54 2020
+* Created: Wed Sep 2 10:53:19 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a32oi/sky130_fd_sc_ls__a32oi_4.pxi.spice b/cells/a32oi/sky130_fd_sc_ls__a32oi_4.pxi.spice
index 882b858..44ebccf 100644
--- a/cells/a32oi/sky130_fd_sc_ls__a32oi_4.pxi.spice
+++ b/cells/a32oi/sky130_fd_sc_ls__a32oi_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a32oi_4.pxi.spice
-* Created: Fri Aug 28 13:00:54 2020
+* Created: Wed Sep 2 10:53:19 2020
*
x_PM_SKY130_FD_SC_LS__A32OI_4%B2 N_B2_M1009_g N_B2_c_150_n N_B2_M1000_g
+ N_B2_M1013_g N_B2_c_151_n N_B2_M1021_g N_B2_M1029_g N_B2_c_152_n N_B2_M1024_g
diff --git a/cells/a32oi/sky130_fd_sc_ls__a32oi_4.spice b/cells/a32oi/sky130_fd_sc_ls__a32oi_4.spice
index a8224ae..1edf830 100644
--- a/cells/a32oi/sky130_fd_sc_ls__a32oi_4.spice
+++ b/cells/a32oi/sky130_fd_sc_ls__a32oi_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a32oi_4.spice
-* Created: Fri Aug 28 13:00:54 2020
+* Created: Wed Sep 2 10:53:19 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a41o/sky130_fd_sc_ls__a41o_1.lvs.report b/cells/a41o/sky130_fd_sc_ls__a41o_1.lvs.report
new file mode 100644
index 0000000..87854bc
--- /dev/null
+++ b/cells/a41o/sky130_fd_sc_ls__a41o_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__a41o_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__a41o_1.sp ('sky130_fd_sc_ls__a41o_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/a41o/sky130_fd_sc_ls__a41o_1.spice ('sky130_fd_sc_ls__a41o_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:53:23 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__a41o_1 sky130_fd_sc_ls__a41o_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__a41o_1
+SOURCE CELL NAME: sky130_fd_sc_ls__a41o_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 15 15
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 11 11
+
+ Instances: 2 2 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMN4 (6 pins)
+ 1 1 SPMP_4_1 (7 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN4
+ 1 1 0 0 SPMP_4_1
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1 A1 A2 A3 A4 X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a41o/sky130_fd_sc_ls__a41o_1.pex.spice b/cells/a41o/sky130_fd_sc_ls__a41o_1.pex.spice
index 718046b..47fdf80 100644
--- a/cells/a41o/sky130_fd_sc_ls__a41o_1.pex.spice
+++ b/cells/a41o/sky130_fd_sc_ls__a41o_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a41o_1.pex.spice
-* Created: Fri Aug 28 13:01:10 2020
+* Created: Wed Sep 2 10:53:26 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a41o/sky130_fd_sc_ls__a41o_1.pxi.spice b/cells/a41o/sky130_fd_sc_ls__a41o_1.pxi.spice
index 47e0ad1..aeb72d9 100644
--- a/cells/a41o/sky130_fd_sc_ls__a41o_1.pxi.spice
+++ b/cells/a41o/sky130_fd_sc_ls__a41o_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a41o_1.pxi.spice
-* Created: Fri Aug 28 13:01:10 2020
+* Created: Wed Sep 2 10:53:26 2020
*
x_PM_SKY130_FD_SC_LS__A41O_1%A_83_244# N_A_83_244#_M1010_d N_A_83_244#_M1005_s
+ N_A_83_244#_c_81_n N_A_83_244#_M1008_g N_A_83_244#_c_73_n N_A_83_244#_M1006_g
diff --git a/cells/a41o/sky130_fd_sc_ls__a41o_1.spice b/cells/a41o/sky130_fd_sc_ls__a41o_1.spice
index 93cd106..a5aea86 100644
--- a/cells/a41o/sky130_fd_sc_ls__a41o_1.spice
+++ b/cells/a41o/sky130_fd_sc_ls__a41o_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a41o_1.spice
-* Created: Fri Aug 28 13:01:10 2020
+* Created: Wed Sep 2 10:53:26 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a41o/sky130_fd_sc_ls__a41o_2.lvs.report b/cells/a41o/sky130_fd_sc_ls__a41o_2.lvs.report
new file mode 100644
index 0000000..65ca19a
--- /dev/null
+++ b/cells/a41o/sky130_fd_sc_ls__a41o_2.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__a41o_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__a41o_2.sp ('sky130_fd_sc_ls__a41o_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/a41o/sky130_fd_sc_ls__a41o_2.spice ('sky130_fd_sc_ls__a41o_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:53:29 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__a41o_2 sky130_fd_sc_ls__a41o_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__a41o_2
+SOURCE CELL NAME: sky130_fd_sc_ls__a41o_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 15 15
+
+ Instances: 7 7 MN (4 pins)
+ 7 7 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 15 14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 11 11
+
+ Instances: 2 2 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMN4 (6 pins)
+ 1 1 SPMP_4_1 (7 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN4
+ 1 1 0 0 SPMP_4_1
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A4 A3 A2 A1 B1 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a41o/sky130_fd_sc_ls__a41o_2.pex.spice b/cells/a41o/sky130_fd_sc_ls__a41o_2.pex.spice
index 073b777..d6a3624 100644
--- a/cells/a41o/sky130_fd_sc_ls__a41o_2.pex.spice
+++ b/cells/a41o/sky130_fd_sc_ls__a41o_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a41o_2.pex.spice
-* Created: Fri Aug 28 13:01:31 2020
+* Created: Wed Sep 2 10:53:32 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a41o/sky130_fd_sc_ls__a41o_2.pxi.spice b/cells/a41o/sky130_fd_sc_ls__a41o_2.pxi.spice
index fb12759..72c63e8 100644
--- a/cells/a41o/sky130_fd_sc_ls__a41o_2.pxi.spice
+++ b/cells/a41o/sky130_fd_sc_ls__a41o_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a41o_2.pxi.spice
-* Created: Fri Aug 28 13:01:31 2020
+* Created: Wed Sep 2 10:53:32 2020
*
x_PM_SKY130_FD_SC_LS__A41O_2%A4 N_A4_c_81_n N_A4_c_86_n N_A4_M1009_g N_A4_c_82_n
+ N_A4_M1005_g A4 N_A4_c_84_n PM_SKY130_FD_SC_LS__A41O_2%A4
diff --git a/cells/a41o/sky130_fd_sc_ls__a41o_2.spice b/cells/a41o/sky130_fd_sc_ls__a41o_2.spice
index a5594c4..d8224fd 100644
--- a/cells/a41o/sky130_fd_sc_ls__a41o_2.spice
+++ b/cells/a41o/sky130_fd_sc_ls__a41o_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a41o_2.spice
-* Created: Fri Aug 28 13:01:31 2020
+* Created: Wed Sep 2 10:53:32 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a41o/sky130_fd_sc_ls__a41o_4.lvs.report b/cells/a41o/sky130_fd_sc_ls__a41o_4.lvs.report
new file mode 100644
index 0000000..d9c6cb0
--- /dev/null
+++ b/cells/a41o/sky130_fd_sc_ls__a41o_4.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__a41o_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__a41o_4.sp ('sky130_fd_sc_ls__a41o_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/a41o/sky130_fd_sc_ls__a41o_4.spice ('sky130_fd_sc_ls__a41o_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:53:36 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__a41o_4 sky130_fd_sc_ls__a41o_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__a41o_4
+SOURCE CELL NAME: sky130_fd_sc_ls__a41o_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 15 15
+
+ Instances: 14 14 MN (4 pins)
+ 14 14 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 29 28
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 11 11
+
+ Instances: 2 2 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMN4 (6 pins)
+ 1 1 SPMP_4_1 (7 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN4
+ 1 1 0 0 SPMP_4_1
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 28 layout mos transistors were reduced to 12.
+ 16 mos transistors were deleted by parallel reduction.
+ 28 source mos transistors were reduced to 12.
+ 16 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1 A1 A2 A3 A4 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a41o/sky130_fd_sc_ls__a41o_4.pex.spice b/cells/a41o/sky130_fd_sc_ls__a41o_4.pex.spice
index 758fe47..c60b388 100644
--- a/cells/a41o/sky130_fd_sc_ls__a41o_4.pex.spice
+++ b/cells/a41o/sky130_fd_sc_ls__a41o_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a41o_4.pex.spice
-* Created: Fri Aug 28 13:01:41 2020
+* Created: Wed Sep 2 10:53:39 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a41o/sky130_fd_sc_ls__a41o_4.pxi.spice b/cells/a41o/sky130_fd_sc_ls__a41o_4.pxi.spice
index 8d37499..9d59fee 100644
--- a/cells/a41o/sky130_fd_sc_ls__a41o_4.pxi.spice
+++ b/cells/a41o/sky130_fd_sc_ls__a41o_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a41o_4.pxi.spice
-* Created: Fri Aug 28 13:01:41 2020
+* Created: Wed Sep 2 10:53:39 2020
*
x_PM_SKY130_FD_SC_LS__A41O_4%B1 N_B1_M1008_g N_B1_c_139_n N_B1_M1022_g
+ N_B1_M1017_g N_B1_c_140_n N_B1_M1023_g B1 N_B1_c_137_n N_B1_c_138_n
diff --git a/cells/a41o/sky130_fd_sc_ls__a41o_4.spice b/cells/a41o/sky130_fd_sc_ls__a41o_4.spice
index 3702f4b..d33b640 100644
--- a/cells/a41o/sky130_fd_sc_ls__a41o_4.spice
+++ b/cells/a41o/sky130_fd_sc_ls__a41o_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a41o_4.spice
-* Created: Fri Aug 28 13:01:41 2020
+* Created: Wed Sep 2 10:53:39 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a41oi/sky130_fd_sc_ls__a41oi_1.lvs.report b/cells/a41oi/sky130_fd_sc_ls__a41oi_1.lvs.report
new file mode 100644
index 0000000..30c8e37
--- /dev/null
+++ b/cells/a41oi/sky130_fd_sc_ls__a41oi_1.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__a41oi_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__a41oi_1.sp ('sky130_fd_sc_ls__a41oi_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/a41oi/sky130_fd_sc_ls__a41oi_1.spice ('sky130_fd_sc_ls__a41oi_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:53:43 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__a41oi_1 sky130_fd_sc_ls__a41oi_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__a41oi_1
+SOURCE CELL NAME: sky130_fd_sc_ls__a41oi_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 14 14
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 10 10
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 SMN4 (6 pins)
+ 1 1 SPMP_4_1 (7 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 SMN4
+ 1 1 0 0 SPMP_4_1
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1 A4 A3 A2 A1 Y VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a41oi/sky130_fd_sc_ls__a41oi_1.pex.spice b/cells/a41oi/sky130_fd_sc_ls__a41oi_1.pex.spice
index e354455..ee47ada 100644
--- a/cells/a41oi/sky130_fd_sc_ls__a41oi_1.pex.spice
+++ b/cells/a41oi/sky130_fd_sc_ls__a41oi_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a41oi_1.pex.spice
-* Created: Fri Aug 28 13:01:50 2020
+* Created: Wed Sep 2 10:53:46 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a41oi/sky130_fd_sc_ls__a41oi_1.pxi.spice b/cells/a41oi/sky130_fd_sc_ls__a41oi_1.pxi.spice
index d99f4fb..bee2c92 100644
--- a/cells/a41oi/sky130_fd_sc_ls__a41oi_1.pxi.spice
+++ b/cells/a41oi/sky130_fd_sc_ls__a41oi_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a41oi_1.pxi.spice
-* Created: Fri Aug 28 13:01:50 2020
+* Created: Wed Sep 2 10:53:46 2020
*
x_PM_SKY130_FD_SC_LS__A41OI_1%B1 N_B1_M1008_g N_B1_c_50_n N_B1_M1007_g B1
+ N_B1_c_51_n PM_SKY130_FD_SC_LS__A41OI_1%B1
diff --git a/cells/a41oi/sky130_fd_sc_ls__a41oi_1.spice b/cells/a41oi/sky130_fd_sc_ls__a41oi_1.spice
index fdf3d01..6a6f64f 100644
--- a/cells/a41oi/sky130_fd_sc_ls__a41oi_1.spice
+++ b/cells/a41oi/sky130_fd_sc_ls__a41oi_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a41oi_1.spice
-* Created: Fri Aug 28 13:01:50 2020
+* Created: Wed Sep 2 10:53:46 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a41oi/sky130_fd_sc_ls__a41oi_2.lvs.report b/cells/a41oi/sky130_fd_sc_ls__a41oi_2.lvs.report
new file mode 100644
index 0000000..14a7543
--- /dev/null
+++ b/cells/a41oi/sky130_fd_sc_ls__a41oi_2.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__a41oi_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__a41oi_2.sp ('sky130_fd_sc_ls__a41oi_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/a41oi/sky130_fd_sc_ls__a41oi_2.spice ('sky130_fd_sc_ls__a41oi_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:53:49 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__a41oi_2 sky130_fd_sc_ls__a41oi_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__a41oi_2
+SOURCE CELL NAME: sky130_fd_sc_ls__a41oi_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 14 14
+
+ Instances: 9 9 MN (4 pins)
+ 10 10 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 20 19
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 10 10
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 SMN4 (6 pins)
+ 1 1 SPMP_4_1 (7 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 SMN4
+ 1 1 0 0 SPMP_4_1
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 18 layout mos transistors were reduced to 9.
+ 9 mos transistors were deleted by parallel reduction.
+ 18 source mos transistors were reduced to 9.
+ 9 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1 A1 A2 A3 A4 Y VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a41oi/sky130_fd_sc_ls__a41oi_2.pex.spice b/cells/a41oi/sky130_fd_sc_ls__a41oi_2.pex.spice
index f9f7cff..7a263a0 100644
--- a/cells/a41oi/sky130_fd_sc_ls__a41oi_2.pex.spice
+++ b/cells/a41oi/sky130_fd_sc_ls__a41oi_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a41oi_2.pex.spice
-* Created: Fri Aug 28 13:02:00 2020
+* Created: Wed Sep 2 10:53:52 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a41oi/sky130_fd_sc_ls__a41oi_2.pxi.spice b/cells/a41oi/sky130_fd_sc_ls__a41oi_2.pxi.spice
index aec952c..c421366 100644
--- a/cells/a41oi/sky130_fd_sc_ls__a41oi_2.pxi.spice
+++ b/cells/a41oi/sky130_fd_sc_ls__a41oi_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a41oi_2.pxi.spice
-* Created: Fri Aug 28 13:02:00 2020
+* Created: Wed Sep 2 10:53:52 2020
*
x_PM_SKY130_FD_SC_LS__A41OI_2%B1 N_B1_c_93_n N_B1_M1006_g N_B1_M1007_g
+ N_B1_c_94_n N_B1_M1009_g B1 B1 N_B1_c_91_n N_B1_c_92_n
diff --git a/cells/a41oi/sky130_fd_sc_ls__a41oi_2.spice b/cells/a41oi/sky130_fd_sc_ls__a41oi_2.spice
index 759d108..bf9b0da 100644
--- a/cells/a41oi/sky130_fd_sc_ls__a41oi_2.spice
+++ b/cells/a41oi/sky130_fd_sc_ls__a41oi_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a41oi_2.spice
-* Created: Fri Aug 28 13:02:00 2020
+* Created: Wed Sep 2 10:53:52 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a41oi/sky130_fd_sc_ls__a41oi_4.lvs.report b/cells/a41oi/sky130_fd_sc_ls__a41oi_4.lvs.report
new file mode 100644
index 0000000..0578357
--- /dev/null
+++ b/cells/a41oi/sky130_fd_sc_ls__a41oi_4.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__a41oi_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__a41oi_4.sp ('sky130_fd_sc_ls__a41oi_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/a41oi/sky130_fd_sc_ls__a41oi_4.spice ('sky130_fd_sc_ls__a41oi_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:53:56 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__a41oi_4 sky130_fd_sc_ls__a41oi_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__a41oi_4
+SOURCE CELL NAME: sky130_fd_sc_ls__a41oi_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 14 14
+
+ Instances: 18 18 MN (4 pins)
+ 20 20 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 39 38
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 10 10
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 SMN4 (6 pins)
+ 1 1 SPMP_4_1 (7 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 SMN4
+ 1 1 0 0 SPMP_4_1
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 38 layout mos transistors were reduced to 10.
+ 28 mos transistors were deleted by parallel reduction.
+ 38 source mos transistors were reduced to 10.
+ 28 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1 A1 A2 A3 A4 Y VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a41oi/sky130_fd_sc_ls__a41oi_4.pex.spice b/cells/a41oi/sky130_fd_sc_ls__a41oi_4.pex.spice
index 1b0e54e..8590060 100644
--- a/cells/a41oi/sky130_fd_sc_ls__a41oi_4.pex.spice
+++ b/cells/a41oi/sky130_fd_sc_ls__a41oi_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a41oi_4.pex.spice
-* Created: Fri Aug 28 13:02:16 2020
+* Created: Wed Sep 2 10:53:59 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a41oi/sky130_fd_sc_ls__a41oi_4.pxi.spice b/cells/a41oi/sky130_fd_sc_ls__a41oi_4.pxi.spice
index af88811..05047ef 100644
--- a/cells/a41oi/sky130_fd_sc_ls__a41oi_4.pxi.spice
+++ b/cells/a41oi/sky130_fd_sc_ls__a41oi_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a41oi_4.pxi.spice
-* Created: Fri Aug 28 13:02:16 2020
+* Created: Wed Sep 2 10:53:59 2020
*
x_PM_SKY130_FD_SC_LS__A41OI_4%B1 N_B1_M1011_g N_B1_c_154_n N_B1_M1000_g
+ N_B1_M1033_g N_B1_c_155_n N_B1_M1016_g N_B1_c_156_n N_B1_M1020_g N_B1_c_151_n
diff --git a/cells/a41oi/sky130_fd_sc_ls__a41oi_4.spice b/cells/a41oi/sky130_fd_sc_ls__a41oi_4.spice
index 17e6f91..9573a00 100644
--- a/cells/a41oi/sky130_fd_sc_ls__a41oi_4.spice
+++ b/cells/a41oi/sky130_fd_sc_ls__a41oi_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__a41oi_4.spice
-* Created: Fri Aug 28 13:02:16 2020
+* Created: Wed Sep 2 10:53:59 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/and2/sky130_fd_sc_ls__and2_1.lvs.report b/cells/and2/sky130_fd_sc_ls__and2_1.lvs.report
new file mode 100644
index 0000000..d1e66ac
--- /dev/null
+++ b/cells/and2/sky130_fd_sc_ls__and2_1.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__and2_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__and2_1.sp ('sky130_fd_sc_ls__and2_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/and2/sky130_fd_sc_ls__and2_1.spice ('sky130_fd_sc_ls__and2_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:54:02 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__and2_1 sky130_fd_sc_ls__and2_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__and2_1
+SOURCE CELL NAME: sky130_fd_sc_ls__and2_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 9 9
+
+ Instances: 3 3 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 7 6
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 1 1 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 3 3 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A B VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/and2/sky130_fd_sc_ls__and2_1.pex.spice b/cells/and2/sky130_fd_sc_ls__and2_1.pex.spice
index 21fe3ca..ad1d228 100644
--- a/cells/and2/sky130_fd_sc_ls__and2_1.pex.spice
+++ b/cells/and2/sky130_fd_sc_ls__and2_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__and2_1.pex.spice
-* Created: Fri Aug 28 13:02:36 2020
+* Created: Wed Sep 2 10:54:05 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/and2/sky130_fd_sc_ls__and2_1.pxi.spice b/cells/and2/sky130_fd_sc_ls__and2_1.pxi.spice
index a02939e..6b07de1 100644
--- a/cells/and2/sky130_fd_sc_ls__and2_1.pxi.spice
+++ b/cells/and2/sky130_fd_sc_ls__and2_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__and2_1.pxi.spice
-* Created: Fri Aug 28 13:02:36 2020
+* Created: Wed Sep 2 10:54:05 2020
*
x_PM_SKY130_FD_SC_LS__AND2_1%A N_A_c_47_n N_A_M1002_g N_A_c_49_n N_A_c_54_n
+ N_A_M1004_g N_A_c_50_n A A N_A_c_52_n PM_SKY130_FD_SC_LS__AND2_1%A
diff --git a/cells/and2/sky130_fd_sc_ls__and2_1.spice b/cells/and2/sky130_fd_sc_ls__and2_1.spice
index 7685457..03ef898 100644
--- a/cells/and2/sky130_fd_sc_ls__and2_1.spice
+++ b/cells/and2/sky130_fd_sc_ls__and2_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__and2_1.spice
-* Created: Fri Aug 28 13:02:36 2020
+* Created: Wed Sep 2 10:54:05 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/and2/sky130_fd_sc_ls__and2_2.lvs.report b/cells/and2/sky130_fd_sc_ls__and2_2.lvs.report
new file mode 100644
index 0000000..912bf05
--- /dev/null
+++ b/cells/and2/sky130_fd_sc_ls__and2_2.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__and2_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__and2_2.sp ('sky130_fd_sc_ls__and2_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/and2/sky130_fd_sc_ls__and2_2.spice ('sky130_fd_sc_ls__and2_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:54:09 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__and2_2 sky130_fd_sc_ls__and2_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__and2_2
+SOURCE CELL NAME: sky130_fd_sc_ls__and2_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 9 9
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 1 1 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 3 3 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A B VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/and2/sky130_fd_sc_ls__and2_2.pex.spice b/cells/and2/sky130_fd_sc_ls__and2_2.pex.spice
index f1bbb9d..9df4d33 100644
--- a/cells/and2/sky130_fd_sc_ls__and2_2.pex.spice
+++ b/cells/and2/sky130_fd_sc_ls__and2_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__and2_2.pex.spice
-* Created: Fri Aug 28 13:02:45 2020
+* Created: Wed Sep 2 10:54:12 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/and2/sky130_fd_sc_ls__and2_2.pxi.spice b/cells/and2/sky130_fd_sc_ls__and2_2.pxi.spice
index 7b9a362..6d36fcd 100644
--- a/cells/and2/sky130_fd_sc_ls__and2_2.pxi.spice
+++ b/cells/and2/sky130_fd_sc_ls__and2_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__and2_2.pxi.spice
-* Created: Fri Aug 28 13:02:45 2020
+* Created: Wed Sep 2 10:54:12 2020
*
x_PM_SKY130_FD_SC_LS__AND2_2%A N_A_c_52_n N_A_c_57_n N_A_M1005_g N_A_M1003_g A
+ N_A_c_54_n N_A_c_55_n PM_SKY130_FD_SC_LS__AND2_2%A
diff --git a/cells/and2/sky130_fd_sc_ls__and2_2.spice b/cells/and2/sky130_fd_sc_ls__and2_2.spice
index 61e5eaa..bbaa16a 100644
--- a/cells/and2/sky130_fd_sc_ls__and2_2.spice
+++ b/cells/and2/sky130_fd_sc_ls__and2_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__and2_2.spice
-* Created: Fri Aug 28 13:02:45 2020
+* Created: Wed Sep 2 10:54:12 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/and2/sky130_fd_sc_ls__and2_4.lvs.report b/cells/and2/sky130_fd_sc_ls__and2_4.lvs.report
new file mode 100644
index 0000000..503ce3d
--- /dev/null
+++ b/cells/and2/sky130_fd_sc_ls__and2_4.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__and2_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__and2_4.sp ('sky130_fd_sc_ls__and2_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/and2/sky130_fd_sc_ls__and2_4.spice ('sky130_fd_sc_ls__and2_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:54:15 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__and2_4 sky130_fd_sc_ls__and2_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__and2_4
+SOURCE CELL NAME: sky130_fd_sc_ls__and2_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 9 9
+
+ Instances: 8 8 MN (4 pins)
+ 8 8 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 17 16
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 1 1 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 3 3 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 16 layout mos transistors were reduced to 6.
+ 10 mos transistors were deleted by parallel reduction.
+ 16 source mos transistors were reduced to 6.
+ 10 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A B VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/and2/sky130_fd_sc_ls__and2_4.pex.spice b/cells/and2/sky130_fd_sc_ls__and2_4.pex.spice
index 635b979..1b25ef6 100644
--- a/cells/and2/sky130_fd_sc_ls__and2_4.pex.spice
+++ b/cells/and2/sky130_fd_sc_ls__and2_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__and2_4.pex.spice
-* Created: Fri Aug 28 13:02:54 2020
+* Created: Wed Sep 2 10:54:18 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/and2/sky130_fd_sc_ls__and2_4.pxi.spice b/cells/and2/sky130_fd_sc_ls__and2_4.pxi.spice
index 30140e5..35c7b53 100644
--- a/cells/and2/sky130_fd_sc_ls__and2_4.pxi.spice
+++ b/cells/and2/sky130_fd_sc_ls__and2_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__and2_4.pxi.spice
-* Created: Fri Aug 28 13:02:54 2020
+* Created: Wed Sep 2 10:54:18 2020
*
x_PM_SKY130_FD_SC_LS__AND2_4%A_83_269# N_A_83_269#_M1001_d N_A_83_269#_M1005_s
+ N_A_83_269#_M1014_s N_A_83_269#_c_84_n N_A_83_269#_M1000_g N_A_83_269#_c_94_n
diff --git a/cells/and2/sky130_fd_sc_ls__and2_4.spice b/cells/and2/sky130_fd_sc_ls__and2_4.spice
index 516decb..35b49ce 100644
--- a/cells/and2/sky130_fd_sc_ls__and2_4.spice
+++ b/cells/and2/sky130_fd_sc_ls__and2_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__and2_4.spice
-* Created: Fri Aug 28 13:02:54 2020
+* Created: Wed Sep 2 10:54:18 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/and2b/sky130_fd_sc_ls__and2b_1.lvs.report b/cells/and2b/sky130_fd_sc_ls__and2b_1.lvs.report
new file mode 100644
index 0000000..532a221
--- /dev/null
+++ b/cells/and2b/sky130_fd_sc_ls__and2b_1.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__and2b_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__and2b_1.sp ('sky130_fd_sc_ls__and2b_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/and2b/sky130_fd_sc_ls__and2b_1.spice ('sky130_fd_sc_ls__and2b_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:54:22 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__and2b_1 sky130_fd_sc_ls__and2b_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__and2b_1
+SOURCE CELL NAME: sky130_fd_sc_ls__and2b_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 10 10
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 9 9
+
+ Instances: 2 2 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ ------ ------
+ Total Inst: 7 7
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 4 4 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ ------- ------- --------- ---------
+ Total Inst: 7 7 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A_N B VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/and2b/sky130_fd_sc_ls__and2b_1.pex.spice b/cells/and2b/sky130_fd_sc_ls__and2b_1.pex.spice
index 7ab9c05..1d1c9e8 100644
--- a/cells/and2b/sky130_fd_sc_ls__and2b_1.pex.spice
+++ b/cells/and2b/sky130_fd_sc_ls__and2b_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__and2b_1.pex.spice
-* Created: Fri Aug 28 13:03:04 2020
+* Created: Wed Sep 2 10:54:24 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/and2b/sky130_fd_sc_ls__and2b_1.pxi.spice b/cells/and2b/sky130_fd_sc_ls__and2b_1.pxi.spice
index 9c35591..3a2c946 100644
--- a/cells/and2b/sky130_fd_sc_ls__and2b_1.pxi.spice
+++ b/cells/and2b/sky130_fd_sc_ls__and2b_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__and2b_1.pxi.spice
-* Created: Fri Aug 28 13:03:04 2020
+* Created: Wed Sep 2 10:54:24 2020
*
x_PM_SKY130_FD_SC_LS__AND2B_1%A_N N_A_N_M1006_g N_A_N_c_62_n N_A_N_c_66_n
+ N_A_N_M1003_g A_N A_N N_A_N_c_63_n N_A_N_c_64_n
diff --git a/cells/and2b/sky130_fd_sc_ls__and2b_1.spice b/cells/and2b/sky130_fd_sc_ls__and2b_1.spice
index 4f36319..898841f 100644
--- a/cells/and2b/sky130_fd_sc_ls__and2b_1.spice
+++ b/cells/and2b/sky130_fd_sc_ls__and2b_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__and2b_1.spice
-* Created: Fri Aug 28 13:03:04 2020
+* Created: Wed Sep 2 10:54:24 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/and2b/sky130_fd_sc_ls__and2b_2.lvs.report b/cells/and2b/sky130_fd_sc_ls__and2b_2.lvs.report
new file mode 100644
index 0000000..af36daa
--- /dev/null
+++ b/cells/and2b/sky130_fd_sc_ls__and2b_2.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__and2b_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__and2b_2.sp ('sky130_fd_sc_ls__and2b_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/and2b/sky130_fd_sc_ls__and2b_2.spice ('sky130_fd_sc_ls__and2b_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:54:28 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__and2b_2 sky130_fd_sc_ls__and2b_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__and2b_2
+SOURCE CELL NAME: sky130_fd_sc_ls__and2b_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 10 10
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 9 9
+
+ Instances: 2 2 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ ------ ------
+ Total Inst: 7 7
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 4 4 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ ------- ------- --------- ---------
+ Total Inst: 7 7 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A_N B VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/and2b/sky130_fd_sc_ls__and2b_2.pex.spice b/cells/and2b/sky130_fd_sc_ls__and2b_2.pex.spice
index fcfd64a..0025083 100644
--- a/cells/and2b/sky130_fd_sc_ls__and2b_2.pex.spice
+++ b/cells/and2b/sky130_fd_sc_ls__and2b_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__and2b_2.pex.spice
-* Created: Fri Aug 28 13:03:20 2020
+* Created: Wed Sep 2 10:54:31 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/and2b/sky130_fd_sc_ls__and2b_2.pxi.spice b/cells/and2b/sky130_fd_sc_ls__and2b_2.pxi.spice
index f6cbbc4..5daf66d 100644
--- a/cells/and2b/sky130_fd_sc_ls__and2b_2.pxi.spice
+++ b/cells/and2b/sky130_fd_sc_ls__and2b_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__and2b_2.pxi.spice
-* Created: Fri Aug 28 13:03:20 2020
+* Created: Wed Sep 2 10:54:31 2020
*
x_PM_SKY130_FD_SC_LS__AND2B_2%A_N N_A_N_M1007_g N_A_N_c_59_n N_A_N_M1005_g A_N
+ N_A_N_c_60_n PM_SKY130_FD_SC_LS__AND2B_2%A_N
diff --git a/cells/and2b/sky130_fd_sc_ls__and2b_2.spice b/cells/and2b/sky130_fd_sc_ls__and2b_2.spice
index dcd24ce..9faeb79 100644
--- a/cells/and2b/sky130_fd_sc_ls__and2b_2.spice
+++ b/cells/and2b/sky130_fd_sc_ls__and2b_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__and2b_2.spice
-* Created: Fri Aug 28 13:03:20 2020
+* Created: Wed Sep 2 10:54:31 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/and2b/sky130_fd_sc_ls__and2b_4.lvs.report b/cells/and2b/sky130_fd_sc_ls__and2b_4.lvs.report
new file mode 100644
index 0000000..ca70b57
--- /dev/null
+++ b/cells/and2b/sky130_fd_sc_ls__and2b_4.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__and2b_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__and2b_4.sp ('sky130_fd_sc_ls__and2b_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/and2b/sky130_fd_sc_ls__and2b_4.spice ('sky130_fd_sc_ls__and2b_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:54:34 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__and2b_4 sky130_fd_sc_ls__and2b_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__and2b_4
+SOURCE CELL NAME: sky130_fd_sc_ls__and2b_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 10 10
+
+ Instances: 9 9 MN (4 pins)
+ 9 9 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 19 18
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 9 9
+
+ Instances: 2 2 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ ------ ------
+ Total Inst: 7 7
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 4 4 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ ------- ------- --------- ---------
+ Total Inst: 7 7 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 16 layout mos transistors were reduced to 6.
+ 10 mos transistors were deleted by parallel reduction.
+ 16 source mos transistors were reduced to 6.
+ 10 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A_N B VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/and2b/sky130_fd_sc_ls__and2b_4.pex.spice b/cells/and2b/sky130_fd_sc_ls__and2b_4.pex.spice
index d6e614d..324b527 100644
--- a/cells/and2b/sky130_fd_sc_ls__and2b_4.pex.spice
+++ b/cells/and2b/sky130_fd_sc_ls__and2b_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__and2b_4.pex.spice
-* Created: Fri Aug 28 13:03:40 2020
+* Created: Wed Sep 2 10:54:37 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/and2b/sky130_fd_sc_ls__and2b_4.pxi.spice b/cells/and2b/sky130_fd_sc_ls__and2b_4.pxi.spice
index ff04738..d85b67b 100644
--- a/cells/and2b/sky130_fd_sc_ls__and2b_4.pxi.spice
+++ b/cells/and2b/sky130_fd_sc_ls__and2b_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__and2b_4.pxi.spice
-* Created: Fri Aug 28 13:03:40 2020
+* Created: Wed Sep 2 10:54:37 2020
*
x_PM_SKY130_FD_SC_LS__AND2B_4%A_N N_A_N_c_109_n N_A_N_M1017_g N_A_N_M1009_g A_N
+ PM_SKY130_FD_SC_LS__AND2B_4%A_N
diff --git a/cells/and2b/sky130_fd_sc_ls__and2b_4.spice b/cells/and2b/sky130_fd_sc_ls__and2b_4.spice
index ab6b7d5..91f2819 100644
--- a/cells/and2b/sky130_fd_sc_ls__and2b_4.spice
+++ b/cells/and2b/sky130_fd_sc_ls__and2b_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__and2b_4.spice
-* Created: Fri Aug 28 13:03:40 2020
+* Created: Wed Sep 2 10:54:37 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/and3/sky130_fd_sc_ls__and3_1.lvs.report b/cells/and3/sky130_fd_sc_ls__and3_1.lvs.report
new file mode 100644
index 0000000..f3d1982
--- /dev/null
+++ b/cells/and3/sky130_fd_sc_ls__and3_1.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__and3_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__and3_1.sp ('sky130_fd_sc_ls__and3_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/and3/sky130_fd_sc_ls__and3_1.spice ('sky130_fd_sc_ls__and3_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:54:42 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__and3_1 sky130_fd_sc_ls__and3_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__and3_1
+SOURCE CELL NAME: sky130_fd_sc_ls__and3_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 11 11
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 9 9
+
+ Instances: 1 1 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 1 SMN3 (5 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 4 4 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN3
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A B C VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/and3/sky130_fd_sc_ls__and3_1.pex.spice b/cells/and3/sky130_fd_sc_ls__and3_1.pex.spice
index 71b70b2..318c028 100644
--- a/cells/and3/sky130_fd_sc_ls__and3_1.pex.spice
+++ b/cells/and3/sky130_fd_sc_ls__and3_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__and3_1.pex.spice
-* Created: Fri Aug 28 13:03:50 2020
+* Created: Wed Sep 2 10:54:45 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/and3/sky130_fd_sc_ls__and3_1.pxi.spice b/cells/and3/sky130_fd_sc_ls__and3_1.pxi.spice
index 9be8aa1..c488151 100644
--- a/cells/and3/sky130_fd_sc_ls__and3_1.pxi.spice
+++ b/cells/and3/sky130_fd_sc_ls__and3_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__and3_1.pxi.spice
-* Created: Fri Aug 28 13:03:50 2020
+* Created: Wed Sep 2 10:54:45 2020
*
x_PM_SKY130_FD_SC_LS__AND3_1%A N_A_c_54_n N_A_c_62_n N_A_M1006_g N_A_c_55_n
+ N_A_M1001_g N_A_c_57_n N_A_c_58_n A N_A_c_60_n PM_SKY130_FD_SC_LS__AND3_1%A
diff --git a/cells/and3/sky130_fd_sc_ls__and3_1.spice b/cells/and3/sky130_fd_sc_ls__and3_1.spice
index c65aa14..a92e1e2 100644
--- a/cells/and3/sky130_fd_sc_ls__and3_1.spice
+++ b/cells/and3/sky130_fd_sc_ls__and3_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__and3_1.spice
-* Created: Fri Aug 28 13:03:50 2020
+* Created: Wed Sep 2 10:54:45 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/and3/sky130_fd_sc_ls__and3_2.lvs.report b/cells/and3/sky130_fd_sc_ls__and3_2.lvs.report
new file mode 100644
index 0000000..299dbdd
--- /dev/null
+++ b/cells/and3/sky130_fd_sc_ls__and3_2.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__and3_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__and3_2.sp ('sky130_fd_sc_ls__and3_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/and3/sky130_fd_sc_ls__and3_2.spice ('sky130_fd_sc_ls__and3_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:54:48 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__and3_2 sky130_fd_sc_ls__and3_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__and3_2
+SOURCE CELL NAME: sky130_fd_sc_ls__and3_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 11 11
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 9 9
+
+ Instances: 1 1 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 1 SMN3 (5 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 4 4 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN3
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A B C VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/and3/sky130_fd_sc_ls__and3_2.pex.spice b/cells/and3/sky130_fd_sc_ls__and3_2.pex.spice
index 382a332..01bda32 100644
--- a/cells/and3/sky130_fd_sc_ls__and3_2.pex.spice
+++ b/cells/and3/sky130_fd_sc_ls__and3_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__and3_2.pex.spice
-* Created: Fri Aug 28 13:03:59 2020
+* Created: Wed Sep 2 10:54:51 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/and3/sky130_fd_sc_ls__and3_2.pxi.spice b/cells/and3/sky130_fd_sc_ls__and3_2.pxi.spice
index b3d65fb..8e2ea94 100644
--- a/cells/and3/sky130_fd_sc_ls__and3_2.pxi.spice
+++ b/cells/and3/sky130_fd_sc_ls__and3_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__and3_2.pxi.spice
-* Created: Fri Aug 28 13:03:59 2020
+* Created: Wed Sep 2 10:54:51 2020
*
x_PM_SKY130_FD_SC_LS__AND3_2%A N_A_c_56_n N_A_c_57_n N_A_c_63_n N_A_M1000_g
+ N_A_c_58_n N_A_M1006_g A A A N_A_c_61_n PM_SKY130_FD_SC_LS__AND3_2%A
diff --git a/cells/and3/sky130_fd_sc_ls__and3_2.spice b/cells/and3/sky130_fd_sc_ls__and3_2.spice
index d9d2261..dfea8fb 100644
--- a/cells/and3/sky130_fd_sc_ls__and3_2.spice
+++ b/cells/and3/sky130_fd_sc_ls__and3_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__and3_2.spice
-* Created: Fri Aug 28 13:03:59 2020
+* Created: Wed Sep 2 10:54:51 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/and3/sky130_fd_sc_ls__and3_4.lvs.report b/cells/and3/sky130_fd_sc_ls__and3_4.lvs.report
new file mode 100644
index 0000000..4af0957
--- /dev/null
+++ b/cells/and3/sky130_fd_sc_ls__and3_4.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__and3_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__and3_4.sp ('sky130_fd_sc_ls__and3_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/and3/sky130_fd_sc_ls__and3_4.spice ('sky130_fd_sc_ls__and3_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:54:55 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__and3_4 sky130_fd_sc_ls__and3_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__and3_4
+SOURCE CELL NAME: sky130_fd_sc_ls__and3_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 11 11
+
+ Instances: 10 10 MN (4 pins)
+ 10 10 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 21 20
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 9 9
+
+ Instances: 1 1 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 1 SMN3 (5 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 4 4 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN3
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 20 layout mos transistors were reduced to 8.
+ 12 mos transistors were deleted by parallel reduction.
+ 20 source mos transistors were reduced to 8.
+ 12 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB C B A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/and3/sky130_fd_sc_ls__and3_4.pex.spice b/cells/and3/sky130_fd_sc_ls__and3_4.pex.spice
index b5687bc..e4845cb 100644
--- a/cells/and3/sky130_fd_sc_ls__and3_4.pex.spice
+++ b/cells/and3/sky130_fd_sc_ls__and3_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__and3_4.pex.spice
-* Created: Fri Aug 28 13:04:08 2020
+* Created: Wed Sep 2 10:54:58 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/and3/sky130_fd_sc_ls__and3_4.pxi.spice b/cells/and3/sky130_fd_sc_ls__and3_4.pxi.spice
index 883a5cf..93d89b0 100644
--- a/cells/and3/sky130_fd_sc_ls__and3_4.pxi.spice
+++ b/cells/and3/sky130_fd_sc_ls__and3_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__and3_4.pxi.spice
-* Created: Fri Aug 28 13:04:08 2020
+* Created: Wed Sep 2 10:54:58 2020
*
x_PM_SKY130_FD_SC_LS__AND3_4%A_83_260# N_A_83_260#_M1007_d N_A_83_260#_M1003_d
+ N_A_83_260#_M1004_s N_A_83_260#_M1005_d N_A_83_260#_c_119_n
diff --git a/cells/and3/sky130_fd_sc_ls__and3_4.spice b/cells/and3/sky130_fd_sc_ls__and3_4.spice
index eb27393..9e94ea6 100644
--- a/cells/and3/sky130_fd_sc_ls__and3_4.spice
+++ b/cells/and3/sky130_fd_sc_ls__and3_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__and3_4.spice
-* Created: Fri Aug 28 13:04:08 2020
+* Created: Wed Sep 2 10:54:58 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/and3b/sky130_fd_sc_ls__and3b_1.lvs.report b/cells/and3b/sky130_fd_sc_ls__and3b_1.lvs.report
new file mode 100644
index 0000000..0624bfa
--- /dev/null
+++ b/cells/and3b/sky130_fd_sc_ls__and3b_1.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__and3b_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__and3b_1.sp ('sky130_fd_sc_ls__and3b_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/and3b/sky130_fd_sc_ls__and3b_1.spice ('sky130_fd_sc_ls__and3b_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:55:01 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__and3b_1 sky130_fd_sc_ls__and3b_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__and3b_1
+SOURCE CELL NAME: sky130_fd_sc_ls__and3b_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 12 12
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 10 10
+
+ Instances: 2 2 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 1 SMN3 (5 pins)
+ ------ ------
+ Total Inst: 8 8
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 5 5 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN3
+ ------- ------- --------- ---------
+ Total Inst: 8 8 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A_N B C VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/and3b/sky130_fd_sc_ls__and3b_1.pex.spice b/cells/and3b/sky130_fd_sc_ls__and3b_1.pex.spice
index 8e1a64b..cbdab23 100644
--- a/cells/and3b/sky130_fd_sc_ls__and3b_1.pex.spice
+++ b/cells/and3b/sky130_fd_sc_ls__and3b_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__and3b_1.pex.spice
-* Created: Fri Aug 28 13:04:24 2020
+* Created: Wed Sep 2 10:55:04 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/and3b/sky130_fd_sc_ls__and3b_1.pxi.spice b/cells/and3b/sky130_fd_sc_ls__and3b_1.pxi.spice
index 6d4ede0..71058da 100644
--- a/cells/and3b/sky130_fd_sc_ls__and3b_1.pxi.spice
+++ b/cells/and3b/sky130_fd_sc_ls__and3b_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__and3b_1.pxi.spice
-* Created: Fri Aug 28 13:04:24 2020
+* Created: Wed Sep 2 10:55:04 2020
*
x_PM_SKY130_FD_SC_LS__AND3B_1%A_N N_A_N_M1008_g N_A_N_M1006_g N_A_N_c_69_n
+ N_A_N_c_70_n N_A_N_c_74_n N_A_N_c_75_n A_N A_N N_A_N_c_71_n N_A_N_c_72_n
diff --git a/cells/and3b/sky130_fd_sc_ls__and3b_1.spice b/cells/and3b/sky130_fd_sc_ls__and3b_1.spice
index c957ffb..be955e8 100644
--- a/cells/and3b/sky130_fd_sc_ls__and3b_1.spice
+++ b/cells/and3b/sky130_fd_sc_ls__and3b_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__and3b_1.spice
-* Created: Fri Aug 28 13:04:24 2020
+* Created: Wed Sep 2 10:55:04 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/and3b/sky130_fd_sc_ls__and3b_2.lvs.report b/cells/and3b/sky130_fd_sc_ls__and3b_2.lvs.report
new file mode 100644
index 0000000..5d885c9
--- /dev/null
+++ b/cells/and3b/sky130_fd_sc_ls__and3b_2.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__and3b_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__and3b_2.sp ('sky130_fd_sc_ls__and3b_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/and3b/sky130_fd_sc_ls__and3b_2.spice ('sky130_fd_sc_ls__and3b_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:55:08 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__and3b_2 sky130_fd_sc_ls__and3b_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__and3b_2
+SOURCE CELL NAME: sky130_fd_sc_ls__and3b_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 12 12
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 10 10
+
+ Instances: 2 2 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 1 SMN3 (5 pins)
+ ------ ------
+ Total Inst: 8 8
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 5 5 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN3
+ ------- ------- --------- ---------
+ Total Inst: 8 8 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A_N B C VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/and3b/sky130_fd_sc_ls__and3b_2.pex.spice b/cells/and3b/sky130_fd_sc_ls__and3b_2.pex.spice
index 96a00ad..61b9dfa 100644
--- a/cells/and3b/sky130_fd_sc_ls__and3b_2.pex.spice
+++ b/cells/and3b/sky130_fd_sc_ls__and3b_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__and3b_2.pex.spice
-* Created: Fri Aug 28 13:04:44 2020
+* Created: Wed Sep 2 10:55:11 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/and3b/sky130_fd_sc_ls__and3b_2.pxi.spice b/cells/and3b/sky130_fd_sc_ls__and3b_2.pxi.spice
index db18437..ef43b50 100644
--- a/cells/and3b/sky130_fd_sc_ls__and3b_2.pxi.spice
+++ b/cells/and3b/sky130_fd_sc_ls__and3b_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__and3b_2.pxi.spice
-* Created: Fri Aug 28 13:04:44 2020
+* Created: Wed Sep 2 10:55:11 2020
*
x_PM_SKY130_FD_SC_LS__AND3B_2%A_N N_A_N_c_76_n N_A_N_M1010_g N_A_N_c_81_n
+ N_A_N_M1007_g A_N N_A_N_c_78_n N_A_N_c_79_n PM_SKY130_FD_SC_LS__AND3B_2%A_N
diff --git a/cells/and3b/sky130_fd_sc_ls__and3b_2.spice b/cells/and3b/sky130_fd_sc_ls__and3b_2.spice
index bbdd2d5..fee31ff 100644
--- a/cells/and3b/sky130_fd_sc_ls__and3b_2.spice
+++ b/cells/and3b/sky130_fd_sc_ls__and3b_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__and3b_2.spice
-* Created: Fri Aug 28 13:04:44 2020
+* Created: Wed Sep 2 10:55:11 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/and3b/sky130_fd_sc_ls__and3b_4.lvs.report b/cells/and3b/sky130_fd_sc_ls__and3b_4.lvs.report
new file mode 100644
index 0000000..ba213f2
--- /dev/null
+++ b/cells/and3b/sky130_fd_sc_ls__and3b_4.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__and3b_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__and3b_4.sp ('sky130_fd_sc_ls__and3b_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/and3b/sky130_fd_sc_ls__and3b_4.spice ('sky130_fd_sc_ls__and3b_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:55:15 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__and3b_4 sky130_fd_sc_ls__and3b_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__and3b_4
+SOURCE CELL NAME: sky130_fd_sc_ls__and3b_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 12 12
+
+ Instances: 11 11 MN (4 pins)
+ 11 11 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 23 22
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 10 10
+
+ Instances: 2 2 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 1 SMN3 (5 pins)
+ ------ ------
+ Total Inst: 8 8
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 5 5 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN3
+ ------- ------- --------- ---------
+ Total Inst: 8 8 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 20 layout mos transistors were reduced to 8.
+ 12 mos transistors were deleted by parallel reduction.
+ 20 source mos transistors were reduced to 8.
+ 12 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A_N B C VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/and3b/sky130_fd_sc_ls__and3b_4.pex.spice b/cells/and3b/sky130_fd_sc_ls__and3b_4.pex.spice
index 453f0d7..1f932b4 100644
--- a/cells/and3b/sky130_fd_sc_ls__and3b_4.pex.spice
+++ b/cells/and3b/sky130_fd_sc_ls__and3b_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__and3b_4.pex.spice
-* Created: Fri Aug 28 13:04:52 2020
+* Created: Wed Sep 2 10:55:18 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/and3b/sky130_fd_sc_ls__and3b_4.pxi.spice b/cells/and3b/sky130_fd_sc_ls__and3b_4.pxi.spice
index 502ef4c..247ad61 100644
--- a/cells/and3b/sky130_fd_sc_ls__and3b_4.pxi.spice
+++ b/cells/and3b/sky130_fd_sc_ls__and3b_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__and3b_4.pxi.spice
-* Created: Fri Aug 28 13:04:52 2020
+* Created: Wed Sep 2 10:55:18 2020
*
x_PM_SKY130_FD_SC_LS__AND3B_4%A_N N_A_N_M1019_g N_A_N_c_125_n N_A_N_M1013_g A_N
+ PM_SKY130_FD_SC_LS__AND3B_4%A_N
diff --git a/cells/and3b/sky130_fd_sc_ls__and3b_4.spice b/cells/and3b/sky130_fd_sc_ls__and3b_4.spice
index 60c72a7..19f234b 100644
--- a/cells/and3b/sky130_fd_sc_ls__and3b_4.spice
+++ b/cells/and3b/sky130_fd_sc_ls__and3b_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__and3b_4.spice
-* Created: Fri Aug 28 13:04:52 2020
+* Created: Wed Sep 2 10:55:18 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/and4/sky130_fd_sc_ls__and4_1.lvs.report b/cells/and4/sky130_fd_sc_ls__and4_1.lvs.report
new file mode 100644
index 0000000..00c2715
--- /dev/null
+++ b/cells/and4/sky130_fd_sc_ls__and4_1.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__and4_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__and4_1.sp ('sky130_fd_sc_ls__and4_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/and4/sky130_fd_sc_ls__and4_1.spice ('sky130_fd_sc_ls__and4_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:55:22 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__and4_1 sky130_fd_sc_ls__and4_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__and4_1
+SOURCE CELL NAME: sky130_fd_sc_ls__and4_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 1 1 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 1 SMN4 (6 pins)
+ ------ ------
+ Total Inst: 7 7
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 5 5 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN4
+ ------- ------- --------- ---------
+ Total Inst: 7 7 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A B C D VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/and4/sky130_fd_sc_ls__and4_1.pex.spice b/cells/and4/sky130_fd_sc_ls__and4_1.pex.spice
index d85cab0..19b8999 100644
--- a/cells/and4/sky130_fd_sc_ls__and4_1.pex.spice
+++ b/cells/and4/sky130_fd_sc_ls__and4_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__and4_1.pex.spice
-* Created: Fri Aug 28 13:05:01 2020
+* Created: Wed Sep 2 10:55:25 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/and4/sky130_fd_sc_ls__and4_1.pxi.spice b/cells/and4/sky130_fd_sc_ls__and4_1.pxi.spice
index 01bb2e3..c00dce0 100644
--- a/cells/and4/sky130_fd_sc_ls__and4_1.pxi.spice
+++ b/cells/and4/sky130_fd_sc_ls__and4_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__and4_1.pxi.spice
-* Created: Fri Aug 28 13:05:01 2020
+* Created: Wed Sep 2 10:55:25 2020
*
x_PM_SKY130_FD_SC_LS__AND4_1%A N_A_c_76_n N_A_c_77_n N_A_M1005_g N_A_M1007_g
+ N_A_c_71_n N_A_c_72_n N_A_c_73_n A A N_A_c_74_n N_A_c_75_n
diff --git a/cells/and4/sky130_fd_sc_ls__and4_1.spice b/cells/and4/sky130_fd_sc_ls__and4_1.spice
index 94d4a8e..6ab834c 100644
--- a/cells/and4/sky130_fd_sc_ls__and4_1.spice
+++ b/cells/and4/sky130_fd_sc_ls__and4_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__and4_1.spice
-* Created: Fri Aug 28 13:05:01 2020
+* Created: Wed Sep 2 10:55:25 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/and4/sky130_fd_sc_ls__and4_2.lvs.report b/cells/and4/sky130_fd_sc_ls__and4_2.lvs.report
new file mode 100644
index 0000000..e2021f8
--- /dev/null
+++ b/cells/and4/sky130_fd_sc_ls__and4_2.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__and4_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__and4_2.sp ('sky130_fd_sc_ls__and4_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/and4/sky130_fd_sc_ls__and4_2.spice ('sky130_fd_sc_ls__and4_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:55:28 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__and4_2 sky130_fd_sc_ls__and4_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__and4_2
+SOURCE CELL NAME: sky130_fd_sc_ls__and4_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 1 1 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 1 SMN4 (6 pins)
+ ------ ------
+ Total Inst: 7 7
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 5 5 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN4
+ ------- ------- --------- ---------
+ Total Inst: 7 7 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A B C D VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/and4/sky130_fd_sc_ls__and4_2.pex.spice b/cells/and4/sky130_fd_sc_ls__and4_2.pex.spice
index 21d4e22..65f78b8 100644
--- a/cells/and4/sky130_fd_sc_ls__and4_2.pex.spice
+++ b/cells/and4/sky130_fd_sc_ls__and4_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__and4_2.pex.spice
-* Created: Fri Aug 28 13:05:09 2020
+* Created: Wed Sep 2 10:55:31 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/and4/sky130_fd_sc_ls__and4_2.pxi.spice b/cells/and4/sky130_fd_sc_ls__and4_2.pxi.spice
index ed33a72..f1d97ce 100644
--- a/cells/and4/sky130_fd_sc_ls__and4_2.pxi.spice
+++ b/cells/and4/sky130_fd_sc_ls__and4_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__and4_2.pxi.spice
-* Created: Fri Aug 28 13:05:09 2020
+* Created: Wed Sep 2 10:55:31 2020
*
x_PM_SKY130_FD_SC_LS__AND4_2%A N_A_c_69_n N_A_c_75_n N_A_M1002_g N_A_M1007_g
+ N_A_c_71_n N_A_c_72_n A N_A_c_73_n PM_SKY130_FD_SC_LS__AND4_2%A
diff --git a/cells/and4/sky130_fd_sc_ls__and4_2.spice b/cells/and4/sky130_fd_sc_ls__and4_2.spice
index e758ebb..c339752 100644
--- a/cells/and4/sky130_fd_sc_ls__and4_2.spice
+++ b/cells/and4/sky130_fd_sc_ls__and4_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__and4_2.spice
-* Created: Fri Aug 28 13:05:09 2020
+* Created: Wed Sep 2 10:55:31 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/and4/sky130_fd_sc_ls__and4_4.lvs.report b/cells/and4/sky130_fd_sc_ls__and4_4.lvs.report
new file mode 100644
index 0000000..97d8630
--- /dev/null
+++ b/cells/and4/sky130_fd_sc_ls__and4_4.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__and4_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__and4_4.sp ('sky130_fd_sc_ls__and4_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/and4/sky130_fd_sc_ls__and4_4.spice ('sky130_fd_sc_ls__and4_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:55:34 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__and4_4 sky130_fd_sc_ls__and4_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__and4_4
+SOURCE CELL NAME: sky130_fd_sc_ls__and4_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 12 12 MN (4 pins)
+ 12 12 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 25 24
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 1 1 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 1 SMN4 (6 pins)
+ ------ ------
+ Total Inst: 7 7
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 5 5 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN4
+ ------- ------- --------- ---------
+ Total Inst: 7 7 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 24 layout mos transistors were reduced to 10.
+ 14 mos transistors were deleted by parallel reduction.
+ 24 source mos transistors were reduced to 10.
+ 14 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A B D C VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/and4/sky130_fd_sc_ls__and4_4.pex.spice b/cells/and4/sky130_fd_sc_ls__and4_4.pex.spice
index a377e88..5031521 100644
--- a/cells/and4/sky130_fd_sc_ls__and4_4.pex.spice
+++ b/cells/and4/sky130_fd_sc_ls__and4_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__and4_4.pex.spice
-* Created: Fri Aug 28 13:05:17 2020
+* Created: Wed Sep 2 10:55:37 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/and4/sky130_fd_sc_ls__and4_4.pxi.spice b/cells/and4/sky130_fd_sc_ls__and4_4.pxi.spice
index 426cb80..cc5405c 100644
--- a/cells/and4/sky130_fd_sc_ls__and4_4.pxi.spice
+++ b/cells/and4/sky130_fd_sc_ls__and4_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__and4_4.pxi.spice
-* Created: Fri Aug 28 13:05:17 2020
+* Created: Wed Sep 2 10:55:37 2020
*
x_PM_SKY130_FD_SC_LS__AND4_4%A N_A_M1001_g N_A_c_136_n N_A_M1000_g N_A_M1003_g
+ N_A_c_137_n N_A_M1015_g A N_A_c_135_n PM_SKY130_FD_SC_LS__AND4_4%A
diff --git a/cells/and4/sky130_fd_sc_ls__and4_4.spice b/cells/and4/sky130_fd_sc_ls__and4_4.spice
index e126459..515e3a5 100644
--- a/cells/and4/sky130_fd_sc_ls__and4_4.spice
+++ b/cells/and4/sky130_fd_sc_ls__and4_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__and4_4.spice
-* Created: Fri Aug 28 13:05:17 2020
+* Created: Wed Sep 2 10:55:37 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/and4b/sky130_fd_sc_ls__and4b_1.lvs.report b/cells/and4b/sky130_fd_sc_ls__and4b_1.lvs.report
new file mode 100644
index 0000000..8493bb5
--- /dev/null
+++ b/cells/and4b/sky130_fd_sc_ls__and4b_1.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__and4b_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__and4b_1.sp ('sky130_fd_sc_ls__and4b_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/and4b/sky130_fd_sc_ls__and4b_1.spice ('sky130_fd_sc_ls__and4b_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:55:41 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__and4b_1 sky130_fd_sc_ls__and4b_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__and4b_1
+SOURCE CELL NAME: sky130_fd_sc_ls__and4b_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 14 14
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 11 11
+
+ Instances: 2 2 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 1 SMN4 (6 pins)
+ ------ ------
+ Total Inst: 9 9
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 6 6 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN4
+ ------- ------- --------- ---------
+ Total Inst: 9 9 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A_N B C D VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/and4b/sky130_fd_sc_ls__and4b_1.pex.spice b/cells/and4b/sky130_fd_sc_ls__and4b_1.pex.spice
index 1ef38b2..334d912 100644
--- a/cells/and4b/sky130_fd_sc_ls__and4b_1.pex.spice
+++ b/cells/and4b/sky130_fd_sc_ls__and4b_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__and4b_1.pex.spice
-* Created: Fri Aug 28 13:05:32 2020
+* Created: Wed Sep 2 10:55:44 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/and4b/sky130_fd_sc_ls__and4b_1.pxi.spice b/cells/and4b/sky130_fd_sc_ls__and4b_1.pxi.spice
index 886b2f4..f895af5 100644
--- a/cells/and4b/sky130_fd_sc_ls__and4b_1.pxi.spice
+++ b/cells/and4b/sky130_fd_sc_ls__and4b_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__and4b_1.pxi.spice
-* Created: Fri Aug 28 13:05:32 2020
+* Created: Wed Sep 2 10:55:44 2020
*
x_PM_SKY130_FD_SC_LS__AND4B_1%A_N N_A_N_M1010_g N_A_N_c_85_n N_A_N_M1007_g
+ N_A_N_c_82_n A_N N_A_N_c_83_n N_A_N_c_84_n PM_SKY130_FD_SC_LS__AND4B_1%A_N
diff --git a/cells/and4b/sky130_fd_sc_ls__and4b_1.spice b/cells/and4b/sky130_fd_sc_ls__and4b_1.spice
index 33671f7..db94015 100644
--- a/cells/and4b/sky130_fd_sc_ls__and4b_1.spice
+++ b/cells/and4b/sky130_fd_sc_ls__and4b_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__and4b_1.spice
-* Created: Fri Aug 28 13:05:32 2020
+* Created: Wed Sep 2 10:55:44 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/and4b/sky130_fd_sc_ls__and4b_2.lvs.report b/cells/and4b/sky130_fd_sc_ls__and4b_2.lvs.report
new file mode 100644
index 0000000..7e6c8d4
--- /dev/null
+++ b/cells/and4b/sky130_fd_sc_ls__and4b_2.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__and4b_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__and4b_2.sp ('sky130_fd_sc_ls__and4b_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/and4b/sky130_fd_sc_ls__and4b_2.spice ('sky130_fd_sc_ls__and4b_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:55:48 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__and4b_2 sky130_fd_sc_ls__and4b_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__and4b_2
+SOURCE CELL NAME: sky130_fd_sc_ls__and4b_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 14 14
+
+ Instances: 7 7 MN (4 pins)
+ 7 7 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 15 14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 11 11
+
+ Instances: 2 2 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 1 SMN4 (6 pins)
+ ------ ------
+ Total Inst: 9 9
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 6 6 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN4
+ ------- ------- --------- ---------
+ Total Inst: 9 9 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A_N D C B VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/and4b/sky130_fd_sc_ls__and4b_2.pex.spice b/cells/and4b/sky130_fd_sc_ls__and4b_2.pex.spice
index e8c6f20..a31f8ca 100644
--- a/cells/and4b/sky130_fd_sc_ls__and4b_2.pex.spice
+++ b/cells/and4b/sky130_fd_sc_ls__and4b_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__and4b_2.pex.spice
-* Created: Fri Aug 28 13:05:50 2020
+* Created: Wed Sep 2 10:55:51 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/and4b/sky130_fd_sc_ls__and4b_2.pxi.spice b/cells/and4b/sky130_fd_sc_ls__and4b_2.pxi.spice
index 5066e23..34e77f2 100644
--- a/cells/and4b/sky130_fd_sc_ls__and4b_2.pxi.spice
+++ b/cells/and4b/sky130_fd_sc_ls__and4b_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__and4b_2.pxi.spice
-* Created: Fri Aug 28 13:05:50 2020
+* Created: Wed Sep 2 10:55:51 2020
*
x_PM_SKY130_FD_SC_LS__AND4B_2%A_N N_A_N_M1005_g N_A_N_c_73_n N_A_N_M1008_g A_N
+ N_A_N_c_74_n PM_SKY130_FD_SC_LS__AND4B_2%A_N
diff --git a/cells/and4b/sky130_fd_sc_ls__and4b_2.spice b/cells/and4b/sky130_fd_sc_ls__and4b_2.spice
index 54e604c..58c85c4 100644
--- a/cells/and4b/sky130_fd_sc_ls__and4b_2.spice
+++ b/cells/and4b/sky130_fd_sc_ls__and4b_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__and4b_2.spice
-* Created: Fri Aug 28 13:05:50 2020
+* Created: Wed Sep 2 10:55:51 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/and4b/sky130_fd_sc_ls__and4b_4.lvs.report b/cells/and4b/sky130_fd_sc_ls__and4b_4.lvs.report
new file mode 100644
index 0000000..423c5e0
--- /dev/null
+++ b/cells/and4b/sky130_fd_sc_ls__and4b_4.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__and4b_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__and4b_4.sp ('sky130_fd_sc_ls__and4b_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/and4b/sky130_fd_sc_ls__and4b_4.spice ('sky130_fd_sc_ls__and4b_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:55:54 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__and4b_4 sky130_fd_sc_ls__and4b_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__and4b_4
+SOURCE CELL NAME: sky130_fd_sc_ls__and4b_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 14 14
+
+ Instances: 13 13 MN (4 pins)
+ 13 13 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 27 26
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 11 11
+
+ Instances: 2 2 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 1 SMN4 (6 pins)
+ ------ ------
+ Total Inst: 9 9
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 6 6 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN4
+ ------- ------- --------- ---------
+ Total Inst: 9 9 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 24 layout mos transistors were reduced to 10.
+ 14 mos transistors were deleted by parallel reduction.
+ 24 source mos transistors were reduced to 10.
+ 14 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A_N D C B VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/and4b/sky130_fd_sc_ls__and4b_4.pex.spice b/cells/and4b/sky130_fd_sc_ls__and4b_4.pex.spice
index cadb726..c11f421 100644
--- a/cells/and4b/sky130_fd_sc_ls__and4b_4.pex.spice
+++ b/cells/and4b/sky130_fd_sc_ls__and4b_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__and4b_4.pex.spice
-* Created: Fri Aug 28 13:05:58 2020
+* Created: Wed Sep 2 10:55:57 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/and4b/sky130_fd_sc_ls__and4b_4.pxi.spice b/cells/and4b/sky130_fd_sc_ls__and4b_4.pxi.spice
index 939ab79..3422e37 100644
--- a/cells/and4b/sky130_fd_sc_ls__and4b_4.pxi.spice
+++ b/cells/and4b/sky130_fd_sc_ls__and4b_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__and4b_4.pxi.spice
-* Created: Fri Aug 28 13:05:58 2020
+* Created: Wed Sep 2 10:55:57 2020
*
x_PM_SKY130_FD_SC_LS__AND4B_4%A_N N_A_N_c_137_n N_A_N_M1016_g N_A_N_c_138_n
+ N_A_N_M1014_g A_N PM_SKY130_FD_SC_LS__AND4B_4%A_N
diff --git a/cells/and4b/sky130_fd_sc_ls__and4b_4.spice b/cells/and4b/sky130_fd_sc_ls__and4b_4.spice
index 4b485d5..56f505b 100644
--- a/cells/and4b/sky130_fd_sc_ls__and4b_4.spice
+++ b/cells/and4b/sky130_fd_sc_ls__and4b_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__and4b_4.spice
-* Created: Fri Aug 28 13:05:58 2020
+* Created: Wed Sep 2 10:55:57 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/and4bb/sky130_fd_sc_ls__and4bb_1.lvs.report b/cells/and4bb/sky130_fd_sc_ls__and4bb_1.lvs.report
new file mode 100644
index 0000000..fc8d8e9
--- /dev/null
+++ b/cells/and4bb/sky130_fd_sc_ls__and4bb_1.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__and4bb_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__and4bb_1.sp ('sky130_fd_sc_ls__and4bb_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/and4bb/sky130_fd_sc_ls__and4bb_1.spice ('sky130_fd_sc_ls__and4bb_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:56:01 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__and4bb_1 sky130_fd_sc_ls__and4bb_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__and4bb_1
+SOURCE CELL NAME: sky130_fd_sc_ls__and4bb_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 15 15
+
+ Instances: 7 7 MN (4 pins)
+ 7 7 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 15 14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 12 12
+
+ Instances: 3 3 MN (4 pins)
+ 7 7 MP (4 pins)
+ 1 1 SMN4 (6 pins)
+ ------ ------
+ Total Inst: 11 11
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 12 12 0 0
+
+ Instances: 3 3 0 0 MN(NSHORT)
+ 7 7 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN4
+ ------- ------- --------- ---------
+ Total Inst: 11 11 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A_N C D B_N VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/and4bb/sky130_fd_sc_ls__and4bb_1.pex.spice b/cells/and4bb/sky130_fd_sc_ls__and4bb_1.pex.spice
index fe9b123..cff8adb 100644
--- a/cells/and4bb/sky130_fd_sc_ls__and4bb_1.pex.spice
+++ b/cells/and4bb/sky130_fd_sc_ls__and4bb_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__and4bb_1.pex.spice
-* Created: Fri Aug 28 13:06:06 2020
+* Created: Wed Sep 2 10:56:04 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/and4bb/sky130_fd_sc_ls__and4bb_1.pxi.spice b/cells/and4bb/sky130_fd_sc_ls__and4bb_1.pxi.spice
index 4e1285e..49acdec 100644
--- a/cells/and4bb/sky130_fd_sc_ls__and4bb_1.pxi.spice
+++ b/cells/and4bb/sky130_fd_sc_ls__and4bb_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__and4bb_1.pxi.spice
-* Created: Fri Aug 28 13:06:06 2020
+* Created: Wed Sep 2 10:56:04 2020
*
x_PM_SKY130_FD_SC_LS__AND4BB_1%A_N N_A_N_M1012_g N_A_N_c_98_n N_A_N_M1008_g A_N
+ N_A_N_c_99_n PM_SKY130_FD_SC_LS__AND4BB_1%A_N
diff --git a/cells/and4bb/sky130_fd_sc_ls__and4bb_1.spice b/cells/and4bb/sky130_fd_sc_ls__and4bb_1.spice
index 5a5559d..0c9aec2 100644
--- a/cells/and4bb/sky130_fd_sc_ls__and4bb_1.spice
+++ b/cells/and4bb/sky130_fd_sc_ls__and4bb_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__and4bb_1.spice
-* Created: Fri Aug 28 13:06:06 2020
+* Created: Wed Sep 2 10:56:04 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/and4bb/sky130_fd_sc_ls__and4bb_2.lvs.report b/cells/and4bb/sky130_fd_sc_ls__and4bb_2.lvs.report
new file mode 100644
index 0000000..a56a999
--- /dev/null
+++ b/cells/and4bb/sky130_fd_sc_ls__and4bb_2.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__and4bb_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__and4bb_2.sp ('sky130_fd_sc_ls__and4bb_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/and4bb/sky130_fd_sc_ls__and4bb_2.spice ('sky130_fd_sc_ls__and4bb_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:56:07 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__and4bb_2 sky130_fd_sc_ls__and4bb_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__and4bb_2
+SOURCE CELL NAME: sky130_fd_sc_ls__and4bb_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 15 15
+
+ Instances: 8 8 MN (4 pins)
+ 8 8 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 17 16
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 12 12
+
+ Instances: 3 3 MN (4 pins)
+ 7 7 MP (4 pins)
+ 1 1 SMN4 (6 pins)
+ ------ ------
+ Total Inst: 11 11
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 12 12 0 0
+
+ Instances: 3 3 0 0 MN(NSHORT)
+ 7 7 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN4
+ ------- ------- --------- ---------
+ Total Inst: 11 11 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A_N C D B_N VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/and4bb/sky130_fd_sc_ls__and4bb_2.pex.spice b/cells/and4bb/sky130_fd_sc_ls__and4bb_2.pex.spice
index 808e903..2000a25 100644
--- a/cells/and4bb/sky130_fd_sc_ls__and4bb_2.pex.spice
+++ b/cells/and4bb/sky130_fd_sc_ls__and4bb_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__and4bb_2.pex.spice
-* Created: Fri Aug 28 13:06:15 2020
+* Created: Wed Sep 2 10:56:10 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/and4bb/sky130_fd_sc_ls__and4bb_2.pxi.spice b/cells/and4bb/sky130_fd_sc_ls__and4bb_2.pxi.spice
index dc00e94..85d7c09 100644
--- a/cells/and4bb/sky130_fd_sc_ls__and4bb_2.pxi.spice
+++ b/cells/and4bb/sky130_fd_sc_ls__and4bb_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__and4bb_2.pxi.spice
-* Created: Fri Aug 28 13:06:15 2020
+* Created: Wed Sep 2 10:56:10 2020
*
x_PM_SKY130_FD_SC_LS__AND4BB_2%A_N N_A_N_M1015_g N_A_N_c_97_n N_A_N_M1000_g A_N
+ N_A_N_c_98_n PM_SKY130_FD_SC_LS__AND4BB_2%A_N
diff --git a/cells/and4bb/sky130_fd_sc_ls__and4bb_2.spice b/cells/and4bb/sky130_fd_sc_ls__and4bb_2.spice
index bfd26f1..0497281 100644
--- a/cells/and4bb/sky130_fd_sc_ls__and4bb_2.spice
+++ b/cells/and4bb/sky130_fd_sc_ls__and4bb_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__and4bb_2.spice
-* Created: Fri Aug 28 13:06:15 2020
+* Created: Wed Sep 2 10:56:10 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/and4bb/sky130_fd_sc_ls__and4bb_4.lvs.report b/cells/and4bb/sky130_fd_sc_ls__and4bb_4.lvs.report
new file mode 100644
index 0000000..1a39f88
--- /dev/null
+++ b/cells/and4bb/sky130_fd_sc_ls__and4bb_4.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__and4bb_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__and4bb_4.sp ('sky130_fd_sc_ls__and4bb_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/and4bb/sky130_fd_sc_ls__and4bb_4.spice ('sky130_fd_sc_ls__and4bb_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:56:14 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__and4bb_4 sky130_fd_sc_ls__and4bb_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__and4bb_4
+SOURCE CELL NAME: sky130_fd_sc_ls__and4bb_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 15 15
+
+ Instances: 14 14 MN (4 pins)
+ 14 14 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 29 28
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 12 12
+
+ Instances: 3 3 MN (4 pins)
+ 7 7 MP (4 pins)
+ 1 1 SMN4 (6 pins)
+ ------ ------
+ Total Inst: 11 11
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 12 12 0 0
+
+ Instances: 3 3 0 0 MN(NSHORT)
+ 7 7 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN4
+ ------- ------- --------- ---------
+ Total Inst: 11 11 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 24 layout mos transistors were reduced to 10.
+ 14 mos transistors were deleted by parallel reduction.
+ 24 source mos transistors were reduced to 10.
+ 14 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B_N A_N C D VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/and4bb/sky130_fd_sc_ls__and4bb_4.pex.spice b/cells/and4bb/sky130_fd_sc_ls__and4bb_4.pex.spice
index 6c62bd3..9fddfe5 100644
--- a/cells/and4bb/sky130_fd_sc_ls__and4bb_4.pex.spice
+++ b/cells/and4bb/sky130_fd_sc_ls__and4bb_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__and4bb_4.pex.spice
-* Created: Fri Aug 28 13:06:23 2020
+* Created: Wed Sep 2 10:56:17 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/and4bb/sky130_fd_sc_ls__and4bb_4.pxi.spice b/cells/and4bb/sky130_fd_sc_ls__and4bb_4.pxi.spice
index 6335de4..b9b836b 100644
--- a/cells/and4bb/sky130_fd_sc_ls__and4bb_4.pxi.spice
+++ b/cells/and4bb/sky130_fd_sc_ls__and4bb_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__and4bb_4.pxi.spice
-* Created: Fri Aug 28 13:06:23 2020
+* Created: Wed Sep 2 10:56:17 2020
*
x_PM_SKY130_FD_SC_LS__AND4BB_4%B_N N_B_N_M1019_g N_B_N_c_153_n N_B_N_M1017_g B_N
+ B_N PM_SKY130_FD_SC_LS__AND4BB_4%B_N
diff --git a/cells/and4bb/sky130_fd_sc_ls__and4bb_4.spice b/cells/and4bb/sky130_fd_sc_ls__and4bb_4.spice
index 44108fa..08fc14e 100644
--- a/cells/and4bb/sky130_fd_sc_ls__and4bb_4.spice
+++ b/cells/and4bb/sky130_fd_sc_ls__and4bb_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__and4bb_4.spice
-* Created: Fri Aug 28 13:06:23 2020
+* Created: Wed Sep 2 10:56:17 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/buf/sky130_fd_sc_ls__buf_1.lvs.report b/cells/buf/sky130_fd_sc_ls__buf_1.lvs.report
new file mode 100644
index 0000000..2d1c826
--- /dev/null
+++ b/cells/buf/sky130_fd_sc_ls__buf_1.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__buf_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__buf_1.sp ('sky130_fd_sc_ls__buf_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/buf/sky130_fd_sc_ls__buf_1.spice ('sky130_fd_sc_ls__buf_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:56:27 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__buf_1 sky130_fd_sc_ls__buf_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__buf_1
+SOURCE CELL NAME: sky130_fd_sc_ls__buf_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 7 7
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 5 4
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 7 7
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 7 7 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/buf/sky130_fd_sc_ls__buf_1.pex.spice b/cells/buf/sky130_fd_sc_ls__buf_1.pex.spice
index dbdf77e..aee446f 100644
--- a/cells/buf/sky130_fd_sc_ls__buf_1.pex.spice
+++ b/cells/buf/sky130_fd_sc_ls__buf_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__buf_1.pex.spice
-* Created: Fri Aug 28 13:06:56 2020
+* Created: Wed Sep 2 10:56:30 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/buf/sky130_fd_sc_ls__buf_1.pxi.spice b/cells/buf/sky130_fd_sc_ls__buf_1.pxi.spice
index d2be838..c674f8f 100644
--- a/cells/buf/sky130_fd_sc_ls__buf_1.pxi.spice
+++ b/cells/buf/sky130_fd_sc_ls__buf_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__buf_1.pxi.spice
-* Created: Fri Aug 28 13:06:56 2020
+* Created: Wed Sep 2 10:56:30 2020
*
x_PM_SKY130_FD_SC_LS__BUF_1%A N_A_M1001_g N_A_c_37_n N_A_M1000_g N_A_c_38_n A A
+ PM_SKY130_FD_SC_LS__BUF_1%A
diff --git a/cells/buf/sky130_fd_sc_ls__buf_1.spice b/cells/buf/sky130_fd_sc_ls__buf_1.spice
index 9fd3947..269b4c6 100644
--- a/cells/buf/sky130_fd_sc_ls__buf_1.spice
+++ b/cells/buf/sky130_fd_sc_ls__buf_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__buf_1.spice
-* Created: Fri Aug 28 13:06:56 2020
+* Created: Wed Sep 2 10:56:30 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/buf/sky130_fd_sc_ls__buf_16.lvs.report b/cells/buf/sky130_fd_sc_ls__buf_16.lvs.report
new file mode 100644
index 0000000..77b01b3
--- /dev/null
+++ b/cells/buf/sky130_fd_sc_ls__buf_16.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__buf_16.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__buf_16.sp ('sky130_fd_sc_ls__buf_16')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/buf/sky130_fd_sc_ls__buf_16.spice ('sky130_fd_sc_ls__buf_16')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:56:21 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__buf_16 sky130_fd_sc_ls__buf_16
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__buf_16
+SOURCE CELL NAME: sky130_fd_sc_ls__buf_16
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 7 7
+
+ Instances: 22 22 MN (4 pins)
+ 22 22 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 45 44
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 7 7
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 7 7 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 44 layout mos transistors were reduced to 4.
+ 40 mos transistors were deleted by parallel reduction.
+ 44 source mos transistors were reduced to 4.
+ 40 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/buf/sky130_fd_sc_ls__buf_16.pex.spice b/cells/buf/sky130_fd_sc_ls__buf_16.pex.spice
index 606fcaa..4a254e3 100644
--- a/cells/buf/sky130_fd_sc_ls__buf_16.pex.spice
+++ b/cells/buf/sky130_fd_sc_ls__buf_16.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__buf_16.pex.spice
-* Created: Fri Aug 28 13:06:37 2020
+* Created: Wed Sep 2 10:56:24 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/buf/sky130_fd_sc_ls__buf_16.pxi.spice b/cells/buf/sky130_fd_sc_ls__buf_16.pxi.spice
index d2a8da4..bd8e270 100644
--- a/cells/buf/sky130_fd_sc_ls__buf_16.pxi.spice
+++ b/cells/buf/sky130_fd_sc_ls__buf_16.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__buf_16.pxi.spice
-* Created: Fri Aug 28 13:06:37 2020
+* Created: Wed Sep 2 10:56:24 2020
*
x_PM_SKY130_FD_SC_LS__BUF_16%A_83_260# N_A_83_260#_M1005_s N_A_83_260#_M1016_s
+ N_A_83_260#_M1040_s N_A_83_260#_M1002_s N_A_83_260#_M1015_s
diff --git a/cells/buf/sky130_fd_sc_ls__buf_16.spice b/cells/buf/sky130_fd_sc_ls__buf_16.spice
index f572899..76571ca 100644
--- a/cells/buf/sky130_fd_sc_ls__buf_16.spice
+++ b/cells/buf/sky130_fd_sc_ls__buf_16.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__buf_16.spice
-* Created: Fri Aug 28 13:06:37 2020
+* Created: Wed Sep 2 10:56:24 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/buf/sky130_fd_sc_ls__buf_2.lvs.report b/cells/buf/sky130_fd_sc_ls__buf_2.lvs.report
new file mode 100644
index 0000000..f56d02f
--- /dev/null
+++ b/cells/buf/sky130_fd_sc_ls__buf_2.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__buf_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__buf_2.sp ('sky130_fd_sc_ls__buf_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/buf/sky130_fd_sc_ls__buf_2.spice ('sky130_fd_sc_ls__buf_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:56:34 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__buf_2 sky130_fd_sc_ls__buf_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__buf_2
+SOURCE CELL NAME: sky130_fd_sc_ls__buf_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 7 7
+
+ Instances: 3 3 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 7 6
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 7 7
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 7 7 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/buf/sky130_fd_sc_ls__buf_2.pex.spice b/cells/buf/sky130_fd_sc_ls__buf_2.pex.spice
index b5c1dcd..c02a90a 100644
--- a/cells/buf/sky130_fd_sc_ls__buf_2.pex.spice
+++ b/cells/buf/sky130_fd_sc_ls__buf_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__buf_2.pex.spice
-* Created: Fri Aug 28 13:07:05 2020
+* Created: Wed Sep 2 10:56:37 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/buf/sky130_fd_sc_ls__buf_2.pxi.spice b/cells/buf/sky130_fd_sc_ls__buf_2.pxi.spice
index e00f088..a05ed28 100644
--- a/cells/buf/sky130_fd_sc_ls__buf_2.pxi.spice
+++ b/cells/buf/sky130_fd_sc_ls__buf_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__buf_2.pxi.spice
-* Created: Fri Aug 28 13:07:05 2020
+* Created: Wed Sep 2 10:56:37 2020
*
x_PM_SKY130_FD_SC_LS__BUF_2%A_21_260# N_A_21_260#_M1003_d N_A_21_260#_M1004_d
+ N_A_21_260#_c_53_n N_A_21_260#_M1000_g N_A_21_260#_M1001_g N_A_21_260#_M1005_g
diff --git a/cells/buf/sky130_fd_sc_ls__buf_2.spice b/cells/buf/sky130_fd_sc_ls__buf_2.spice
index 5c20c93..1834f71 100644
--- a/cells/buf/sky130_fd_sc_ls__buf_2.spice
+++ b/cells/buf/sky130_fd_sc_ls__buf_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__buf_2.spice
-* Created: Fri Aug 28 13:07:05 2020
+* Created: Wed Sep 2 10:56:37 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/buf/sky130_fd_sc_ls__buf_4.lvs.report b/cells/buf/sky130_fd_sc_ls__buf_4.lvs.report
new file mode 100644
index 0000000..1cab6dd
--- /dev/null
+++ b/cells/buf/sky130_fd_sc_ls__buf_4.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__buf_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__buf_4.sp ('sky130_fd_sc_ls__buf_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/buf/sky130_fd_sc_ls__buf_4.spice ('sky130_fd_sc_ls__buf_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:56:40 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__buf_4 sky130_fd_sc_ls__buf_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__buf_4
+SOURCE CELL NAME: sky130_fd_sc_ls__buf_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 7 7
+
+ Instances: 5 5 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 12 11
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 7 7
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 7 7 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 10 layout mos transistors were reduced to 3.
+ 7 mos transistors were deleted by parallel reduction.
+ 10 source mos transistors were reduced to 3.
+ 7 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/buf/sky130_fd_sc_ls__buf_4.pex.spice b/cells/buf/sky130_fd_sc_ls__buf_4.pex.spice
index 9be1ec1..3bf90d9 100644
--- a/cells/buf/sky130_fd_sc_ls__buf_4.pex.spice
+++ b/cells/buf/sky130_fd_sc_ls__buf_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__buf_4.pex.spice
-* Created: Fri Aug 28 13:07:13 2020
+* Created: Wed Sep 2 10:56:43 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/buf/sky130_fd_sc_ls__buf_4.pxi.spice b/cells/buf/sky130_fd_sc_ls__buf_4.pxi.spice
index 9e41541..472e478 100644
--- a/cells/buf/sky130_fd_sc_ls__buf_4.pxi.spice
+++ b/cells/buf/sky130_fd_sc_ls__buf_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__buf_4.pxi.spice
-* Created: Fri Aug 28 13:07:13 2020
+* Created: Wed Sep 2 10:56:43 2020
*
x_PM_SKY130_FD_SC_LS__BUF_4%A_86_260# N_A_86_260#_M1007_d N_A_86_260#_M1001_d
+ N_A_86_260#_c_63_n N_A_86_260#_c_78_n N_A_86_260#_M1002_g N_A_86_260#_M1000_g
diff --git a/cells/buf/sky130_fd_sc_ls__buf_4.spice b/cells/buf/sky130_fd_sc_ls__buf_4.spice
index aed955c..b73c39e 100644
--- a/cells/buf/sky130_fd_sc_ls__buf_4.spice
+++ b/cells/buf/sky130_fd_sc_ls__buf_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__buf_4.spice
-* Created: Fri Aug 28 13:07:13 2020
+* Created: Wed Sep 2 10:56:43 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/buf/sky130_fd_sc_ls__buf_8.lvs.report b/cells/buf/sky130_fd_sc_ls__buf_8.lvs.report
new file mode 100644
index 0000000..1911bd4
--- /dev/null
+++ b/cells/buf/sky130_fd_sc_ls__buf_8.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__buf_8.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__buf_8.sp ('sky130_fd_sc_ls__buf_8')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/buf/sky130_fd_sc_ls__buf_8.spice ('sky130_fd_sc_ls__buf_8')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:56:47 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__buf_8 sky130_fd_sc_ls__buf_8
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__buf_8
+SOURCE CELL NAME: sky130_fd_sc_ls__buf_8
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 7 7
+
+ Instances: 11 11 MN (4 pins)
+ 11 11 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 23 22
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 7 7
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 7 7 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 22 layout mos transistors were reduced to 4.
+ 18 mos transistors were deleted by parallel reduction.
+ 22 source mos transistors were reduced to 4.
+ 18 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/buf/sky130_fd_sc_ls__buf_8.pex.spice b/cells/buf/sky130_fd_sc_ls__buf_8.pex.spice
index ca7c801..c80d439 100644
--- a/cells/buf/sky130_fd_sc_ls__buf_8.pex.spice
+++ b/cells/buf/sky130_fd_sc_ls__buf_8.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__buf_8.pex.spice
-* Created: Fri Aug 28 13:07:22 2020
+* Created: Wed Sep 2 10:56:50 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/buf/sky130_fd_sc_ls__buf_8.pxi.spice b/cells/buf/sky130_fd_sc_ls__buf_8.pxi.spice
index baf4474..a64b520 100644
--- a/cells/buf/sky130_fd_sc_ls__buf_8.pxi.spice
+++ b/cells/buf/sky130_fd_sc_ls__buf_8.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__buf_8.pxi.spice
-* Created: Fri Aug 28 13:07:22 2020
+* Created: Wed Sep 2 10:56:50 2020
*
x_PM_SKY130_FD_SC_LS__BUF_8%A N_A_M1001_g N_A_c_108_n N_A_M1010_g N_A_c_109_n
+ N_A_M1011_g N_A_M1008_g N_A_M1017_g N_A_c_110_n N_A_M1015_g A A A N_A_c_106_n
diff --git a/cells/buf/sky130_fd_sc_ls__buf_8.spice b/cells/buf/sky130_fd_sc_ls__buf_8.spice
index b7ec99f..d110524 100644
--- a/cells/buf/sky130_fd_sc_ls__buf_8.spice
+++ b/cells/buf/sky130_fd_sc_ls__buf_8.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__buf_8.spice
-* Created: Fri Aug 28 13:07:22 2020
+* Created: Wed Sep 2 10:56:50 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/bufbuf/sky130_fd_sc_ls__bufbuf_16.lvs.report b/cells/bufbuf/sky130_fd_sc_ls__bufbuf_16.lvs.report
new file mode 100644
index 0000000..b049416
--- /dev/null
+++ b/cells/bufbuf/sky130_fd_sc_ls__bufbuf_16.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__bufbuf_16.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__bufbuf_16.sp ('sky130_fd_sc_ls__bufbuf_16')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/bufbuf/sky130_fd_sc_ls__bufbuf_16.spice ('sky130_fd_sc_ls__bufbuf_16')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:56:54 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__bufbuf_16 sky130_fd_sc_ls__bufbuf_16
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__bufbuf_16
+SOURCE CELL NAME: sky130_fd_sc_ls__bufbuf_16
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 9 9
+
+ Instances: 26 26 MN (4 pins)
+ 26 26 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 53 52
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 9 9
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ ------ ------
+ Total Inst: 8 8
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 4 4 0 0 MN(NSHORT)
+ 4 4 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 8 8 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 50 layout mos transistors were reduced to 6.
+ 44 mos transistors were deleted by parallel reduction.
+ 50 source mos transistors were reduced to 6.
+ 44 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/bufbuf/sky130_fd_sc_ls__bufbuf_16.pex.spice b/cells/bufbuf/sky130_fd_sc_ls__bufbuf_16.pex.spice
index cfb8cd9..f2370c1 100644
--- a/cells/bufbuf/sky130_fd_sc_ls__bufbuf_16.pex.spice
+++ b/cells/bufbuf/sky130_fd_sc_ls__bufbuf_16.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__bufbuf_16.pex.spice
-* Created: Fri Aug 28 13:07:31 2020
+* Created: Wed Sep 2 10:56:57 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/bufbuf/sky130_fd_sc_ls__bufbuf_16.pxi.spice b/cells/bufbuf/sky130_fd_sc_ls__bufbuf_16.pxi.spice
index 0278ad3..3a96b15 100644
--- a/cells/bufbuf/sky130_fd_sc_ls__bufbuf_16.pxi.spice
+++ b/cells/bufbuf/sky130_fd_sc_ls__bufbuf_16.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__bufbuf_16.pxi.spice
-* Created: Fri Aug 28 13:07:31 2020
+* Created: Wed Sep 2 10:56:57 2020
*
x_PM_SKY130_FD_SC_LS__BUFBUF_16%A N_A_c_235_n N_A_M1030_g N_A_M1049_g A
+ N_A_c_237_n PM_SKY130_FD_SC_LS__BUFBUF_16%A
diff --git a/cells/bufbuf/sky130_fd_sc_ls__bufbuf_16.spice b/cells/bufbuf/sky130_fd_sc_ls__bufbuf_16.spice
index decea96..c3bc6ca 100644
--- a/cells/bufbuf/sky130_fd_sc_ls__bufbuf_16.spice
+++ b/cells/bufbuf/sky130_fd_sc_ls__bufbuf_16.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__bufbuf_16.spice
-* Created: Fri Aug 28 13:07:31 2020
+* Created: Wed Sep 2 10:56:57 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/bufbuf/sky130_fd_sc_ls__bufbuf_8.lvs.report b/cells/bufbuf/sky130_fd_sc_ls__bufbuf_8.lvs.report
new file mode 100644
index 0000000..a050c11
--- /dev/null
+++ b/cells/bufbuf/sky130_fd_sc_ls__bufbuf_8.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__bufbuf_8.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__bufbuf_8.sp ('sky130_fd_sc_ls__bufbuf_8')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/bufbuf/sky130_fd_sc_ls__bufbuf_8.spice ('sky130_fd_sc_ls__bufbuf_8')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:57:01 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__bufbuf_8 sky130_fd_sc_ls__bufbuf_8
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__bufbuf_8
+SOURCE CELL NAME: sky130_fd_sc_ls__bufbuf_8
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 9 9
+
+ Instances: 13 13 MN (4 pins)
+ 13 13 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 27 26
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 9 9
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ ------ ------
+ Total Inst: 8 8
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 4 4 0 0 MN(NSHORT)
+ 4 4 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 8 8 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 22 layout mos transistors were reduced to 4.
+ 18 mos transistors were deleted by parallel reduction.
+ 22 source mos transistors were reduced to 4.
+ 18 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/bufbuf/sky130_fd_sc_ls__bufbuf_8.pex.spice b/cells/bufbuf/sky130_fd_sc_ls__bufbuf_8.pex.spice
index c7e9e6e..2b1a13f 100644
--- a/cells/bufbuf/sky130_fd_sc_ls__bufbuf_8.pex.spice
+++ b/cells/bufbuf/sky130_fd_sc_ls__bufbuf_8.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__bufbuf_8.pex.spice
-* Created: Fri Aug 28 13:07:45 2020
+* Created: Wed Sep 2 10:57:04 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/bufbuf/sky130_fd_sc_ls__bufbuf_8.pxi.spice b/cells/bufbuf/sky130_fd_sc_ls__bufbuf_8.pxi.spice
index 8974d5c..e360b1a 100644
--- a/cells/bufbuf/sky130_fd_sc_ls__bufbuf_8.pxi.spice
+++ b/cells/bufbuf/sky130_fd_sc_ls__bufbuf_8.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__bufbuf_8.pxi.spice
-* Created: Fri Aug 28 13:07:45 2020
+* Created: Wed Sep 2 10:57:04 2020
*
x_PM_SKY130_FD_SC_LS__BUFBUF_8%A N_A_M1015_g N_A_c_126_n N_A_M1018_g A
+ N_A_c_127_n PM_SKY130_FD_SC_LS__BUFBUF_8%A
diff --git a/cells/bufbuf/sky130_fd_sc_ls__bufbuf_8.spice b/cells/bufbuf/sky130_fd_sc_ls__bufbuf_8.spice
index 4091204..794b274 100644
--- a/cells/bufbuf/sky130_fd_sc_ls__bufbuf_8.spice
+++ b/cells/bufbuf/sky130_fd_sc_ls__bufbuf_8.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__bufbuf_8.spice
-* Created: Fri Aug 28 13:07:45 2020
+* Created: Wed Sep 2 10:57:04 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/bufinv/sky130_fd_sc_ls__bufinv_16.lvs.report b/cells/bufinv/sky130_fd_sc_ls__bufinv_16.lvs.report
new file mode 100644
index 0000000..9ebc15c
--- /dev/null
+++ b/cells/bufinv/sky130_fd_sc_ls__bufinv_16.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__bufinv_16.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__bufinv_16.sp ('sky130_fd_sc_ls__bufinv_16')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/bufinv/sky130_fd_sc_ls__bufinv_16.spice ('sky130_fd_sc_ls__bufinv_16')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:57:08 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__bufinv_16 sky130_fd_sc_ls__bufinv_16
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__bufinv_16
+SOURCE CELL NAME: sky130_fd_sc_ls__bufinv_16
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 8 8
+
+ Instances: 25 25 MN (4 pins)
+ 25 25 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 51 50
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 8 8
+
+ Instances: 3 3 MN (4 pins)
+ 3 3 MP (4 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 3 3 0 0 MN(NSHORT)
+ 3 3 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 50 layout mos transistors were reduced to 6.
+ 44 mos transistors were deleted by parallel reduction.
+ 50 source mos transistors were reduced to 6.
+ 44 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/bufinv/sky130_fd_sc_ls__bufinv_16.pex.spice b/cells/bufinv/sky130_fd_sc_ls__bufinv_16.pex.spice
index 4080bd7..20aaa89 100644
--- a/cells/bufinv/sky130_fd_sc_ls__bufinv_16.pex.spice
+++ b/cells/bufinv/sky130_fd_sc_ls__bufinv_16.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__bufinv_16.pex.spice
-* Created: Fri Aug 28 13:08:04 2020
+* Created: Wed Sep 2 10:57:11 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/bufinv/sky130_fd_sc_ls__bufinv_16.pxi.spice b/cells/bufinv/sky130_fd_sc_ls__bufinv_16.pxi.spice
index ee1650c..2184f8a 100644
--- a/cells/bufinv/sky130_fd_sc_ls__bufinv_16.pxi.spice
+++ b/cells/bufinv/sky130_fd_sc_ls__bufinv_16.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__bufinv_16.pxi.spice
-* Created: Fri Aug 28 13:08:04 2020
+* Created: Wed Sep 2 10:57:11 2020
*
x_PM_SKY130_FD_SC_LS__BUFINV_16%A N_A_M1025_g N_A_c_218_n N_A_M1021_g
+ N_A_c_219_n N_A_M1022_g N_A_M1041_g N_A_c_220_n N_A_M1034_g N_A_M1049_g A A A
diff --git a/cells/bufinv/sky130_fd_sc_ls__bufinv_16.spice b/cells/bufinv/sky130_fd_sc_ls__bufinv_16.spice
index 3a696f1..f59b4b7 100644
--- a/cells/bufinv/sky130_fd_sc_ls__bufinv_16.spice
+++ b/cells/bufinv/sky130_fd_sc_ls__bufinv_16.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__bufinv_16.spice
-* Created: Fri Aug 28 13:08:04 2020
+* Created: Wed Sep 2 10:57:11 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/bufinv/sky130_fd_sc_ls__bufinv_8.lvs.report b/cells/bufinv/sky130_fd_sc_ls__bufinv_8.lvs.report
new file mode 100644
index 0000000..0965201
--- /dev/null
+++ b/cells/bufinv/sky130_fd_sc_ls__bufinv_8.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__bufinv_8.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__bufinv_8.sp ('sky130_fd_sc_ls__bufinv_8')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/bufinv/sky130_fd_sc_ls__bufinv_8.spice ('sky130_fd_sc_ls__bufinv_8')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:57:14 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__bufinv_8 sky130_fd_sc_ls__bufinv_8
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__bufinv_8
+SOURCE CELL NAME: sky130_fd_sc_ls__bufinv_8
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 8 8
+
+ Instances: 12 12 MN (4 pins)
+ 12 12 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 25 24
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 8 8
+
+ Instances: 3 3 MN (4 pins)
+ 3 3 MP (4 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 3 3 0 0 MN(NSHORT)
+ 3 3 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 22 layout mos transistors were reduced to 4.
+ 18 mos transistors were deleted by parallel reduction.
+ 22 source mos transistors were reduced to 4.
+ 18 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/bufinv/sky130_fd_sc_ls__bufinv_8.pex.spice b/cells/bufinv/sky130_fd_sc_ls__bufinv_8.pex.spice
index 3a5e68d..2865e12 100644
--- a/cells/bufinv/sky130_fd_sc_ls__bufinv_8.pex.spice
+++ b/cells/bufinv/sky130_fd_sc_ls__bufinv_8.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__bufinv_8.pex.spice
-* Created: Fri Aug 28 13:08:15 2020
+* Created: Wed Sep 2 10:57:17 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/bufinv/sky130_fd_sc_ls__bufinv_8.pxi.spice b/cells/bufinv/sky130_fd_sc_ls__bufinv_8.pxi.spice
index 48574a9..f635858 100644
--- a/cells/bufinv/sky130_fd_sc_ls__bufinv_8.pxi.spice
+++ b/cells/bufinv/sky130_fd_sc_ls__bufinv_8.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__bufinv_8.pxi.spice
-* Created: Fri Aug 28 13:08:15 2020
+* Created: Wed Sep 2 10:57:17 2020
*
x_PM_SKY130_FD_SC_LS__BUFINV_8%A N_A_c_106_n N_A_M1013_g N_A_M1021_g A
+ N_A_c_108_n PM_SKY130_FD_SC_LS__BUFINV_8%A
diff --git a/cells/bufinv/sky130_fd_sc_ls__bufinv_8.spice b/cells/bufinv/sky130_fd_sc_ls__bufinv_8.spice
index 9d0233e..27e43b4 100644
--- a/cells/bufinv/sky130_fd_sc_ls__bufinv_8.spice
+++ b/cells/bufinv/sky130_fd_sc_ls__bufinv_8.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__bufinv_8.spice
-* Created: Fri Aug 28 13:08:15 2020
+* Created: Wed Sep 2 10:57:17 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/clkbuf/sky130_fd_sc_ls__clkbuf_1.lvs.report b/cells/clkbuf/sky130_fd_sc_ls__clkbuf_1.lvs.report
new file mode 100644
index 0000000..1627e36
--- /dev/null
+++ b/cells/clkbuf/sky130_fd_sc_ls__clkbuf_1.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__clkbuf_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__clkbuf_1.sp ('sky130_fd_sc_ls__clkbuf_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/clkbuf/sky130_fd_sc_ls__clkbuf_1.spice ('sky130_fd_sc_ls__clkbuf_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:57:28 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__clkbuf_1 sky130_fd_sc_ls__clkbuf_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__clkbuf_1
+SOURCE CELL NAME: sky130_fd_sc_ls__clkbuf_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 7 7
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 5 4
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 7 7
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 7 7 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/clkbuf/sky130_fd_sc_ls__clkbuf_1.pex.spice b/cells/clkbuf/sky130_fd_sc_ls__clkbuf_1.pex.spice
index e1c4cc0..586f9d9 100644
--- a/cells/clkbuf/sky130_fd_sc_ls__clkbuf_1.pex.spice
+++ b/cells/clkbuf/sky130_fd_sc_ls__clkbuf_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__clkbuf_1.pex.spice
-* Created: Fri Aug 28 13:08:31 2020
+* Created: Wed Sep 2 10:57:30 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/clkbuf/sky130_fd_sc_ls__clkbuf_1.pxi.spice b/cells/clkbuf/sky130_fd_sc_ls__clkbuf_1.pxi.spice
index af03689..cf90289 100644
--- a/cells/clkbuf/sky130_fd_sc_ls__clkbuf_1.pxi.spice
+++ b/cells/clkbuf/sky130_fd_sc_ls__clkbuf_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__clkbuf_1.pxi.spice
-* Created: Fri Aug 28 13:08:31 2020
+* Created: Wed Sep 2 10:57:30 2020
*
x_PM_SKY130_FD_SC_LS__CLKBUF_1%A N_A_M1003_g N_A_c_40_n N_A_M1000_g A A
+ N_A_c_39_n PM_SKY130_FD_SC_LS__CLKBUF_1%A
diff --git a/cells/clkbuf/sky130_fd_sc_ls__clkbuf_1.spice b/cells/clkbuf/sky130_fd_sc_ls__clkbuf_1.spice
index 78ef9e1..7f50f73 100644
--- a/cells/clkbuf/sky130_fd_sc_ls__clkbuf_1.spice
+++ b/cells/clkbuf/sky130_fd_sc_ls__clkbuf_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__clkbuf_1.spice
-* Created: Fri Aug 28 13:08:31 2020
+* Created: Wed Sep 2 10:57:30 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/clkbuf/sky130_fd_sc_ls__clkbuf_16.lvs.report b/cells/clkbuf/sky130_fd_sc_ls__clkbuf_16.lvs.report
new file mode 100644
index 0000000..7c30ce0
--- /dev/null
+++ b/cells/clkbuf/sky130_fd_sc_ls__clkbuf_16.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__clkbuf_16.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__clkbuf_16.sp ('sky130_fd_sc_ls__clkbuf_16')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/clkbuf/sky130_fd_sc_ls__clkbuf_16.spice ('sky130_fd_sc_ls__clkbuf_16')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:57:21 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__clkbuf_16 sky130_fd_sc_ls__clkbuf_16
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__clkbuf_16
+SOURCE CELL NAME: sky130_fd_sc_ls__clkbuf_16
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 7 7
+
+ Instances: 20 20 MN (4 pins)
+ 20 20 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 41 40
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 7 7
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 7 7 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 40 layout mos transistors were reduced to 4.
+ 36 mos transistors were deleted by parallel reduction.
+ 40 source mos transistors were reduced to 4.
+ 36 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/clkbuf/sky130_fd_sc_ls__clkbuf_16.pex.spice b/cells/clkbuf/sky130_fd_sc_ls__clkbuf_16.pex.spice
index 85eac46..4c7355e 100644
--- a/cells/clkbuf/sky130_fd_sc_ls__clkbuf_16.pex.spice
+++ b/cells/clkbuf/sky130_fd_sc_ls__clkbuf_16.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__clkbuf_16.pex.spice
-* Created: Fri Aug 28 13:08:23 2020
+* Created: Wed Sep 2 10:57:24 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/clkbuf/sky130_fd_sc_ls__clkbuf_16.pxi.spice b/cells/clkbuf/sky130_fd_sc_ls__clkbuf_16.pxi.spice
index 7d3c78d..cbe4013 100644
--- a/cells/clkbuf/sky130_fd_sc_ls__clkbuf_16.pxi.spice
+++ b/cells/clkbuf/sky130_fd_sc_ls__clkbuf_16.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__clkbuf_16.pxi.spice
-* Created: Fri Aug 28 13:08:23 2020
+* Created: Wed Sep 2 10:57:24 2020
*
x_PM_SKY130_FD_SC_LS__CLKBUF_16%A N_A_M1022_g N_A_c_202_n N_A_M1020_g
+ N_A_M1029_g N_A_c_203_n N_A_M1021_g N_A_M1030_g N_A_c_204_n N_A_M1025_g
diff --git a/cells/clkbuf/sky130_fd_sc_ls__clkbuf_16.spice b/cells/clkbuf/sky130_fd_sc_ls__clkbuf_16.spice
index 696a804..142a683 100644
--- a/cells/clkbuf/sky130_fd_sc_ls__clkbuf_16.spice
+++ b/cells/clkbuf/sky130_fd_sc_ls__clkbuf_16.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__clkbuf_16.spice
-* Created: Fri Aug 28 13:08:23 2020
+* Created: Wed Sep 2 10:57:24 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/clkbuf/sky130_fd_sc_ls__clkbuf_2.lvs.report b/cells/clkbuf/sky130_fd_sc_ls__clkbuf_2.lvs.report
new file mode 100644
index 0000000..4a88ad8
--- /dev/null
+++ b/cells/clkbuf/sky130_fd_sc_ls__clkbuf_2.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__clkbuf_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__clkbuf_2.sp ('sky130_fd_sc_ls__clkbuf_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/clkbuf/sky130_fd_sc_ls__clkbuf_2.spice ('sky130_fd_sc_ls__clkbuf_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:57:34 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__clkbuf_2 sky130_fd_sc_ls__clkbuf_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__clkbuf_2
+SOURCE CELL NAME: sky130_fd_sc_ls__clkbuf_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 7 7
+
+ Instances: 3 3 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 7 6
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 7 7
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 7 7 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/clkbuf/sky130_fd_sc_ls__clkbuf_2.pex.spice b/cells/clkbuf/sky130_fd_sc_ls__clkbuf_2.pex.spice
index 5bf377d..e9497b5 100644
--- a/cells/clkbuf/sky130_fd_sc_ls__clkbuf_2.pex.spice
+++ b/cells/clkbuf/sky130_fd_sc_ls__clkbuf_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__clkbuf_2.pex.spice
-* Created: Fri Aug 28 13:08:46 2020
+* Created: Wed Sep 2 10:57:37 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/clkbuf/sky130_fd_sc_ls__clkbuf_2.pxi.spice b/cells/clkbuf/sky130_fd_sc_ls__clkbuf_2.pxi.spice
index f0accca..1c6f4e6 100644
--- a/cells/clkbuf/sky130_fd_sc_ls__clkbuf_2.pxi.spice
+++ b/cells/clkbuf/sky130_fd_sc_ls__clkbuf_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__clkbuf_2.pxi.spice
-* Created: Fri Aug 28 13:08:46 2020
+* Created: Wed Sep 2 10:57:37 2020
*
x_PM_SKY130_FD_SC_LS__CLKBUF_2%A_43_192# N_A_43_192#_M1001_d N_A_43_192#_M1000_d
+ N_A_43_192#_M1004_g N_A_43_192#_c_50_n N_A_43_192#_M1002_g N_A_43_192#_M1005_g
diff --git a/cells/clkbuf/sky130_fd_sc_ls__clkbuf_2.spice b/cells/clkbuf/sky130_fd_sc_ls__clkbuf_2.spice
index 6a818f7..ff9b5e7 100644
--- a/cells/clkbuf/sky130_fd_sc_ls__clkbuf_2.spice
+++ b/cells/clkbuf/sky130_fd_sc_ls__clkbuf_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__clkbuf_2.spice
-* Created: Fri Aug 28 13:08:46 2020
+* Created: Wed Sep 2 10:57:37 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/clkbuf/sky130_fd_sc_ls__clkbuf_4.lvs.report b/cells/clkbuf/sky130_fd_sc_ls__clkbuf_4.lvs.report
new file mode 100644
index 0000000..3f2b02e
--- /dev/null
+++ b/cells/clkbuf/sky130_fd_sc_ls__clkbuf_4.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__clkbuf_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__clkbuf_4.sp ('sky130_fd_sc_ls__clkbuf_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/clkbuf/sky130_fd_sc_ls__clkbuf_4.spice ('sky130_fd_sc_ls__clkbuf_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:57:40 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__clkbuf_4 sky130_fd_sc_ls__clkbuf_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__clkbuf_4
+SOURCE CELL NAME: sky130_fd_sc_ls__clkbuf_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 7 7
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 7 7
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 7 7 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 8 layout mos transistors were reduced to 2.
+ 6 mos transistors were deleted by parallel reduction.
+ 8 source mos transistors were reduced to 2.
+ 6 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/clkbuf/sky130_fd_sc_ls__clkbuf_4.pex.spice b/cells/clkbuf/sky130_fd_sc_ls__clkbuf_4.pex.spice
index 3ba1eb5..3e72a95 100644
--- a/cells/clkbuf/sky130_fd_sc_ls__clkbuf_4.pex.spice
+++ b/cells/clkbuf/sky130_fd_sc_ls__clkbuf_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__clkbuf_4.pex.spice
-* Created: Fri Aug 28 13:09:05 2020
+* Created: Wed Sep 2 10:57:43 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/clkbuf/sky130_fd_sc_ls__clkbuf_4.pxi.spice b/cells/clkbuf/sky130_fd_sc_ls__clkbuf_4.pxi.spice
index 4b49665..f57c68c 100644
--- a/cells/clkbuf/sky130_fd_sc_ls__clkbuf_4.pxi.spice
+++ b/cells/clkbuf/sky130_fd_sc_ls__clkbuf_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__clkbuf_4.pxi.spice
-* Created: Fri Aug 28 13:09:05 2020
+* Created: Wed Sep 2 10:57:43 2020
*
x_PM_SKY130_FD_SC_LS__CLKBUF_4%A_83_270# N_A_83_270#_M1003_d N_A_83_270#_M1002_d
+ N_A_83_270#_c_64_n N_A_83_270#_M1000_g N_A_83_270#_M1001_g N_A_83_270#_M1004_g
diff --git a/cells/clkbuf/sky130_fd_sc_ls__clkbuf_4.spice b/cells/clkbuf/sky130_fd_sc_ls__clkbuf_4.spice
index 566848d..923279e 100644
--- a/cells/clkbuf/sky130_fd_sc_ls__clkbuf_4.spice
+++ b/cells/clkbuf/sky130_fd_sc_ls__clkbuf_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__clkbuf_4.spice
-* Created: Fri Aug 28 13:09:05 2020
+* Created: Wed Sep 2 10:57:43 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/clkbuf/sky130_fd_sc_ls__clkbuf_8.lvs.report b/cells/clkbuf/sky130_fd_sc_ls__clkbuf_8.lvs.report
new file mode 100644
index 0000000..ce1636b
--- /dev/null
+++ b/cells/clkbuf/sky130_fd_sc_ls__clkbuf_8.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__clkbuf_8.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__clkbuf_8.sp ('sky130_fd_sc_ls__clkbuf_8')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/clkbuf/sky130_fd_sc_ls__clkbuf_8.spice ('sky130_fd_sc_ls__clkbuf_8')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:57:47 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__clkbuf_8 sky130_fd_sc_ls__clkbuf_8
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__clkbuf_8
+SOURCE CELL NAME: sky130_fd_sc_ls__clkbuf_8
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 7 7
+
+ Instances: 10 10 MN (4 pins)
+ 10 10 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 21 20
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 7 7
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 7 7 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 20 layout mos transistors were reduced to 4.
+ 16 mos transistors were deleted by parallel reduction.
+ 20 source mos transistors were reduced to 4.
+ 16 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/clkbuf/sky130_fd_sc_ls__clkbuf_8.pex.spice b/cells/clkbuf/sky130_fd_sc_ls__clkbuf_8.pex.spice
index 25deb1b..3009f7a 100644
--- a/cells/clkbuf/sky130_fd_sc_ls__clkbuf_8.pex.spice
+++ b/cells/clkbuf/sky130_fd_sc_ls__clkbuf_8.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__clkbuf_8.pex.spice
-* Created: Fri Aug 28 13:09:13 2020
+* Created: Wed Sep 2 10:57:50 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/clkbuf/sky130_fd_sc_ls__clkbuf_8.pxi.spice b/cells/clkbuf/sky130_fd_sc_ls__clkbuf_8.pxi.spice
index dbf619e..8de58eb 100644
--- a/cells/clkbuf/sky130_fd_sc_ls__clkbuf_8.pxi.spice
+++ b/cells/clkbuf/sky130_fd_sc_ls__clkbuf_8.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__clkbuf_8.pxi.spice
-* Created: Fri Aug 28 13:09:13 2020
+* Created: Wed Sep 2 10:57:50 2020
*
x_PM_SKY130_FD_SC_LS__CLKBUF_8%A N_A_c_116_n N_A_M1011_g N_A_M1008_g N_A_M1009_g
+ N_A_c_117_n N_A_M1014_g A A N_A_c_114_n N_A_c_115_n
diff --git a/cells/clkbuf/sky130_fd_sc_ls__clkbuf_8.spice b/cells/clkbuf/sky130_fd_sc_ls__clkbuf_8.spice
index 7e685ee..2296d1c 100644
--- a/cells/clkbuf/sky130_fd_sc_ls__clkbuf_8.spice
+++ b/cells/clkbuf/sky130_fd_sc_ls__clkbuf_8.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__clkbuf_8.spice
-* Created: Fri Aug 28 13:09:13 2020
+* Created: Wed Sep 2 10:57:50 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/clkdlyinv3sd1/sky130_fd_sc_ls__clkdlyinv3sd1_1.lvs.report b/cells/clkdlyinv3sd1/sky130_fd_sc_ls__clkdlyinv3sd1_1.lvs.report
new file mode 100644
index 0000000..5d58b6c
--- /dev/null
+++ b/cells/clkdlyinv3sd1/sky130_fd_sc_ls__clkdlyinv3sd1_1.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__clkdlyinv3sd1_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__clkdlyinv3sd1_1.sp ('sky130_fd_sc_ls__clkdlyinv3sd1_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/clkdlyinv3sd1/sky130_fd_sc_ls__clkdlyinv3sd1_1.spice ('sky130_fd_sc_ls__clkdlyinv3sd1_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:57:53 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__clkdlyinv3sd1_1 sky130_fd_sc_ls__clkdlyinv3sd1_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__clkdlyinv3sd1_1
+SOURCE CELL NAME: sky130_fd_sc_ls__clkdlyinv3sd1_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 8 8
+
+ Instances: 3 3 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 7 6
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 8 8
+
+ Instances: 3 3 MN (4 pins)
+ 3 3 MP (4 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 3 3 0 0 MN(NSHORT)
+ 3 3 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/clkdlyinv3sd1/sky130_fd_sc_ls__clkdlyinv3sd1_1.pex.spice b/cells/clkdlyinv3sd1/sky130_fd_sc_ls__clkdlyinv3sd1_1.pex.spice
index 6127d3a..11cfbcd 100644
--- a/cells/clkdlyinv3sd1/sky130_fd_sc_ls__clkdlyinv3sd1_1.pex.spice
+++ b/cells/clkdlyinv3sd1/sky130_fd_sc_ls__clkdlyinv3sd1_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__clkdlyinv3sd1_1.pex.spice
-* Created: Fri Aug 28 13:09:21 2020
+* Created: Wed Sep 2 10:57:56 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/clkdlyinv3sd1/sky130_fd_sc_ls__clkdlyinv3sd1_1.pxi.spice b/cells/clkdlyinv3sd1/sky130_fd_sc_ls__clkdlyinv3sd1_1.pxi.spice
index 3c946f0..bf1a8d4 100644
--- a/cells/clkdlyinv3sd1/sky130_fd_sc_ls__clkdlyinv3sd1_1.pxi.spice
+++ b/cells/clkdlyinv3sd1/sky130_fd_sc_ls__clkdlyinv3sd1_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__clkdlyinv3sd1_1.pxi.spice
-* Created: Fri Aug 28 13:09:21 2020
+* Created: Wed Sep 2 10:57:56 2020
*
x_PM_SKY130_FD_SC_LS__CLKDLYINV3SD1_1%A N_A_M1000_g N_A_c_51_n N_A_c_55_n
+ N_A_M1001_g A A N_A_c_53_n PM_SKY130_FD_SC_LS__CLKDLYINV3SD1_1%A
diff --git a/cells/clkdlyinv3sd1/sky130_fd_sc_ls__clkdlyinv3sd1_1.spice b/cells/clkdlyinv3sd1/sky130_fd_sc_ls__clkdlyinv3sd1_1.spice
index e93fafd..ced380c 100644
--- a/cells/clkdlyinv3sd1/sky130_fd_sc_ls__clkdlyinv3sd1_1.spice
+++ b/cells/clkdlyinv3sd1/sky130_fd_sc_ls__clkdlyinv3sd1_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__clkdlyinv3sd1_1.spice
-* Created: Fri Aug 28 13:09:21 2020
+* Created: Wed Sep 2 10:57:56 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/clkdlyinv3sd2/sky130_fd_sc_ls__clkdlyinv3sd2_1.lvs.report b/cells/clkdlyinv3sd2/sky130_fd_sc_ls__clkdlyinv3sd2_1.lvs.report
new file mode 100644
index 0000000..0f098ce
--- /dev/null
+++ b/cells/clkdlyinv3sd2/sky130_fd_sc_ls__clkdlyinv3sd2_1.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__clkdlyinv3sd2_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__clkdlyinv3sd2_1.sp ('sky130_fd_sc_ls__clkdlyinv3sd2_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/clkdlyinv3sd2/sky130_fd_sc_ls__clkdlyinv3sd2_1.spice ('sky130_fd_sc_ls__clkdlyinv3sd2_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:58:00 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__clkdlyinv3sd2_1 sky130_fd_sc_ls__clkdlyinv3sd2_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__clkdlyinv3sd2_1
+SOURCE CELL NAME: sky130_fd_sc_ls__clkdlyinv3sd2_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 8 8
+
+ Instances: 3 3 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 7 6
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 8 8
+
+ Instances: 3 3 MN (4 pins)
+ 3 3 MP (4 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 3 3 0 0 MN(NSHORT)
+ 3 3 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/clkdlyinv3sd2/sky130_fd_sc_ls__clkdlyinv3sd2_1.pex.spice b/cells/clkdlyinv3sd2/sky130_fd_sc_ls__clkdlyinv3sd2_1.pex.spice
index 12a7181..25216bf 100644
--- a/cells/clkdlyinv3sd2/sky130_fd_sc_ls__clkdlyinv3sd2_1.pex.spice
+++ b/cells/clkdlyinv3sd2/sky130_fd_sc_ls__clkdlyinv3sd2_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__clkdlyinv3sd2_1.pex.spice
-* Created: Fri Aug 28 13:09:30 2020
+* Created: Wed Sep 2 10:58:03 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/clkdlyinv3sd2/sky130_fd_sc_ls__clkdlyinv3sd2_1.pxi.spice b/cells/clkdlyinv3sd2/sky130_fd_sc_ls__clkdlyinv3sd2_1.pxi.spice
index c0799ba..9be15bd 100644
--- a/cells/clkdlyinv3sd2/sky130_fd_sc_ls__clkdlyinv3sd2_1.pxi.spice
+++ b/cells/clkdlyinv3sd2/sky130_fd_sc_ls__clkdlyinv3sd2_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__clkdlyinv3sd2_1.pxi.spice
-* Created: Fri Aug 28 13:09:30 2020
+* Created: Wed Sep 2 10:58:03 2020
*
x_PM_SKY130_FD_SC_LS__CLKDLYINV3SD2_1%A N_A_M1001_g N_A_c_51_n N_A_c_55_n
+ N_A_M1002_g A A N_A_c_53_n PM_SKY130_FD_SC_LS__CLKDLYINV3SD2_1%A
diff --git a/cells/clkdlyinv3sd2/sky130_fd_sc_ls__clkdlyinv3sd2_1.spice b/cells/clkdlyinv3sd2/sky130_fd_sc_ls__clkdlyinv3sd2_1.spice
index 0c198db..a3e0a4f 100644
--- a/cells/clkdlyinv3sd2/sky130_fd_sc_ls__clkdlyinv3sd2_1.spice
+++ b/cells/clkdlyinv3sd2/sky130_fd_sc_ls__clkdlyinv3sd2_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__clkdlyinv3sd2_1.spice
-* Created: Fri Aug 28 13:09:30 2020
+* Created: Wed Sep 2 10:58:03 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/clkdlyinv3sd3/sky130_fd_sc_ls__clkdlyinv3sd3_1.lvs.report b/cells/clkdlyinv3sd3/sky130_fd_sc_ls__clkdlyinv3sd3_1.lvs.report
new file mode 100644
index 0000000..484b30d
--- /dev/null
+++ b/cells/clkdlyinv3sd3/sky130_fd_sc_ls__clkdlyinv3sd3_1.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__clkdlyinv3sd3_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__clkdlyinv3sd3_1.sp ('sky130_fd_sc_ls__clkdlyinv3sd3_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/clkdlyinv3sd3/sky130_fd_sc_ls__clkdlyinv3sd3_1.spice ('sky130_fd_sc_ls__clkdlyinv3sd3_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:58:06 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__clkdlyinv3sd3_1 sky130_fd_sc_ls__clkdlyinv3sd3_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__clkdlyinv3sd3_1
+SOURCE CELL NAME: sky130_fd_sc_ls__clkdlyinv3sd3_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 8 8
+
+ Instances: 3 3 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 7 6
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 8 8
+
+ Instances: 3 3 MN (4 pins)
+ 3 3 MP (4 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 3 3 0 0 MN(NSHORT)
+ 3 3 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/clkdlyinv3sd3/sky130_fd_sc_ls__clkdlyinv3sd3_1.pex.spice b/cells/clkdlyinv3sd3/sky130_fd_sc_ls__clkdlyinv3sd3_1.pex.spice
index 5c3fe68..7ce5fcc 100644
--- a/cells/clkdlyinv3sd3/sky130_fd_sc_ls__clkdlyinv3sd3_1.pex.spice
+++ b/cells/clkdlyinv3sd3/sky130_fd_sc_ls__clkdlyinv3sd3_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__clkdlyinv3sd3_1.pex.spice
-* Created: Fri Aug 28 13:09:38 2020
+* Created: Wed Sep 2 10:58:09 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/clkdlyinv3sd3/sky130_fd_sc_ls__clkdlyinv3sd3_1.pxi.spice b/cells/clkdlyinv3sd3/sky130_fd_sc_ls__clkdlyinv3sd3_1.pxi.spice
index 0e728b1..07ae066 100644
--- a/cells/clkdlyinv3sd3/sky130_fd_sc_ls__clkdlyinv3sd3_1.pxi.spice
+++ b/cells/clkdlyinv3sd3/sky130_fd_sc_ls__clkdlyinv3sd3_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__clkdlyinv3sd3_1.pxi.spice
-* Created: Fri Aug 28 13:09:38 2020
+* Created: Wed Sep 2 10:58:09 2020
*
x_PM_SKY130_FD_SC_LS__CLKDLYINV3SD3_1%A N_A_M1002_g N_A_c_49_n N_A_c_53_n
+ N_A_M1003_g A A N_A_c_51_n PM_SKY130_FD_SC_LS__CLKDLYINV3SD3_1%A
diff --git a/cells/clkdlyinv3sd3/sky130_fd_sc_ls__clkdlyinv3sd3_1.spice b/cells/clkdlyinv3sd3/sky130_fd_sc_ls__clkdlyinv3sd3_1.spice
index aac7f53..85c3d73 100644
--- a/cells/clkdlyinv3sd3/sky130_fd_sc_ls__clkdlyinv3sd3_1.spice
+++ b/cells/clkdlyinv3sd3/sky130_fd_sc_ls__clkdlyinv3sd3_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__clkdlyinv3sd3_1.spice
-* Created: Fri Aug 28 13:09:38 2020
+* Created: Wed Sep 2 10:58:09 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/clkdlyinv5sd1/sky130_fd_sc_ls__clkdlyinv5sd1_1.lvs.report b/cells/clkdlyinv5sd1/sky130_fd_sc_ls__clkdlyinv5sd1_1.lvs.report
new file mode 100644
index 0000000..a7bd9f2
--- /dev/null
+++ b/cells/clkdlyinv5sd1/sky130_fd_sc_ls__clkdlyinv5sd1_1.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__clkdlyinv5sd1_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__clkdlyinv5sd1_1.sp ('sky130_fd_sc_ls__clkdlyinv5sd1_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/clkdlyinv5sd1/sky130_fd_sc_ls__clkdlyinv5sd1_1.spice ('sky130_fd_sc_ls__clkdlyinv5sd1_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:58:12 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__clkdlyinv5sd1_1 sky130_fd_sc_ls__clkdlyinv5sd1_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__clkdlyinv5sd1_1
+SOURCE CELL NAME: sky130_fd_sc_ls__clkdlyinv5sd1_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 10 10
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 10 10
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ ------ ------
+ Total Inst: 10 10
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 5 5 0 0 MN(NSHORT)
+ 5 5 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 10 10 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/clkdlyinv5sd1/sky130_fd_sc_ls__clkdlyinv5sd1_1.pex.spice b/cells/clkdlyinv5sd1/sky130_fd_sc_ls__clkdlyinv5sd1_1.pex.spice
index 835a1b4..1bd6ef0 100644
--- a/cells/clkdlyinv5sd1/sky130_fd_sc_ls__clkdlyinv5sd1_1.pex.spice
+++ b/cells/clkdlyinv5sd1/sky130_fd_sc_ls__clkdlyinv5sd1_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__clkdlyinv5sd1_1.pex.spice
-* Created: Fri Aug 28 13:09:53 2020
+* Created: Wed Sep 2 10:58:15 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/clkdlyinv5sd1/sky130_fd_sc_ls__clkdlyinv5sd1_1.pxi.spice b/cells/clkdlyinv5sd1/sky130_fd_sc_ls__clkdlyinv5sd1_1.pxi.spice
index 21b0e72..3b97404 100644
--- a/cells/clkdlyinv5sd1/sky130_fd_sc_ls__clkdlyinv5sd1_1.pxi.spice
+++ b/cells/clkdlyinv5sd1/sky130_fd_sc_ls__clkdlyinv5sd1_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__clkdlyinv5sd1_1.pxi.spice
-* Created: Fri Aug 28 13:09:53 2020
+* Created: Wed Sep 2 10:58:15 2020
*
x_PM_SKY130_FD_SC_LS__CLKDLYINV5SD1_1%A N_A_M1006_g N_A_c_81_n N_A_c_85_n
+ N_A_M1007_g A A N_A_c_83_n PM_SKY130_FD_SC_LS__CLKDLYINV5SD1_1%A
diff --git a/cells/clkdlyinv5sd1/sky130_fd_sc_ls__clkdlyinv5sd1_1.spice b/cells/clkdlyinv5sd1/sky130_fd_sc_ls__clkdlyinv5sd1_1.spice
index 78eb4cc..59179ad 100644
--- a/cells/clkdlyinv5sd1/sky130_fd_sc_ls__clkdlyinv5sd1_1.spice
+++ b/cells/clkdlyinv5sd1/sky130_fd_sc_ls__clkdlyinv5sd1_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__clkdlyinv5sd1_1.spice
-* Created: Fri Aug 28 13:09:53 2020
+* Created: Wed Sep 2 10:58:15 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/clkdlyinv5sd2/sky130_fd_sc_ls__clkdlyinv5sd2_1.lvs.report b/cells/clkdlyinv5sd2/sky130_fd_sc_ls__clkdlyinv5sd2_1.lvs.report
new file mode 100644
index 0000000..095ff58
--- /dev/null
+++ b/cells/clkdlyinv5sd2/sky130_fd_sc_ls__clkdlyinv5sd2_1.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__clkdlyinv5sd2_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__clkdlyinv5sd2_1.sp ('sky130_fd_sc_ls__clkdlyinv5sd2_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/clkdlyinv5sd2/sky130_fd_sc_ls__clkdlyinv5sd2_1.spice ('sky130_fd_sc_ls__clkdlyinv5sd2_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:58:19 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__clkdlyinv5sd2_1 sky130_fd_sc_ls__clkdlyinv5sd2_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__clkdlyinv5sd2_1
+SOURCE CELL NAME: sky130_fd_sc_ls__clkdlyinv5sd2_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 10 10
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 10 10
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ ------ ------
+ Total Inst: 10 10
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 5 5 0 0 MN(NSHORT)
+ 5 5 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 10 10 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/clkdlyinv5sd2/sky130_fd_sc_ls__clkdlyinv5sd2_1.pex.spice b/cells/clkdlyinv5sd2/sky130_fd_sc_ls__clkdlyinv5sd2_1.pex.spice
index ab9954b..43b3f8a 100644
--- a/cells/clkdlyinv5sd2/sky130_fd_sc_ls__clkdlyinv5sd2_1.pex.spice
+++ b/cells/clkdlyinv5sd2/sky130_fd_sc_ls__clkdlyinv5sd2_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__clkdlyinv5sd2_1.pex.spice
-* Created: Fri Aug 28 13:10:11 2020
+* Created: Wed Sep 2 10:58:22 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/clkdlyinv5sd2/sky130_fd_sc_ls__clkdlyinv5sd2_1.pxi.spice b/cells/clkdlyinv5sd2/sky130_fd_sc_ls__clkdlyinv5sd2_1.pxi.spice
index ddd2646..7a4105a 100644
--- a/cells/clkdlyinv5sd2/sky130_fd_sc_ls__clkdlyinv5sd2_1.pxi.spice
+++ b/cells/clkdlyinv5sd2/sky130_fd_sc_ls__clkdlyinv5sd2_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__clkdlyinv5sd2_1.pxi.spice
-* Created: Fri Aug 28 13:10:11 2020
+* Created: Wed Sep 2 10:58:22 2020
*
x_PM_SKY130_FD_SC_LS__CLKDLYINV5SD2_1%A N_A_M1007_g N_A_c_78_n N_A_c_82_n
+ N_A_M1008_g A A N_A_c_80_n PM_SKY130_FD_SC_LS__CLKDLYINV5SD2_1%A
diff --git a/cells/clkdlyinv5sd2/sky130_fd_sc_ls__clkdlyinv5sd2_1.spice b/cells/clkdlyinv5sd2/sky130_fd_sc_ls__clkdlyinv5sd2_1.spice
index c11164e..a01fd92 100644
--- a/cells/clkdlyinv5sd2/sky130_fd_sc_ls__clkdlyinv5sd2_1.spice
+++ b/cells/clkdlyinv5sd2/sky130_fd_sc_ls__clkdlyinv5sd2_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__clkdlyinv5sd2_1.spice
-* Created: Fri Aug 28 13:10:11 2020
+* Created: Wed Sep 2 10:58:22 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/clkdlyinv5sd3/sky130_fd_sc_ls__clkdlyinv5sd3_1.lvs.report b/cells/clkdlyinv5sd3/sky130_fd_sc_ls__clkdlyinv5sd3_1.lvs.report
new file mode 100644
index 0000000..d0dad35
--- /dev/null
+++ b/cells/clkdlyinv5sd3/sky130_fd_sc_ls__clkdlyinv5sd3_1.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__clkdlyinv5sd3_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__clkdlyinv5sd3_1.sp ('sky130_fd_sc_ls__clkdlyinv5sd3_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/clkdlyinv5sd3/sky130_fd_sc_ls__clkdlyinv5sd3_1.spice ('sky130_fd_sc_ls__clkdlyinv5sd3_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:58:26 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__clkdlyinv5sd3_1 sky130_fd_sc_ls__clkdlyinv5sd3_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__clkdlyinv5sd3_1
+SOURCE CELL NAME: sky130_fd_sc_ls__clkdlyinv5sd3_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 10 10
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 10 10
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ ------ ------
+ Total Inst: 10 10
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 5 5 0 0 MN(NSHORT)
+ 5 5 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 10 10 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/clkdlyinv5sd3/sky130_fd_sc_ls__clkdlyinv5sd3_1.pex.spice b/cells/clkdlyinv5sd3/sky130_fd_sc_ls__clkdlyinv5sd3_1.pex.spice
index 34c00a0..5a24c4c 100644
--- a/cells/clkdlyinv5sd3/sky130_fd_sc_ls__clkdlyinv5sd3_1.pex.spice
+++ b/cells/clkdlyinv5sd3/sky130_fd_sc_ls__clkdlyinv5sd3_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__clkdlyinv5sd3_1.pex.spice
-* Created: Fri Aug 28 13:10:20 2020
+* Created: Wed Sep 2 10:58:29 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/clkdlyinv5sd3/sky130_fd_sc_ls__clkdlyinv5sd3_1.pxi.spice b/cells/clkdlyinv5sd3/sky130_fd_sc_ls__clkdlyinv5sd3_1.pxi.spice
index 2e37681..9a3ad92 100644
--- a/cells/clkdlyinv5sd3/sky130_fd_sc_ls__clkdlyinv5sd3_1.pxi.spice
+++ b/cells/clkdlyinv5sd3/sky130_fd_sc_ls__clkdlyinv5sd3_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__clkdlyinv5sd3_1.pxi.spice
-* Created: Fri Aug 28 13:10:20 2020
+* Created: Wed Sep 2 10:58:29 2020
*
x_PM_SKY130_FD_SC_LS__CLKDLYINV5SD3_1%A N_A_M1007_g N_A_c_74_n N_A_c_78_n
+ N_A_M1009_g A A N_A_c_76_n PM_SKY130_FD_SC_LS__CLKDLYINV5SD3_1%A
diff --git a/cells/clkdlyinv5sd3/sky130_fd_sc_ls__clkdlyinv5sd3_1.spice b/cells/clkdlyinv5sd3/sky130_fd_sc_ls__clkdlyinv5sd3_1.spice
index afe3941..ef3b6f9 100644
--- a/cells/clkdlyinv5sd3/sky130_fd_sc_ls__clkdlyinv5sd3_1.spice
+++ b/cells/clkdlyinv5sd3/sky130_fd_sc_ls__clkdlyinv5sd3_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__clkdlyinv5sd3_1.spice
-* Created: Fri Aug 28 13:10:20 2020
+* Created: Wed Sep 2 10:58:29 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/clkinv/sky130_fd_sc_ls__clkinv_1.lvs.report b/cells/clkinv/sky130_fd_sc_ls__clkinv_1.lvs.report
new file mode 100644
index 0000000..ff7b7f9
--- /dev/null
+++ b/cells/clkinv/sky130_fd_sc_ls__clkinv_1.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__clkinv_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__clkinv_1.sp ('sky130_fd_sc_ls__clkinv_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/clkinv/sky130_fd_sc_ls__clkinv_1.spice ('sky130_fd_sc_ls__clkinv_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:58:40 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__clkinv_1 sky130_fd_sc_ls__clkinv_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__clkinv_1
+SOURCE CELL NAME: sky130_fd_sc_ls__clkinv_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 6 6
+
+ Instances: 1 1 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 4 3
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 6 6
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ ------ ------
+ Total Inst: 2 2
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 6 6 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 2 2 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 2 layout mos transistors were reduced to 1.
+ 1 mos transistor was deleted by parallel reduction.
+ 2 source mos transistors were reduced to 1.
+ 1 mos transistor was deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/clkinv/sky130_fd_sc_ls__clkinv_1.pex.spice b/cells/clkinv/sky130_fd_sc_ls__clkinv_1.pex.spice
index ddcbafd..7291c64 100644
--- a/cells/clkinv/sky130_fd_sc_ls__clkinv_1.pex.spice
+++ b/cells/clkinv/sky130_fd_sc_ls__clkinv_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__clkinv_1.pex.spice
-* Created: Fri Aug 28 13:10:37 2020
+* Created: Wed Sep 2 10:58:43 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/clkinv/sky130_fd_sc_ls__clkinv_1.pxi.spice b/cells/clkinv/sky130_fd_sc_ls__clkinv_1.pxi.spice
index 2d03790..da7de2a 100644
--- a/cells/clkinv/sky130_fd_sc_ls__clkinv_1.pxi.spice
+++ b/cells/clkinv/sky130_fd_sc_ls__clkinv_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__clkinv_1.pxi.spice
-* Created: Fri Aug 28 13:10:37 2020
+* Created: Wed Sep 2 10:58:43 2020
*
x_PM_SKY130_FD_SC_LS__CLKINV_1%A N_A_c_31_n N_A_M1001_g N_A_M1000_g N_A_c_32_n
+ N_A_M1002_g A A N_A_c_28_n N_A_c_29_n N_A_c_30_n
diff --git a/cells/clkinv/sky130_fd_sc_ls__clkinv_1.spice b/cells/clkinv/sky130_fd_sc_ls__clkinv_1.spice
index 949c0eb..966eabe 100644
--- a/cells/clkinv/sky130_fd_sc_ls__clkinv_1.spice
+++ b/cells/clkinv/sky130_fd_sc_ls__clkinv_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__clkinv_1.spice
-* Created: Fri Aug 28 13:10:37 2020
+* Created: Wed Sep 2 10:58:43 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/clkinv/sky130_fd_sc_ls__clkinv_16.lvs.report b/cells/clkinv/sky130_fd_sc_ls__clkinv_16.lvs.report
new file mode 100644
index 0000000..724347c
--- /dev/null
+++ b/cells/clkinv/sky130_fd_sc_ls__clkinv_16.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__clkinv_16.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__clkinv_16.sp ('sky130_fd_sc_ls__clkinv_16')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/clkinv/sky130_fd_sc_ls__clkinv_16.spice ('sky130_fd_sc_ls__clkinv_16')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:58:33 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__clkinv_16 sky130_fd_sc_ls__clkinv_16
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__clkinv_16
+SOURCE CELL NAME: sky130_fd_sc_ls__clkinv_16
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 6 6
+
+ Instances: 16 16 MN (4 pins)
+ 24 24 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 41 40
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 6 6
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ ------ ------
+ Total Inst: 2 2
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 6 6 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 2 2 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 40 layout mos transistors were reduced to 2.
+ 38 mos transistors were deleted by parallel reduction.
+ 40 source mos transistors were reduced to 2.
+ 38 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/clkinv/sky130_fd_sc_ls__clkinv_16.pex.spice b/cells/clkinv/sky130_fd_sc_ls__clkinv_16.pex.spice
index d3ab94b..e4b186f 100644
--- a/cells/clkinv/sky130_fd_sc_ls__clkinv_16.pex.spice
+++ b/cells/clkinv/sky130_fd_sc_ls__clkinv_16.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__clkinv_16.pex.spice
-* Created: Fri Aug 28 13:10:28 2020
+* Created: Wed Sep 2 10:58:36 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/clkinv/sky130_fd_sc_ls__clkinv_16.pxi.spice b/cells/clkinv/sky130_fd_sc_ls__clkinv_16.pxi.spice
index f97570c..e1afee1 100644
--- a/cells/clkinv/sky130_fd_sc_ls__clkinv_16.pxi.spice
+++ b/cells/clkinv/sky130_fd_sc_ls__clkinv_16.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__clkinv_16.pxi.spice
-* Created: Fri Aug 28 13:10:28 2020
+* Created: Wed Sep 2 10:58:36 2020
*
x_PM_SKY130_FD_SC_LS__CLKINV_16%A N_A_M1002_g N_A_c_182_n N_A_M1000_g
+ N_A_M1003_g N_A_c_183_n N_A_M1001_g N_A_M1004_g N_A_c_184_n N_A_M1005_g
diff --git a/cells/clkinv/sky130_fd_sc_ls__clkinv_16.spice b/cells/clkinv/sky130_fd_sc_ls__clkinv_16.spice
index fd8b2be..94d7c60 100644
--- a/cells/clkinv/sky130_fd_sc_ls__clkinv_16.spice
+++ b/cells/clkinv/sky130_fd_sc_ls__clkinv_16.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__clkinv_16.spice
-* Created: Fri Aug 28 13:10:28 2020
+* Created: Wed Sep 2 10:58:36 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/clkinv/sky130_fd_sc_ls__clkinv_2.lvs.report b/cells/clkinv/sky130_fd_sc_ls__clkinv_2.lvs.report
new file mode 100644
index 0000000..33c5f62
--- /dev/null
+++ b/cells/clkinv/sky130_fd_sc_ls__clkinv_2.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__clkinv_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__clkinv_2.sp ('sky130_fd_sc_ls__clkinv_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/clkinv/sky130_fd_sc_ls__clkinv_2.spice ('sky130_fd_sc_ls__clkinv_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:58:47 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__clkinv_2 sky130_fd_sc_ls__clkinv_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__clkinv_2
+SOURCE CELL NAME: sky130_fd_sc_ls__clkinv_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 6 6
+
+ Instances: 2 2 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 6 5
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 6 6
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ ------ ------
+ Total Inst: 2 2
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 6 6 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 2 2 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 5 layout mos transistors were reduced to 2.
+ 3 mos transistors were deleted by parallel reduction.
+ 5 source mos transistors were reduced to 2.
+ 3 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A Y VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/clkinv/sky130_fd_sc_ls__clkinv_2.pex.spice b/cells/clkinv/sky130_fd_sc_ls__clkinv_2.pex.spice
index 98166a3..8623730 100644
--- a/cells/clkinv/sky130_fd_sc_ls__clkinv_2.pex.spice
+++ b/cells/clkinv/sky130_fd_sc_ls__clkinv_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__clkinv_2.pex.spice
-* Created: Fri Aug 28 13:10:45 2020
+* Created: Wed Sep 2 10:58:50 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/clkinv/sky130_fd_sc_ls__clkinv_2.pxi.spice b/cells/clkinv/sky130_fd_sc_ls__clkinv_2.pxi.spice
index f386c0f..5e4d18d 100644
--- a/cells/clkinv/sky130_fd_sc_ls__clkinv_2.pxi.spice
+++ b/cells/clkinv/sky130_fd_sc_ls__clkinv_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__clkinv_2.pxi.spice
-* Created: Fri Aug 28 13:10:45 2020
+* Created: Wed Sep 2 10:58:50 2020
*
x_PM_SKY130_FD_SC_LS__CLKINV_2%A N_A_M1000_g N_A_c_35_n N_A_M1002_g N_A_c_36_n
+ N_A_M1003_g N_A_c_37_n N_A_M1004_g N_A_M1001_g A A A N_A_c_34_n
diff --git a/cells/clkinv/sky130_fd_sc_ls__clkinv_2.spice b/cells/clkinv/sky130_fd_sc_ls__clkinv_2.spice
index 2142342..7331dde 100644
--- a/cells/clkinv/sky130_fd_sc_ls__clkinv_2.spice
+++ b/cells/clkinv/sky130_fd_sc_ls__clkinv_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__clkinv_2.spice
-* Created: Fri Aug 28 13:10:45 2020
+* Created: Wed Sep 2 10:58:50 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/clkinv/sky130_fd_sc_ls__clkinv_4.lvs.report b/cells/clkinv/sky130_fd_sc_ls__clkinv_4.lvs.report
new file mode 100644
index 0000000..0123fbc
--- /dev/null
+++ b/cells/clkinv/sky130_fd_sc_ls__clkinv_4.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__clkinv_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__clkinv_4.sp ('sky130_fd_sc_ls__clkinv_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/clkinv/sky130_fd_sc_ls__clkinv_4.spice ('sky130_fd_sc_ls__clkinv_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:58:54 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__clkinv_4 sky130_fd_sc_ls__clkinv_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__clkinv_4
+SOURCE CELL NAME: sky130_fd_sc_ls__clkinv_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 6 6
+
+ Instances: 4 4 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 6 6
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ ------ ------
+ Total Inst: 2 2
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 6 6 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 2 2 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 10 layout mos transistors were reduced to 2.
+ 8 mos transistors were deleted by parallel reduction.
+ 10 source mos transistors were reduced to 2.
+ 8 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/clkinv/sky130_fd_sc_ls__clkinv_4.pex.spice b/cells/clkinv/sky130_fd_sc_ls__clkinv_4.pex.spice
index 1746a72..de03f54 100644
--- a/cells/clkinv/sky130_fd_sc_ls__clkinv_4.pex.spice
+++ b/cells/clkinv/sky130_fd_sc_ls__clkinv_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__clkinv_4.pex.spice
-* Created: Fri Aug 28 13:11:00 2020
+* Created: Wed Sep 2 10:58:57 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/clkinv/sky130_fd_sc_ls__clkinv_4.pxi.spice b/cells/clkinv/sky130_fd_sc_ls__clkinv_4.pxi.spice
index eacf6d9..5e98b27 100644
--- a/cells/clkinv/sky130_fd_sc_ls__clkinv_4.pxi.spice
+++ b/cells/clkinv/sky130_fd_sc_ls__clkinv_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__clkinv_4.pxi.spice
-* Created: Fri Aug 28 13:11:00 2020
+* Created: Wed Sep 2 10:58:57 2020
*
x_PM_SKY130_FD_SC_LS__CLKINV_4%A N_A_c_63_n N_A_M1000_g N_A_c_55_n N_A_M1001_g
+ N_A_c_65_n N_A_M1002_g N_A_c_66_n N_A_M1003_g N_A_M1004_g N_A_c_67_n
diff --git a/cells/clkinv/sky130_fd_sc_ls__clkinv_4.spice b/cells/clkinv/sky130_fd_sc_ls__clkinv_4.spice
index 65be845..1b2443b 100644
--- a/cells/clkinv/sky130_fd_sc_ls__clkinv_4.spice
+++ b/cells/clkinv/sky130_fd_sc_ls__clkinv_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__clkinv_4.spice
-* Created: Fri Aug 28 13:11:00 2020
+* Created: Wed Sep 2 10:58:57 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/clkinv/sky130_fd_sc_ls__clkinv_8.lvs.report b/cells/clkinv/sky130_fd_sc_ls__clkinv_8.lvs.report
new file mode 100644
index 0000000..101fce9
--- /dev/null
+++ b/cells/clkinv/sky130_fd_sc_ls__clkinv_8.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__clkinv_8.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__clkinv_8.sp ('sky130_fd_sc_ls__clkinv_8')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/clkinv/sky130_fd_sc_ls__clkinv_8.spice ('sky130_fd_sc_ls__clkinv_8')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:59:01 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__clkinv_8 sky130_fd_sc_ls__clkinv_8
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__clkinv_8
+SOURCE CELL NAME: sky130_fd_sc_ls__clkinv_8
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 6 6
+
+ Instances: 8 8 MN (4 pins)
+ 12 12 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 21 20
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 6 6
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ ------ ------
+ Total Inst: 2 2
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 6 6 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 2 2 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 20 layout mos transistors were reduced to 2.
+ 18 mos transistors were deleted by parallel reduction.
+ 20 source mos transistors were reduced to 2.
+ 18 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/clkinv/sky130_fd_sc_ls__clkinv_8.pex.spice b/cells/clkinv/sky130_fd_sc_ls__clkinv_8.pex.spice
index 159d024..3e11a04 100644
--- a/cells/clkinv/sky130_fd_sc_ls__clkinv_8.pex.spice
+++ b/cells/clkinv/sky130_fd_sc_ls__clkinv_8.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__clkinv_8.pex.spice
-* Created: Fri Aug 28 13:11:18 2020
+* Created: Wed Sep 2 10:59:04 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/clkinv/sky130_fd_sc_ls__clkinv_8.pxi.spice b/cells/clkinv/sky130_fd_sc_ls__clkinv_8.pxi.spice
index a86847f..9b5c033 100644
--- a/cells/clkinv/sky130_fd_sc_ls__clkinv_8.pxi.spice
+++ b/cells/clkinv/sky130_fd_sc_ls__clkinv_8.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__clkinv_8.pxi.spice
-* Created: Fri Aug 28 13:11:18 2020
+* Created: Wed Sep 2 10:59:04 2020
*
x_PM_SKY130_FD_SC_LS__CLKINV_8%A N_A_M1005_g N_A_c_92_n N_A_M1000_g N_A_c_93_n
+ N_A_M1001_g N_A_c_94_n N_A_M1002_g N_A_c_95_n N_A_M1003_g N_A_c_96_n
diff --git a/cells/clkinv/sky130_fd_sc_ls__clkinv_8.spice b/cells/clkinv/sky130_fd_sc_ls__clkinv_8.spice
index b460918..f3ec8bd 100644
--- a/cells/clkinv/sky130_fd_sc_ls__clkinv_8.spice
+++ b/cells/clkinv/sky130_fd_sc_ls__clkinv_8.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__clkinv_8.spice
-* Created: Fri Aug 28 13:11:18 2020
+* Created: Wed Sep 2 10:59:04 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/conb/sky130_fd_sc_ls__conb_1.lvs.report b/cells/conb/sky130_fd_sc_ls__conb_1.lvs.report
new file mode 100644
index 0000000..2c951c3
--- /dev/null
+++ b/cells/conb/sky130_fd_sc_ls__conb_1.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__conb_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__conb_1.sp ('sky130_fd_sc_ls__conb_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/conb/sky130_fd_sc_ls__conb_1.spice ('sky130_fd_sc_ls__conb_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:59:08 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__conb_1 sky130_fd_sc_ls__conb_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__conb_1
+SOURCE CELL NAME: sky130_fd_sc_ls__conb_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 6 6
+
+ Instances: 2 2 R (2 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 3 2
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 6 6
+
+ Instances: 2 2 R (2 pins)
+ ------ ------
+ Total Inst: 2 2
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 6 6 0 0
+
+ Instances: 2 2 0 0 R(SHORT)
+ ------- ------- --------- ---------
+ Total Inst: 2 2 0 0
+
+
+o Statistics:
+
+ 2 passthrough layout nets were found.
+ 2 passthrough source nets were found.
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Passthrough Layout Nets And Their Ports:
+
+ (Layout nets which are connected only to ports).
+
+ VPB (port: VPB), VNB (port: VNB),
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB HI VPWR VGND LO
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/conb/sky130_fd_sc_ls__conb_1.pex.spice b/cells/conb/sky130_fd_sc_ls__conb_1.pex.spice
index f2e0bf9..dcf74ff 100644
--- a/cells/conb/sky130_fd_sc_ls__conb_1.pex.spice
+++ b/cells/conb/sky130_fd_sc_ls__conb_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__conb_1.pex.spice
-* Created: Fri Aug 28 13:11:27 2020
+* Created: Wed Sep 2 10:59:11 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/conb/sky130_fd_sc_ls__conb_1.pxi.spice b/cells/conb/sky130_fd_sc_ls__conb_1.pxi.spice
index 70b029b..7537eba 100644
--- a/cells/conb/sky130_fd_sc_ls__conb_1.pxi.spice
+++ b/cells/conb/sky130_fd_sc_ls__conb_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__conb_1.pxi.spice
-* Created: Fri Aug 28 13:11:27 2020
+* Created: Wed Sep 2 10:59:11 2020
*
x_PM_SKY130_FD_SC_LS__CONB_1%HI HI HI HI HI HI N_HI_R0_pos N_HI_c_24_n
+ N_HI_c_25_n HI PM_SKY130_FD_SC_LS__CONB_1%HI
diff --git a/cells/conb/sky130_fd_sc_ls__conb_1.spice b/cells/conb/sky130_fd_sc_ls__conb_1.spice
index db9c526..99b4baa 100644
--- a/cells/conb/sky130_fd_sc_ls__conb_1.spice
+++ b/cells/conb/sky130_fd_sc_ls__conb_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__conb_1.spice
-* Created: Fri Aug 28 13:11:27 2020
+* Created: Wed Sep 2 10:59:11 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/decap/sky130_fd_sc_ls__decap_4.lvs.report b/cells/decap/sky130_fd_sc_ls__decap_4.lvs.report
new file mode 100644
index 0000000..3e8a520
--- /dev/null
+++ b/cells/decap/sky130_fd_sc_ls__decap_4.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__decap_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__decap_4.sp ('sky130_fd_sc_ls__decap_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/decap/sky130_fd_sc_ls__decap_4.spice ('sky130_fd_sc_ls__decap_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:59:15 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__decap_4 sky130_fd_sc_ls__decap_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__decap_4
+SOURCE CELL NAME: sky130_fd_sc_ls__decap_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 4 4
+
+ Nets: 4 4
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 3 2
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 4 4
+
+ Nets: 4 4
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ ------ ------
+ Total Inst: 2 2
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 4 4 0 0
+
+ Nets: 4 4 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 2 2 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB VGND VPWR
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/decap/sky130_fd_sc_ls__decap_4.pex.spice b/cells/decap/sky130_fd_sc_ls__decap_4.pex.spice
index fc41604..eb5aba2 100644
--- a/cells/decap/sky130_fd_sc_ls__decap_4.pex.spice
+++ b/cells/decap/sky130_fd_sc_ls__decap_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__decap_4.pex.spice
-* Created: Fri Aug 28 13:11:35 2020
+* Created: Wed Sep 2 10:59:18 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/decap/sky130_fd_sc_ls__decap_4.pxi.spice b/cells/decap/sky130_fd_sc_ls__decap_4.pxi.spice
index a5874cf..37bdee3 100644
--- a/cells/decap/sky130_fd_sc_ls__decap_4.pxi.spice
+++ b/cells/decap/sky130_fd_sc_ls__decap_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__decap_4.pxi.spice
-* Created: Fri Aug 28 13:11:35 2020
+* Created: Wed Sep 2 10:59:18 2020
*
x_PM_SKY130_FD_SC_LS__DECAP_4%VGND N_VGND_M1001_s N_VGND_M1000_g N_VGND_c_22_n
+ N_VGND_c_23_n N_VGND_c_24_n N_VGND_c_25_n N_VGND_c_26_n N_VGND_c_27_n
diff --git a/cells/decap/sky130_fd_sc_ls__decap_4.spice b/cells/decap/sky130_fd_sc_ls__decap_4.spice
index f79312c..6a16c82 100644
--- a/cells/decap/sky130_fd_sc_ls__decap_4.spice
+++ b/cells/decap/sky130_fd_sc_ls__decap_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__decap_4.spice
-* Created: Fri Aug 28 13:11:35 2020
+* Created: Wed Sep 2 10:59:18 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/decap/sky130_fd_sc_ls__decap_8.lvs.report b/cells/decap/sky130_fd_sc_ls__decap_8.lvs.report
new file mode 100644
index 0000000..e4c354d
--- /dev/null
+++ b/cells/decap/sky130_fd_sc_ls__decap_8.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__decap_8.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__decap_8.sp ('sky130_fd_sc_ls__decap_8')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/decap/sky130_fd_sc_ls__decap_8.spice ('sky130_fd_sc_ls__decap_8')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:59:22 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__decap_8 sky130_fd_sc_ls__decap_8
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__decap_8
+SOURCE CELL NAME: sky130_fd_sc_ls__decap_8
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 4 4
+
+ Nets: 4 4
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 5 4
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 4 4
+
+ Nets: 4 4
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ ------ ------
+ Total Inst: 2 2
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 4 4 0 0
+
+ Nets: 4 4 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 2 2 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB VGND VPWR
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/decap/sky130_fd_sc_ls__decap_8.pex.spice b/cells/decap/sky130_fd_sc_ls__decap_8.pex.spice
index 74d3f8f..a68302f 100644
--- a/cells/decap/sky130_fd_sc_ls__decap_8.pex.spice
+++ b/cells/decap/sky130_fd_sc_ls__decap_8.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__decap_8.pex.spice
-* Created: Fri Aug 28 13:11:43 2020
+* Created: Wed Sep 2 10:59:26 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/decap/sky130_fd_sc_ls__decap_8.pxi.spice b/cells/decap/sky130_fd_sc_ls__decap_8.pxi.spice
index f850b67..375e10c 100644
--- a/cells/decap/sky130_fd_sc_ls__decap_8.pxi.spice
+++ b/cells/decap/sky130_fd_sc_ls__decap_8.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__decap_8.pxi.spice
-* Created: Fri Aug 28 13:11:43 2020
+* Created: Wed Sep 2 10:59:26 2020
*
x_PM_SKY130_FD_SC_LS__DECAP_8%VGND N_VGND_M1000_s N_VGND_M1002_g N_VGND_M1003_g
+ N_VGND_c_34_n N_VGND_c_35_n N_VGND_c_36_n N_VGND_c_37_n N_VGND_c_38_n
diff --git a/cells/decap/sky130_fd_sc_ls__decap_8.spice b/cells/decap/sky130_fd_sc_ls__decap_8.spice
index 15d67bd..6b4b029 100644
--- a/cells/decap/sky130_fd_sc_ls__decap_8.spice
+++ b/cells/decap/sky130_fd_sc_ls__decap_8.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__decap_8.spice
-* Created: Fri Aug 28 13:11:43 2020
+* Created: Wed Sep 2 10:59:26 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/decaphe/sky130_fd_sc_ls__decaphe_18.lvs.report b/cells/decaphe/sky130_fd_sc_ls__decaphe_18.lvs.report
new file mode 100644
index 0000000..2799d71
--- /dev/null
+++ b/cells/decaphe/sky130_fd_sc_ls__decaphe_18.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__decaphe_18.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__decaphe_18.sp ('sky130_fd_sc_ls__decaphe_18')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/decaphe/sky130_fd_sc_ls__decaphe_18.spice ('sky130_fd_sc_ls__decaphe_18')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:59:30 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__decaphe_18 sky130_fd_sc_ls__decaphe_18
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__decaphe_18
+SOURCE CELL NAME: sky130_fd_sc_ls__decaphe_18
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 4 4
+
+ Nets: 4 4
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 3 2
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 4 4
+
+ Nets: 4 4
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ ------ ------
+ Total Inst: 2 2
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 4 4 0 0
+
+ Nets: 4 4 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PSHORT)
+ ------- ------- --------- ---------
+ Total Inst: 2 2 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/decaphe/sky130_fd_sc_ls__decaphe_18.pex.spice b/cells/decaphe/sky130_fd_sc_ls__decaphe_18.pex.spice
index c3e5963..f7ca5fc 100644
--- a/cells/decaphe/sky130_fd_sc_ls__decaphe_18.pex.spice
+++ b/cells/decaphe/sky130_fd_sc_ls__decaphe_18.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__decaphe_18.pex.spice
-* Created: Fri Aug 28 13:11:52 2020
+* Created: Wed Sep 2 10:59:33 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/decaphe/sky130_fd_sc_ls__decaphe_18.pxi.spice b/cells/decaphe/sky130_fd_sc_ls__decaphe_18.pxi.spice
index 1f628c0..bb481bb 100644
--- a/cells/decaphe/sky130_fd_sc_ls__decaphe_18.pxi.spice
+++ b/cells/decaphe/sky130_fd_sc_ls__decaphe_18.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__decaphe_18.pxi.spice
-* Created: Fri Aug 28 13:11:52 2020
+* Created: Wed Sep 2 10:59:33 2020
*
x_PM_SKY130_FD_SC_LS__DECAPHE_18%VPWR N_VPWR_M1001_s N_VPWR_c_15_n
+ N_VPWR_M1000_g N_VPWR_c_16_n VPWR N_VPWR_c_17_n N_VPWR_c_18_n N_VPWR_c_19_n
diff --git a/cells/decaphe/sky130_fd_sc_ls__decaphe_18.spice b/cells/decaphe/sky130_fd_sc_ls__decaphe_18.spice
index 9a1877b..09323d3 100644
--- a/cells/decaphe/sky130_fd_sc_ls__decaphe_18.spice
+++ b/cells/decaphe/sky130_fd_sc_ls__decaphe_18.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__decaphe_18.spice
-* Created: Fri Aug 28 13:11:52 2020
+* Created: Wed Sep 2 10:59:33 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/decaphe/sky130_fd_sc_ls__decaphe_2.lvs.report b/cells/decaphe/sky130_fd_sc_ls__decaphe_2.lvs.report
new file mode 100644
index 0000000..6f491f4
--- /dev/null
+++ b/cells/decaphe/sky130_fd_sc_ls__decaphe_2.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__decaphe_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__decaphe_2.sp ('sky130_fd_sc_ls__decaphe_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/decaphe/sky130_fd_sc_ls__decaphe_2.spice ('sky130_fd_sc_ls__decaphe_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:59:37 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__decaphe_2 sky130_fd_sc_ls__decaphe_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__decaphe_2
+SOURCE CELL NAME: sky130_fd_sc_ls__decaphe_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 4 4
+
+ Nets: 4 4
+
+ Instances: 1 1 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 2 1
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 4 4
+
+ Nets: 4 4
+
+ Instances: 1 1 MP (4 pins)
+ ------ ------
+ Total Inst: 1 1
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 4 4 0 0
+
+ Nets: 4 4 0 0
+
+ Instances: 1 1 0 0 MP(PSHORT)
+ ------- ------- --------- ---------
+ Total Inst: 1 1 0 0
+
+
+o Statistics:
+
+ 1 passthrough layout net was found.
+ 1 passthrough source net was found.
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Passthrough Layout Nets And Their Ports:
+
+ (Layout nets which are connected only to ports).
+
+ VNB (port: VNB),
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB VGND VPWR
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/decaphe/sky130_fd_sc_ls__decaphe_2.pex.spice b/cells/decaphe/sky130_fd_sc_ls__decaphe_2.pex.spice
index d83ec30..d024268 100644
--- a/cells/decaphe/sky130_fd_sc_ls__decaphe_2.pex.spice
+++ b/cells/decaphe/sky130_fd_sc_ls__decaphe_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__decaphe_2.pex.spice
-* Created: Fri Aug 28 13:12:06 2020
+* Created: Wed Sep 2 10:59:40 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/decaphe/sky130_fd_sc_ls__decaphe_2.pxi.spice b/cells/decaphe/sky130_fd_sc_ls__decaphe_2.pxi.spice
index c5cb0e8..5a38a68 100644
--- a/cells/decaphe/sky130_fd_sc_ls__decaphe_2.pxi.spice
+++ b/cells/decaphe/sky130_fd_sc_ls__decaphe_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__decaphe_2.pxi.spice
-* Created: Fri Aug 28 13:12:06 2020
+* Created: Wed Sep 2 10:59:40 2020
*
x_PM_SKY130_FD_SC_LS__DECAPHE_2%VGND N_VGND_M1000_g N_VGND_c_14_n N_VGND_c_15_n
+ VGND N_VGND_c_16_n N_VGND_c_17_n N_VGND_c_18_n
diff --git a/cells/decaphe/sky130_fd_sc_ls__decaphe_2.spice b/cells/decaphe/sky130_fd_sc_ls__decaphe_2.spice
index dc4e87d..9b1ec1b 100644
--- a/cells/decaphe/sky130_fd_sc_ls__decaphe_2.spice
+++ b/cells/decaphe/sky130_fd_sc_ls__decaphe_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__decaphe_2.spice
-* Created: Fri Aug 28 13:12:06 2020
+* Created: Wed Sep 2 10:59:40 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/decaphe/sky130_fd_sc_ls__decaphe_3.lvs.report b/cells/decaphe/sky130_fd_sc_ls__decaphe_3.lvs.report
new file mode 100644
index 0000000..7a6bbf8
--- /dev/null
+++ b/cells/decaphe/sky130_fd_sc_ls__decaphe_3.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__decaphe_3.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__decaphe_3.sp ('sky130_fd_sc_ls__decaphe_3')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/decaphe/sky130_fd_sc_ls__decaphe_3.spice ('sky130_fd_sc_ls__decaphe_3')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:59:44 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__decaphe_3 sky130_fd_sc_ls__decaphe_3
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__decaphe_3
+SOURCE CELL NAME: sky130_fd_sc_ls__decaphe_3
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 4 4
+
+ Nets: 4 4
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 3 2
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 4 4
+
+ Nets: 4 4
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ ------ ------
+ Total Inst: 2 2
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 4 4 0 0
+
+ Nets: 4 4 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PSHORT)
+ ------- ------- --------- ---------
+ Total Inst: 2 2 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB VGND VPWR
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/decaphe/sky130_fd_sc_ls__decaphe_3.pex.spice b/cells/decaphe/sky130_fd_sc_ls__decaphe_3.pex.spice
index b987c63..48bd116 100644
--- a/cells/decaphe/sky130_fd_sc_ls__decaphe_3.pex.spice
+++ b/cells/decaphe/sky130_fd_sc_ls__decaphe_3.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__decaphe_3.pex.spice
-* Created: Fri Aug 28 13:12:24 2020
+* Created: Wed Sep 2 10:59:47 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/decaphe/sky130_fd_sc_ls__decaphe_3.pxi.spice b/cells/decaphe/sky130_fd_sc_ls__decaphe_3.pxi.spice
index f037e58..68626d8 100644
--- a/cells/decaphe/sky130_fd_sc_ls__decaphe_3.pxi.spice
+++ b/cells/decaphe/sky130_fd_sc_ls__decaphe_3.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__decaphe_3.pxi.spice
-* Created: Fri Aug 28 13:12:24 2020
+* Created: Wed Sep 2 10:59:47 2020
*
x_PM_SKY130_FD_SC_LS__DECAPHE_3%VGND N_VGND_M1000_s N_VGND_c_12_n N_VGND_M1001_g
+ VGND N_VGND_c_13_n N_VGND_c_14_n PM_SKY130_FD_SC_LS__DECAPHE_3%VGND
diff --git a/cells/decaphe/sky130_fd_sc_ls__decaphe_3.spice b/cells/decaphe/sky130_fd_sc_ls__decaphe_3.spice
index 8c5a7c6..b193c8f 100644
--- a/cells/decaphe/sky130_fd_sc_ls__decaphe_3.spice
+++ b/cells/decaphe/sky130_fd_sc_ls__decaphe_3.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__decaphe_3.spice
-* Created: Fri Aug 28 13:12:24 2020
+* Created: Wed Sep 2 10:59:47 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/decaphe/sky130_fd_sc_ls__decaphe_4.lvs.report b/cells/decaphe/sky130_fd_sc_ls__decaphe_4.lvs.report
new file mode 100644
index 0000000..5f564c3
--- /dev/null
+++ b/cells/decaphe/sky130_fd_sc_ls__decaphe_4.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__decaphe_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__decaphe_4.sp ('sky130_fd_sc_ls__decaphe_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/decaphe/sky130_fd_sc_ls__decaphe_4.spice ('sky130_fd_sc_ls__decaphe_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:59:51 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__decaphe_4 sky130_fd_sc_ls__decaphe_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__decaphe_4
+SOURCE CELL NAME: sky130_fd_sc_ls__decaphe_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 4 4
+
+ Nets: 4 4
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 3 2
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 4 4
+
+ Nets: 4 4
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ ------ ------
+ Total Inst: 2 2
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 4 4 0 0
+
+ Nets: 4 4 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PSHORT)
+ ------- ------- --------- ---------
+ Total Inst: 2 2 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB VGND VPWR
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/decaphe/sky130_fd_sc_ls__decaphe_4.pex.spice b/cells/decaphe/sky130_fd_sc_ls__decaphe_4.pex.spice
index 5d1136d..5935cfc 100644
--- a/cells/decaphe/sky130_fd_sc_ls__decaphe_4.pex.spice
+++ b/cells/decaphe/sky130_fd_sc_ls__decaphe_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__decaphe_4.pex.spice
-* Created: Fri Aug 28 13:12:33 2020
+* Created: Wed Sep 2 10:59:54 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/decaphe/sky130_fd_sc_ls__decaphe_4.pxi.spice b/cells/decaphe/sky130_fd_sc_ls__decaphe_4.pxi.spice
index c50dc5c..41e4655 100644
--- a/cells/decaphe/sky130_fd_sc_ls__decaphe_4.pxi.spice
+++ b/cells/decaphe/sky130_fd_sc_ls__decaphe_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__decaphe_4.pxi.spice
-* Created: Fri Aug 28 13:12:33 2020
+* Created: Wed Sep 2 10:59:54 2020
*
x_PM_SKY130_FD_SC_LS__DECAPHE_4%VGND N_VGND_M1000_s N_VGND_M1001_g VGND
+ N_VGND_c_12_n N_VGND_c_13_n N_VGND_c_14_n PM_SKY130_FD_SC_LS__DECAPHE_4%VGND
diff --git a/cells/decaphe/sky130_fd_sc_ls__decaphe_4.spice b/cells/decaphe/sky130_fd_sc_ls__decaphe_4.spice
index 291b4ad..8358c68 100644
--- a/cells/decaphe/sky130_fd_sc_ls__decaphe_4.spice
+++ b/cells/decaphe/sky130_fd_sc_ls__decaphe_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__decaphe_4.spice
-* Created: Fri Aug 28 13:12:33 2020
+* Created: Wed Sep 2 10:59:54 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/decaphe/sky130_fd_sc_ls__decaphe_6.lvs.report b/cells/decaphe/sky130_fd_sc_ls__decaphe_6.lvs.report
new file mode 100644
index 0000000..2d3c6f1
--- /dev/null
+++ b/cells/decaphe/sky130_fd_sc_ls__decaphe_6.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__decaphe_6.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__decaphe_6.sp ('sky130_fd_sc_ls__decaphe_6')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/decaphe/sky130_fd_sc_ls__decaphe_6.spice ('sky130_fd_sc_ls__decaphe_6')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:59:58 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__decaphe_6 sky130_fd_sc_ls__decaphe_6
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__decaphe_6
+SOURCE CELL NAME: sky130_fd_sc_ls__decaphe_6
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 4 4
+
+ Nets: 4 4
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 3 2
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 4 4
+
+ Nets: 4 4
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ ------ ------
+ Total Inst: 2 2
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 4 4 0 0
+
+ Nets: 4 4 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PSHORT)
+ ------- ------- --------- ---------
+ Total Inst: 2 2 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB VGND VPWR
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/decaphe/sky130_fd_sc_ls__decaphe_6.pex.spice b/cells/decaphe/sky130_fd_sc_ls__decaphe_6.pex.spice
index dbc259f..0b36d3d 100644
--- a/cells/decaphe/sky130_fd_sc_ls__decaphe_6.pex.spice
+++ b/cells/decaphe/sky130_fd_sc_ls__decaphe_6.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__decaphe_6.pex.spice
-* Created: Fri Aug 28 13:12:42 2020
+* Created: Wed Sep 2 11:00:01 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/decaphe/sky130_fd_sc_ls__decaphe_6.pxi.spice b/cells/decaphe/sky130_fd_sc_ls__decaphe_6.pxi.spice
index 2b2fb8c..57a152b 100644
--- a/cells/decaphe/sky130_fd_sc_ls__decaphe_6.pxi.spice
+++ b/cells/decaphe/sky130_fd_sc_ls__decaphe_6.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__decaphe_6.pxi.spice
-* Created: Fri Aug 28 13:12:42 2020
+* Created: Wed Sep 2 11:00:01 2020
*
x_PM_SKY130_FD_SC_LS__DECAPHE_6%VGND N_VGND_M1000_s N_VGND_c_13_n N_VGND_c_14_n
+ VGND N_VGND_c_15_n N_VGND_M1001_g N_VGND_c_16_n N_VGND_c_17_n
diff --git a/cells/decaphe/sky130_fd_sc_ls__decaphe_6.spice b/cells/decaphe/sky130_fd_sc_ls__decaphe_6.spice
index 8cd1b5c..cef2b42 100644
--- a/cells/decaphe/sky130_fd_sc_ls__decaphe_6.spice
+++ b/cells/decaphe/sky130_fd_sc_ls__decaphe_6.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__decaphe_6.spice
-* Created: Fri Aug 28 13:12:42 2020
+* Created: Wed Sep 2 11:00:01 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/decaphe/sky130_fd_sc_ls__decaphe_8.lvs.report b/cells/decaphe/sky130_fd_sc_ls__decaphe_8.lvs.report
new file mode 100644
index 0000000..1228d77
--- /dev/null
+++ b/cells/decaphe/sky130_fd_sc_ls__decaphe_8.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__decaphe_8.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__decaphe_8.sp ('sky130_fd_sc_ls__decaphe_8')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/decaphe/sky130_fd_sc_ls__decaphe_8.spice ('sky130_fd_sc_ls__decaphe_8')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:00:05 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__decaphe_8 sky130_fd_sc_ls__decaphe_8
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__decaphe_8
+SOURCE CELL NAME: sky130_fd_sc_ls__decaphe_8
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 4 4
+
+ Nets: 4 4
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 3 2
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 4 4
+
+ Nets: 4 4
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ ------ ------
+ Total Inst: 2 2
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 4 4 0 0
+
+ Nets: 4 4 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PSHORT)
+ ------- ------- --------- ---------
+ Total Inst: 2 2 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB VGND VPWR
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/decaphe/sky130_fd_sc_ls__decaphe_8.pex.spice b/cells/decaphe/sky130_fd_sc_ls__decaphe_8.pex.spice
index 13e7211..03a5cb7 100644
--- a/cells/decaphe/sky130_fd_sc_ls__decaphe_8.pex.spice
+++ b/cells/decaphe/sky130_fd_sc_ls__decaphe_8.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__decaphe_8.pex.spice
-* Created: Fri Aug 28 13:12:50 2020
+* Created: Wed Sep 2 11:00:08 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/decaphe/sky130_fd_sc_ls__decaphe_8.pxi.spice b/cells/decaphe/sky130_fd_sc_ls__decaphe_8.pxi.spice
index 2b55917..ddbb131 100644
--- a/cells/decaphe/sky130_fd_sc_ls__decaphe_8.pxi.spice
+++ b/cells/decaphe/sky130_fd_sc_ls__decaphe_8.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__decaphe_8.pxi.spice
-* Created: Fri Aug 28 13:12:50 2020
+* Created: Wed Sep 2 11:00:08 2020
*
x_PM_SKY130_FD_SC_LS__DECAPHE_8%VGND N_VGND_M1000_s VGND N_VGND_M1001_g
+ N_VGND_c_12_n N_VGND_c_13_n PM_SKY130_FD_SC_LS__DECAPHE_8%VGND
diff --git a/cells/decaphe/sky130_fd_sc_ls__decaphe_8.spice b/cells/decaphe/sky130_fd_sc_ls__decaphe_8.spice
index a6caf6d..3901583 100644
--- a/cells/decaphe/sky130_fd_sc_ls__decaphe_8.spice
+++ b/cells/decaphe/sky130_fd_sc_ls__decaphe_8.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__decaphe_8.spice
-* Created: Fri Aug 28 13:12:50 2020
+* Created: Wed Sep 2 11:00:08 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/decaphetap/sky130_fd_sc_ls__decaphetap_2.lvs.report b/cells/decaphetap/sky130_fd_sc_ls__decaphetap_2.lvs.report
new file mode 100644
index 0000000..548c308
--- /dev/null
+++ b/cells/decaphetap/sky130_fd_sc_ls__decaphetap_2.lvs.report
@@ -0,0 +1,494 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__decaphetap_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__decaphetap_2.sp ('sky130_fd_sc_ls__decaphetap_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/decaphetap/sky130_fd_sc_ls__decaphetap_2.spice ('sky130_fd_sc_ls__decaphetap_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:00:12 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # # #####################
+ # # # #
+ # # INCORRECT #
+ # # # #
+ # # #####################
+
+
+ Error: Different numbers of ports.
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ INCORRECT sky130_fd_sc_ls__decaphetap_2 sky130_fd_sc_ls__decaphetap_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # # #####################
+ # # # #
+ # # INCORRECT #
+ # # # #
+ # # #####################
+
+
+ Error: Different numbers of ports (see below).
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__decaphetap_2
+SOURCE CELL NAME: sky130_fd_sc_ls__decaphetap_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 4 3 *
+
+ Nets: 4 4
+
+ Instances: 1 1 MP (4 pins)
+ 1 1 R (2 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 3 2
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 4 3 *
+
+ Nets: 4 4
+
+ Instances: 1 1 MP (4 pins)
+ 1 1 R (2 pins)
+ ------ ------
+ Total Inst: 2 2
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INCORRECT OBJECTS
+**************************************************************************************************************
+
+
+LEGEND:
+-------
+
+ ne = Naming Error (same layout name found in source
+ circuit, but object was matched otherwise).
+
+
+**************************************************************************************************************
+ INCORRECT PORTS
+
+DISC# LAYOUT NAME SOURCE NAME
+**************************************************************************************************************
+
+ 1 VNB on net: VNB ** missing port **
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 3 3 1 0
+
+ Nets: 4 4 0 0
+
+ Instances: 1 1 0 0 MP(PSHORT)
+ 1 1 0 0 R(SHORT)
+ ------- ------- --------- ---------
+ Total Inst: 2 2 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Layout Names That Are Missing In The Source:
+
+ Ports: VNB
+
+
+o Initial Correspondence Points:
+
+ Ports: VPB VGND VPWR
+ Nets: VNB
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/decaphetap/sky130_fd_sc_ls__decaphetap_2.pex.spice b/cells/decaphetap/sky130_fd_sc_ls__decaphetap_2.pex.spice
index 800fae9..592ad07 100644
--- a/cells/decaphetap/sky130_fd_sc_ls__decaphetap_2.pex.spice
+++ b/cells/decaphetap/sky130_fd_sc_ls__decaphetap_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__decaphetap_2.pex.spice
-* Created: Fri Aug 28 13:12:58 2020
+* Created: Wed Sep 2 11:00:16 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/decaphetap/sky130_fd_sc_ls__decaphetap_2.pxi.spice b/cells/decaphetap/sky130_fd_sc_ls__decaphetap_2.pxi.spice
index 6c51fe2..46e405b 100644
--- a/cells/decaphetap/sky130_fd_sc_ls__decaphetap_2.pxi.spice
+++ b/cells/decaphetap/sky130_fd_sc_ls__decaphetap_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__decaphetap_2.pxi.spice
-* Created: Fri Aug 28 13:12:58 2020
+* Created: Wed Sep 2 11:00:16 2020
*
x_PM_SKY130_FD_SC_LS__DECAPHETAP_2%VNB VNB N_VNB_R0_neg
+ PM_SKY130_FD_SC_LS__DECAPHETAP_2%VNB
diff --git a/cells/decaphetap/sky130_fd_sc_ls__decaphetap_2.spice b/cells/decaphetap/sky130_fd_sc_ls__decaphetap_2.spice
index 7cd4684..e2a8c83 100644
--- a/cells/decaphetap/sky130_fd_sc_ls__decaphetap_2.spice
+++ b/cells/decaphetap/sky130_fd_sc_ls__decaphetap_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__decaphetap_2.spice
-* Created: Fri Aug 28 13:12:58 2020
+* Created: Wed Sep 2 11:00:16 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dfbbn/sky130_fd_sc_ls__dfbbn_1.lvs.report b/cells/dfbbn/sky130_fd_sc_ls__dfbbn_1.lvs.report
new file mode 100644
index 0000000..c86f07b
--- /dev/null
+++ b/cells/dfbbn/sky130_fd_sc_ls__dfbbn_1.lvs.report
@@ -0,0 +1,470 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__dfbbn_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__dfbbn_1.sp ('sky130_fd_sc_ls__dfbbn_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/dfbbn/sky130_fd_sc_ls__dfbbn_1.spice ('sky130_fd_sc_ls__dfbbn_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:00:20 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__dfbbn_1 sky130_fd_sc_ls__dfbbn_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__dfbbn_1
+SOURCE CELL NAME: sky130_fd_sc_ls__dfbbn_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 29 29
+
+ Instances: 20 20 MN (4 pins)
+ 20 20 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 41 40
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 19 19
+
+ Instances: 8 8 MN (4 pins)
+ 10 10 MP (4 pins)
+ 3 3 SMN2 (4 pins)
+ 5 5 SMP2 (4 pins)
+ 2 2 SPMN_2_1 (5 pins)
+ ------ ------
+ Total Inst: 28 28
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 19 19 0 0
+
+ Instances: 8 8 0 0 MN(NSHORT)
+ 10 10 0 0 MP(PHIGHVT)
+ 3 3 0 0 SMN2
+ 5 5 0 0 SMP2
+ 2 2 0 0 SPMN_2_1
+ ------- ------- --------- ---------
+ Total Inst: 28 28 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB CLK_N D SET_B RESET_B VPWR Q_N Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dfbbn/sky130_fd_sc_ls__dfbbn_1.pex.spice b/cells/dfbbn/sky130_fd_sc_ls__dfbbn_1.pex.spice
index aeb673d..41ad6c0 100644
--- a/cells/dfbbn/sky130_fd_sc_ls__dfbbn_1.pex.spice
+++ b/cells/dfbbn/sky130_fd_sc_ls__dfbbn_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dfbbn_1.pex.spice
-* Created: Fri Aug 28 13:13:13 2020
+* Created: Wed Sep 2 11:00:23 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dfbbn/sky130_fd_sc_ls__dfbbn_1.pxi.spice b/cells/dfbbn/sky130_fd_sc_ls__dfbbn_1.pxi.spice
index 204566c..638ea98 100644
--- a/cells/dfbbn/sky130_fd_sc_ls__dfbbn_1.pxi.spice
+++ b/cells/dfbbn/sky130_fd_sc_ls__dfbbn_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dfbbn_1.pxi.spice
-* Created: Fri Aug 28 13:13:13 2020
+* Created: Wed Sep 2 11:00:23 2020
*
x_PM_SKY130_FD_SC_LS__DFBBN_1%CLK_N N_CLK_N_M1033_g N_CLK_N_c_276_n
+ N_CLK_N_M1030_g CLK_N N_CLK_N_c_277_n PM_SKY130_FD_SC_LS__DFBBN_1%CLK_N
diff --git a/cells/dfbbn/sky130_fd_sc_ls__dfbbn_1.spice b/cells/dfbbn/sky130_fd_sc_ls__dfbbn_1.spice
index 50cfc3f..f59cf0d 100644
--- a/cells/dfbbn/sky130_fd_sc_ls__dfbbn_1.spice
+++ b/cells/dfbbn/sky130_fd_sc_ls__dfbbn_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dfbbn_1.spice
-* Created: Fri Aug 28 13:13:13 2020
+* Created: Wed Sep 2 11:00:23 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dfbbn/sky130_fd_sc_ls__dfbbn_2.lvs.report b/cells/dfbbn/sky130_fd_sc_ls__dfbbn_2.lvs.report
new file mode 100644
index 0000000..cffb863
--- /dev/null
+++ b/cells/dfbbn/sky130_fd_sc_ls__dfbbn_2.lvs.report
@@ -0,0 +1,475 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__dfbbn_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__dfbbn_2.sp ('sky130_fd_sc_ls__dfbbn_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/dfbbn/sky130_fd_sc_ls__dfbbn_2.spice ('sky130_fd_sc_ls__dfbbn_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:00:27 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__dfbbn_2 sky130_fd_sc_ls__dfbbn_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__dfbbn_2
+SOURCE CELL NAME: sky130_fd_sc_ls__dfbbn_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 29 29
+
+ Instances: 22 22 MN (4 pins)
+ 22 22 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 45 44
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 19 19
+
+ Instances: 8 8 MN (4 pins)
+ 10 10 MP (4 pins)
+ 3 3 SMN2 (4 pins)
+ 5 5 SMP2 (4 pins)
+ 2 2 SPMN_2_1 (5 pins)
+ ------ ------
+ Total Inst: 28 28
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 19 19 0 0
+
+ Instances: 8 8 0 0 MN(NSHORT)
+ 10 10 0 0 MP(PHIGHVT)
+ 3 3 0 0 SMN2
+ 5 5 0 0 SMP2
+ 2 2 0 0 SPMN_2_1
+ ------- ------- --------- ---------
+ Total Inst: 28 28 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 8 layout mos transistors were reduced to 4.
+ 4 mos transistors were deleted by parallel reduction.
+ 8 source mos transistors were reduced to 4.
+ 4 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB CLK_N D SET_B RESET_B VPWR Q_N Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dfbbn/sky130_fd_sc_ls__dfbbn_2.pex.spice b/cells/dfbbn/sky130_fd_sc_ls__dfbbn_2.pex.spice
index c7f4190..06831ab 100644
--- a/cells/dfbbn/sky130_fd_sc_ls__dfbbn_2.pex.spice
+++ b/cells/dfbbn/sky130_fd_sc_ls__dfbbn_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dfbbn_2.pex.spice
-* Created: Fri Aug 28 13:13:32 2020
+* Created: Wed Sep 2 11:00:30 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dfbbn/sky130_fd_sc_ls__dfbbn_2.pxi.spice b/cells/dfbbn/sky130_fd_sc_ls__dfbbn_2.pxi.spice
index 01b5fda..f7b5af5 100644
--- a/cells/dfbbn/sky130_fd_sc_ls__dfbbn_2.pxi.spice
+++ b/cells/dfbbn/sky130_fd_sc_ls__dfbbn_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dfbbn_2.pxi.spice
-* Created: Fri Aug 28 13:13:32 2020
+* Created: Wed Sep 2 11:00:30 2020
*
x_PM_SKY130_FD_SC_LS__DFBBN_2%CLK_N N_CLK_N_M1032_g N_CLK_N_c_293_n
+ N_CLK_N_M1028_g CLK_N N_CLK_N_c_294_n PM_SKY130_FD_SC_LS__DFBBN_2%CLK_N
diff --git a/cells/dfbbn/sky130_fd_sc_ls__dfbbn_2.spice b/cells/dfbbn/sky130_fd_sc_ls__dfbbn_2.spice
index 4bf8e35..01d9082 100644
--- a/cells/dfbbn/sky130_fd_sc_ls__dfbbn_2.spice
+++ b/cells/dfbbn/sky130_fd_sc_ls__dfbbn_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dfbbn_2.spice
-* Created: Fri Aug 28 13:13:32 2020
+* Created: Wed Sep 2 11:00:30 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dfbbp/sky130_fd_sc_ls__dfbbp_1.lvs.report b/cells/dfbbp/sky130_fd_sc_ls__dfbbp_1.lvs.report
new file mode 100644
index 0000000..83a4b31
--- /dev/null
+++ b/cells/dfbbp/sky130_fd_sc_ls__dfbbp_1.lvs.report
@@ -0,0 +1,470 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__dfbbp_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__dfbbp_1.sp ('sky130_fd_sc_ls__dfbbp_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/dfbbp/sky130_fd_sc_ls__dfbbp_1.spice ('sky130_fd_sc_ls__dfbbp_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:00:34 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__dfbbp_1 sky130_fd_sc_ls__dfbbp_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__dfbbp_1
+SOURCE CELL NAME: sky130_fd_sc_ls__dfbbp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 29 29
+
+ Instances: 20 20 MN (4 pins)
+ 20 20 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 41 40
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 19 19
+
+ Instances: 8 8 MN (4 pins)
+ 10 10 MP (4 pins)
+ 3 3 SMN2 (4 pins)
+ 5 5 SMP2 (4 pins)
+ 2 2 SPMN_2_1 (5 pins)
+ ------ ------
+ Total Inst: 28 28
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 19 19 0 0
+
+ Instances: 8 8 0 0 MN(NSHORT)
+ 10 10 0 0 MP(PHIGHVT)
+ 3 3 0 0 SMN2
+ 5 5 0 0 SMP2
+ 2 2 0 0 SPMN_2_1
+ ------- ------- --------- ---------
+ Total Inst: 28 28 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB CLK D SET_B RESET_B VPWR Q_N Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dfbbp/sky130_fd_sc_ls__dfbbp_1.pex.spice b/cells/dfbbp/sky130_fd_sc_ls__dfbbp_1.pex.spice
index f273970..1d1f675 100644
--- a/cells/dfbbp/sky130_fd_sc_ls__dfbbp_1.pex.spice
+++ b/cells/dfbbp/sky130_fd_sc_ls__dfbbp_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dfbbp_1.pex.spice
-* Created: Fri Aug 28 13:13:41 2020
+* Created: Wed Sep 2 11:00:37 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dfbbp/sky130_fd_sc_ls__dfbbp_1.pxi.spice b/cells/dfbbp/sky130_fd_sc_ls__dfbbp_1.pxi.spice
index 8af07dc..97c6b88 100644
--- a/cells/dfbbp/sky130_fd_sc_ls__dfbbp_1.pxi.spice
+++ b/cells/dfbbp/sky130_fd_sc_ls__dfbbp_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dfbbp_1.pxi.spice
-* Created: Fri Aug 28 13:13:41 2020
+* Created: Wed Sep 2 11:00:37 2020
*
x_PM_SKY130_FD_SC_LS__DFBBP_1%CLK N_CLK_c_267_n N_CLK_M1029_g N_CLK_c_268_n
+ N_CLK_M1037_g CLK PM_SKY130_FD_SC_LS__DFBBP_1%CLK
diff --git a/cells/dfbbp/sky130_fd_sc_ls__dfbbp_1.spice b/cells/dfbbp/sky130_fd_sc_ls__dfbbp_1.spice
index 3111b43..a28a992 100644
--- a/cells/dfbbp/sky130_fd_sc_ls__dfbbp_1.spice
+++ b/cells/dfbbp/sky130_fd_sc_ls__dfbbp_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dfbbp_1.spice
-* Created: Fri Aug 28 13:13:41 2020
+* Created: Wed Sep 2 11:00:37 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dfrbp/sky130_fd_sc_ls__dfrbp_1.lvs.report b/cells/dfrbp/sky130_fd_sc_ls__dfrbp_1.lvs.report
new file mode 100644
index 0000000..20f9ad6
--- /dev/null
+++ b/cells/dfrbp/sky130_fd_sc_ls__dfrbp_1.lvs.report
@@ -0,0 +1,470 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__dfrbp_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__dfrbp_1.sp ('sky130_fd_sc_ls__dfrbp_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/dfrbp/sky130_fd_sc_ls__dfrbp_1.spice ('sky130_fd_sc_ls__dfrbp_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:00:41 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__dfrbp_1 sky130_fd_sc_ls__dfrbp_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__dfrbp_1
+SOURCE CELL NAME: sky130_fd_sc_ls__dfrbp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 24 24
+
+ Instances: 17 17 MN (4 pins)
+ 17 17 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 35 34
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 17 17
+
+ Instances: 8 8 MN (4 pins)
+ 13 13 MP (4 pins)
+ 3 3 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 27 27
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 17 17 0 0
+
+ Instances: 8 8 0 0 MN(NSHORT)
+ 13 13 0 0 MP(PHIGHVT)
+ 3 3 0 0 SMN2
+ 1 1 0 0 SMN3
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 27 27 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D CLK RESET_B VPWR Q_N Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dfrbp/sky130_fd_sc_ls__dfrbp_1.pex.spice b/cells/dfrbp/sky130_fd_sc_ls__dfrbp_1.pex.spice
index 6150104..b39ec82 100644
--- a/cells/dfrbp/sky130_fd_sc_ls__dfrbp_1.pex.spice
+++ b/cells/dfrbp/sky130_fd_sc_ls__dfrbp_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dfrbp_1.pex.spice
-* Created: Fri Aug 28 13:13:49 2020
+* Created: Wed Sep 2 11:00:45 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dfrbp/sky130_fd_sc_ls__dfrbp_1.pxi.spice b/cells/dfrbp/sky130_fd_sc_ls__dfrbp_1.pxi.spice
index 4410583..e663c1c 100644
--- a/cells/dfrbp/sky130_fd_sc_ls__dfrbp_1.pxi.spice
+++ b/cells/dfrbp/sky130_fd_sc_ls__dfrbp_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dfrbp_1.pxi.spice
-* Created: Fri Aug 28 13:13:49 2020
+* Created: Wed Sep 2 11:00:45 2020
*
x_PM_SKY130_FD_SC_LS__DFRBP_1%D N_D_c_247_n N_D_M1021_g N_D_M1007_g N_D_c_248_n
+ D D D N_D_c_244_n N_D_c_245_n N_D_c_246_n PM_SKY130_FD_SC_LS__DFRBP_1%D
diff --git a/cells/dfrbp/sky130_fd_sc_ls__dfrbp_1.spice b/cells/dfrbp/sky130_fd_sc_ls__dfrbp_1.spice
index 881d0b2..ba074e5 100644
--- a/cells/dfrbp/sky130_fd_sc_ls__dfrbp_1.spice
+++ b/cells/dfrbp/sky130_fd_sc_ls__dfrbp_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dfrbp_1.spice
-* Created: Fri Aug 28 13:13:49 2020
+* Created: Wed Sep 2 11:00:45 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dfrbp/sky130_fd_sc_ls__dfrbp_2.lvs.report b/cells/dfrbp/sky130_fd_sc_ls__dfrbp_2.lvs.report
new file mode 100644
index 0000000..ae3f203
--- /dev/null
+++ b/cells/dfrbp/sky130_fd_sc_ls__dfrbp_2.lvs.report
@@ -0,0 +1,475 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__dfrbp_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__dfrbp_2.sp ('sky130_fd_sc_ls__dfrbp_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/dfrbp/sky130_fd_sc_ls__dfrbp_2.spice ('sky130_fd_sc_ls__dfrbp_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:00:49 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__dfrbp_2 sky130_fd_sc_ls__dfrbp_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__dfrbp_2
+SOURCE CELL NAME: sky130_fd_sc_ls__dfrbp_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 24 24
+
+ Instances: 19 19 MN (4 pins)
+ 19 19 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 39 38
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 17 17
+
+ Instances: 8 8 MN (4 pins)
+ 13 13 MP (4 pins)
+ 3 3 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 27 27
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 17 17 0 0
+
+ Instances: 8 8 0 0 MN(NSHORT)
+ 13 13 0 0 MP(PHIGHVT)
+ 3 3 0 0 SMN2
+ 1 1 0 0 SMN3
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 27 27 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 8 layout mos transistors were reduced to 4.
+ 4 mos transistors were deleted by parallel reduction.
+ 8 source mos transistors were reduced to 4.
+ 4 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D RESET_B CLK VPWR Q_N Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dfrbp/sky130_fd_sc_ls__dfrbp_2.pex.spice b/cells/dfrbp/sky130_fd_sc_ls__dfrbp_2.pex.spice
index 2691ae6..78c7913 100644
--- a/cells/dfrbp/sky130_fd_sc_ls__dfrbp_2.pex.spice
+++ b/cells/dfrbp/sky130_fd_sc_ls__dfrbp_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dfrbp_2.pex.spice
-* Created: Fri Aug 28 13:13:58 2020
+* Created: Wed Sep 2 11:00:52 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dfrbp/sky130_fd_sc_ls__dfrbp_2.pxi.spice b/cells/dfrbp/sky130_fd_sc_ls__dfrbp_2.pxi.spice
index 7f123cb..c7277cb 100644
--- a/cells/dfrbp/sky130_fd_sc_ls__dfrbp_2.pxi.spice
+++ b/cells/dfrbp/sky130_fd_sc_ls__dfrbp_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dfrbp_2.pxi.spice
-* Created: Fri Aug 28 13:13:58 2020
+* Created: Wed Sep 2 11:00:52 2020
*
x_PM_SKY130_FD_SC_LS__DFRBP_2%D N_D_c_269_n N_D_c_276_n N_D_M1027_g N_D_M1008_g
+ N_D_c_270_n N_D_c_271_n N_D_c_272_n D D N_D_c_274_n
diff --git a/cells/dfrbp/sky130_fd_sc_ls__dfrbp_2.spice b/cells/dfrbp/sky130_fd_sc_ls__dfrbp_2.spice
index 34e337f..dc29720 100644
--- a/cells/dfrbp/sky130_fd_sc_ls__dfrbp_2.spice
+++ b/cells/dfrbp/sky130_fd_sc_ls__dfrbp_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dfrbp_2.spice
-* Created: Fri Aug 28 13:13:58 2020
+* Created: Wed Sep 2 11:00:52 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dfrtn/sky130_fd_sc_ls__dfrtn_1.lvs.report b/cells/dfrtn/sky130_fd_sc_ls__dfrtn_1.lvs.report
new file mode 100644
index 0000000..cad5e3d
--- /dev/null
+++ b/cells/dfrtn/sky130_fd_sc_ls__dfrtn_1.lvs.report
@@ -0,0 +1,470 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__dfrtn_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__dfrtn_1.sp ('sky130_fd_sc_ls__dfrtn_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/dfrtn/sky130_fd_sc_ls__dfrtn_1.spice ('sky130_fd_sc_ls__dfrtn_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:00:56 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__dfrtn_1 sky130_fd_sc_ls__dfrtn_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__dfrtn_1
+SOURCE CELL NAME: sky130_fd_sc_ls__dfrtn_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 23 23
+
+ Instances: 16 16 MN (4 pins)
+ 16 16 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 33 32
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 16 16
+
+ Instances: 7 7 MN (4 pins)
+ 12 12 MP (4 pins)
+ 3 3 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 25 25
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 16 16 0 0
+
+ Instances: 7 7 0 0 MN(NSHORT)
+ 12 12 0 0 MP(PHIGHVT)
+ 3 3 0 0 SMN2
+ 1 1 0 0 SMN3
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 25 25 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D CLK_N RESET_B VPWR Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dfrtn/sky130_fd_sc_ls__dfrtn_1.pex.spice b/cells/dfrtn/sky130_fd_sc_ls__dfrtn_1.pex.spice
index 07a8d4e..bc797db 100644
--- a/cells/dfrtn/sky130_fd_sc_ls__dfrtn_1.pex.spice
+++ b/cells/dfrtn/sky130_fd_sc_ls__dfrtn_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dfrtn_1.pex.spice
-* Created: Fri Aug 28 13:14:06 2020
+* Created: Wed Sep 2 11:00:59 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dfrtn/sky130_fd_sc_ls__dfrtn_1.pxi.spice b/cells/dfrtn/sky130_fd_sc_ls__dfrtn_1.pxi.spice
index 9fe101f..d6c7b27 100644
--- a/cells/dfrtn/sky130_fd_sc_ls__dfrtn_1.pxi.spice
+++ b/cells/dfrtn/sky130_fd_sc_ls__dfrtn_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dfrtn_1.pxi.spice
-* Created: Fri Aug 28 13:14:06 2020
+* Created: Wed Sep 2 11:00:59 2020
*
x_PM_SKY130_FD_SC_LS__DFRTN_1%D N_D_c_240_n N_D_c_247_n N_D_c_248_n N_D_c_249_n
+ N_D_M1023_g N_D_M1029_g N_D_c_242_n N_D_c_243_n D D D N_D_c_244_n N_D_c_245_n
diff --git a/cells/dfrtn/sky130_fd_sc_ls__dfrtn_1.spice b/cells/dfrtn/sky130_fd_sc_ls__dfrtn_1.spice
index d1d5b70..85ff392 100644
--- a/cells/dfrtn/sky130_fd_sc_ls__dfrtn_1.spice
+++ b/cells/dfrtn/sky130_fd_sc_ls__dfrtn_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dfrtn_1.spice
-* Created: Fri Aug 28 13:14:06 2020
+* Created: Wed Sep 2 11:00:59 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dfrtp/sky130_fd_sc_ls__dfrtp_1.lvs.report b/cells/dfrtp/sky130_fd_sc_ls__dfrtp_1.lvs.report
new file mode 100644
index 0000000..a6d25dc
--- /dev/null
+++ b/cells/dfrtp/sky130_fd_sc_ls__dfrtp_1.lvs.report
@@ -0,0 +1,470 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__dfrtp_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__dfrtp_1.sp ('sky130_fd_sc_ls__dfrtp_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/dfrtp/sky130_fd_sc_ls__dfrtp_1.spice ('sky130_fd_sc_ls__dfrtp_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:01:03 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__dfrtp_1 sky130_fd_sc_ls__dfrtp_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__dfrtp_1
+SOURCE CELL NAME: sky130_fd_sc_ls__dfrtp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 23 23
+
+ Instances: 16 16 MN (4 pins)
+ 16 16 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 33 32
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 16 16
+
+ Instances: 7 7 MN (4 pins)
+ 12 12 MP (4 pins)
+ 3 3 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 25 25
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 16 16 0 0
+
+ Instances: 7 7 0 0 MN(NSHORT)
+ 12 12 0 0 MP(PHIGHVT)
+ 3 3 0 0 SMN2
+ 1 1 0 0 SMN3
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 25 25 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D CLK RESET_B VPWR Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dfrtp/sky130_fd_sc_ls__dfrtp_1.pex.spice b/cells/dfrtp/sky130_fd_sc_ls__dfrtp_1.pex.spice
index d4467a5..4d29941 100644
--- a/cells/dfrtp/sky130_fd_sc_ls__dfrtp_1.pex.spice
+++ b/cells/dfrtp/sky130_fd_sc_ls__dfrtp_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dfrtp_1.pex.spice
-* Created: Fri Aug 28 13:14:21 2020
+* Created: Wed Sep 2 11:01:06 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dfrtp/sky130_fd_sc_ls__dfrtp_1.pxi.spice b/cells/dfrtp/sky130_fd_sc_ls__dfrtp_1.pxi.spice
index 82ab47a..d83e944 100644
--- a/cells/dfrtp/sky130_fd_sc_ls__dfrtp_1.pxi.spice
+++ b/cells/dfrtp/sky130_fd_sc_ls__dfrtp_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dfrtp_1.pxi.spice
-* Created: Fri Aug 28 13:14:21 2020
+* Created: Wed Sep 2 11:01:06 2020
*
x_PM_SKY130_FD_SC_LS__DFRTP_1%D N_D_c_238_n N_D_c_243_n N_D_c_244_n N_D_M1018_g
+ N_D_M1020_g D D D N_D_c_240_n N_D_c_241_n N_D_c_246_n
diff --git a/cells/dfrtp/sky130_fd_sc_ls__dfrtp_1.spice b/cells/dfrtp/sky130_fd_sc_ls__dfrtp_1.spice
index abd8e39..6b3c05e 100644
--- a/cells/dfrtp/sky130_fd_sc_ls__dfrtp_1.spice
+++ b/cells/dfrtp/sky130_fd_sc_ls__dfrtp_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dfrtp_1.spice
-* Created: Fri Aug 28 13:14:21 2020
+* Created: Wed Sep 2 11:01:06 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dfrtp/sky130_fd_sc_ls__dfrtp_2.lvs.report b/cells/dfrtp/sky130_fd_sc_ls__dfrtp_2.lvs.report
new file mode 100644
index 0000000..c189624
--- /dev/null
+++ b/cells/dfrtp/sky130_fd_sc_ls__dfrtp_2.lvs.report
@@ -0,0 +1,475 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__dfrtp_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__dfrtp_2.sp ('sky130_fd_sc_ls__dfrtp_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/dfrtp/sky130_fd_sc_ls__dfrtp_2.spice ('sky130_fd_sc_ls__dfrtp_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:01:10 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__dfrtp_2 sky130_fd_sc_ls__dfrtp_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__dfrtp_2
+SOURCE CELL NAME: sky130_fd_sc_ls__dfrtp_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 23 23
+
+ Instances: 17 17 MN (4 pins)
+ 17 17 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 35 34
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 16 16
+
+ Instances: 7 7 MN (4 pins)
+ 12 12 MP (4 pins)
+ 3 3 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 25 25
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 16 16 0 0
+
+ Instances: 7 7 0 0 MN(NSHORT)
+ 12 12 0 0 MP(PHIGHVT)
+ 3 3 0 0 SMN2
+ 1 1 0 0 SMN3
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 25 25 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D CLK RESET_B VPWR Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dfrtp/sky130_fd_sc_ls__dfrtp_2.pex.spice b/cells/dfrtp/sky130_fd_sc_ls__dfrtp_2.pex.spice
index 03d8b18..01a6cd7 100644
--- a/cells/dfrtp/sky130_fd_sc_ls__dfrtp_2.pex.spice
+++ b/cells/dfrtp/sky130_fd_sc_ls__dfrtp_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dfrtp_2.pex.spice
-* Created: Fri Aug 28 13:14:39 2020
+* Created: Wed Sep 2 11:01:13 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dfrtp/sky130_fd_sc_ls__dfrtp_2.pxi.spice b/cells/dfrtp/sky130_fd_sc_ls__dfrtp_2.pxi.spice
index 0f56801..620b80e 100644
--- a/cells/dfrtp/sky130_fd_sc_ls__dfrtp_2.pxi.spice
+++ b/cells/dfrtp/sky130_fd_sc_ls__dfrtp_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dfrtp_2.pxi.spice
-* Created: Fri Aug 28 13:14:39 2020
+* Created: Wed Sep 2 11:01:13 2020
*
x_PM_SKY130_FD_SC_LS__DFRTP_2%D N_D_c_243_n N_D_c_248_n N_D_c_249_n N_D_M1022_g
+ N_D_M1025_g D D D N_D_c_245_n N_D_c_246_n N_D_c_251_n
diff --git a/cells/dfrtp/sky130_fd_sc_ls__dfrtp_2.spice b/cells/dfrtp/sky130_fd_sc_ls__dfrtp_2.spice
index 4f72526..177d4c4 100644
--- a/cells/dfrtp/sky130_fd_sc_ls__dfrtp_2.spice
+++ b/cells/dfrtp/sky130_fd_sc_ls__dfrtp_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dfrtp_2.spice
-* Created: Fri Aug 28 13:14:39 2020
+* Created: Wed Sep 2 11:01:13 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dfrtp/sky130_fd_sc_ls__dfrtp_4.lvs.report b/cells/dfrtp/sky130_fd_sc_ls__dfrtp_4.lvs.report
new file mode 100644
index 0000000..f4260d9
--- /dev/null
+++ b/cells/dfrtp/sky130_fd_sc_ls__dfrtp_4.lvs.report
@@ -0,0 +1,475 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__dfrtp_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__dfrtp_4.sp ('sky130_fd_sc_ls__dfrtp_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/dfrtp/sky130_fd_sc_ls__dfrtp_4.spice ('sky130_fd_sc_ls__dfrtp_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:01:17 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__dfrtp_4 sky130_fd_sc_ls__dfrtp_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__dfrtp_4
+SOURCE CELL NAME: sky130_fd_sc_ls__dfrtp_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 23 23
+
+ Instances: 19 19 MN (4 pins)
+ 20 20 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 40 39
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 16 16
+
+ Instances: 7 7 MN (4 pins)
+ 12 12 MP (4 pins)
+ 3 3 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 25 25
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 16 16 0 0
+
+ Instances: 7 7 0 0 MN(NSHORT)
+ 12 12 0 0 MP(PHIGHVT)
+ 3 3 0 0 SMN2
+ 1 1 0 0 SMN3
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 25 25 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 10 layout mos transistors were reduced to 3.
+ 7 mos transistors were deleted by parallel reduction.
+ 10 source mos transistors were reduced to 3.
+ 7 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D CLK RESET_B VPWR Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dfrtp/sky130_fd_sc_ls__dfrtp_4.pex.spice b/cells/dfrtp/sky130_fd_sc_ls__dfrtp_4.pex.spice
index 1aac62e..881ac6f 100644
--- a/cells/dfrtp/sky130_fd_sc_ls__dfrtp_4.pex.spice
+++ b/cells/dfrtp/sky130_fd_sc_ls__dfrtp_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dfrtp_4.pex.spice
-* Created: Fri Aug 28 13:14:48 2020
+* Created: Wed Sep 2 11:01:20 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dfrtp/sky130_fd_sc_ls__dfrtp_4.pxi.spice b/cells/dfrtp/sky130_fd_sc_ls__dfrtp_4.pxi.spice
index c5f03de..e6788ea 100644
--- a/cells/dfrtp/sky130_fd_sc_ls__dfrtp_4.pxi.spice
+++ b/cells/dfrtp/sky130_fd_sc_ls__dfrtp_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dfrtp_4.pxi.spice
-* Created: Fri Aug 28 13:14:48 2020
+* Created: Wed Sep 2 11:01:20 2020
*
x_PM_SKY130_FD_SC_LS__DFRTP_4%D N_D_c_276_n N_D_c_281_n N_D_c_282_n N_D_M1021_g
+ N_D_M1012_g D D D N_D_c_278_n N_D_c_279_n N_D_c_284_n
diff --git a/cells/dfrtp/sky130_fd_sc_ls__dfrtp_4.spice b/cells/dfrtp/sky130_fd_sc_ls__dfrtp_4.spice
index 17d5d36..933ceb5 100644
--- a/cells/dfrtp/sky130_fd_sc_ls__dfrtp_4.spice
+++ b/cells/dfrtp/sky130_fd_sc_ls__dfrtp_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dfrtp_4.spice
-* Created: Fri Aug 28 13:14:48 2020
+* Created: Wed Sep 2 11:01:20 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dfsbp/sky130_fd_sc_ls__dfsbp_1.lvs.report b/cells/dfsbp/sky130_fd_sc_ls__dfsbp_1.lvs.report
new file mode 100644
index 0000000..cd5953a
--- /dev/null
+++ b/cells/dfsbp/sky130_fd_sc_ls__dfsbp_1.lvs.report
@@ -0,0 +1,470 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__dfsbp_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__dfsbp_1.sp ('sky130_fd_sc_ls__dfsbp_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/dfsbp/sky130_fd_sc_ls__dfsbp_1.spice ('sky130_fd_sc_ls__dfsbp_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:01:24 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__dfsbp_1 sky130_fd_sc_ls__dfsbp_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__dfsbp_1
+SOURCE CELL NAME: sky130_fd_sc_ls__dfsbp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 25 25
+
+ Instances: 17 17 MN (4 pins)
+ 17 17 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 35 34
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 17 17
+
+ Instances: 8 8 MN (4 pins)
+ 11 11 MP (4 pins)
+ 3 3 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ 3 3 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 26 26
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 17 17 0 0
+
+ Instances: 8 8 0 0 MN(NSHORT)
+ 11 11 0 0 MP(PHIGHVT)
+ 3 3 0 0 SMN2
+ 1 1 0 0 SMN3
+ 3 3 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 26 26 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D CLK SET_B VPWR Q_N Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dfsbp/sky130_fd_sc_ls__dfsbp_1.pex.spice b/cells/dfsbp/sky130_fd_sc_ls__dfsbp_1.pex.spice
index 9112ad9..4dc3930 100644
--- a/cells/dfsbp/sky130_fd_sc_ls__dfsbp_1.pex.spice
+++ b/cells/dfsbp/sky130_fd_sc_ls__dfsbp_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dfsbp_1.pex.spice
-* Created: Fri Aug 28 13:14:58 2020
+* Created: Wed Sep 2 11:01:28 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dfsbp/sky130_fd_sc_ls__dfsbp_1.pxi.spice b/cells/dfsbp/sky130_fd_sc_ls__dfsbp_1.pxi.spice
index af931e3..9aecadd 100644
--- a/cells/dfsbp/sky130_fd_sc_ls__dfsbp_1.pxi.spice
+++ b/cells/dfsbp/sky130_fd_sc_ls__dfsbp_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dfsbp_1.pxi.spice
-* Created: Fri Aug 28 13:14:58 2020
+* Created: Wed Sep 2 11:01:28 2020
*
x_PM_SKY130_FD_SC_LS__DFSBP_1%D N_D_c_270_n N_D_c_275_n N_D_M1002_g N_D_c_276_n
+ N_D_M1016_g D D N_D_c_272_n N_D_c_273_n N_D_c_278_n
diff --git a/cells/dfsbp/sky130_fd_sc_ls__dfsbp_1.spice b/cells/dfsbp/sky130_fd_sc_ls__dfsbp_1.spice
index e26f1bd..fc2e1a2 100644
--- a/cells/dfsbp/sky130_fd_sc_ls__dfsbp_1.spice
+++ b/cells/dfsbp/sky130_fd_sc_ls__dfsbp_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dfsbp_1.spice
-* Created: Fri Aug 28 13:14:58 2020
+* Created: Wed Sep 2 11:01:28 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dfsbp/sky130_fd_sc_ls__dfsbp_2.lvs.report b/cells/dfsbp/sky130_fd_sc_ls__dfsbp_2.lvs.report
new file mode 100644
index 0000000..c5a9c1c
--- /dev/null
+++ b/cells/dfsbp/sky130_fd_sc_ls__dfsbp_2.lvs.report
@@ -0,0 +1,475 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__dfsbp_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__dfsbp_2.sp ('sky130_fd_sc_ls__dfsbp_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/dfsbp/sky130_fd_sc_ls__dfsbp_2.spice ('sky130_fd_sc_ls__dfsbp_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:01:32 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__dfsbp_2 sky130_fd_sc_ls__dfsbp_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__dfsbp_2
+SOURCE CELL NAME: sky130_fd_sc_ls__dfsbp_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 25 25
+
+ Instances: 19 19 MN (4 pins)
+ 19 19 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 39 38
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 17 17
+
+ Instances: 8 8 MN (4 pins)
+ 11 11 MP (4 pins)
+ 3 3 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ 3 3 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 26 26
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 17 17 0 0
+
+ Instances: 8 8 0 0 MN(NSHORT)
+ 11 11 0 0 MP(PHIGHVT)
+ 3 3 0 0 SMN2
+ 1 1 0 0 SMN3
+ 3 3 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 26 26 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 8 layout mos transistors were reduced to 4.
+ 4 mos transistors were deleted by parallel reduction.
+ 8 source mos transistors were reduced to 4.
+ 4 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D CLK SET_B VPWR Q_N Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dfsbp/sky130_fd_sc_ls__dfsbp_2.pex.spice b/cells/dfsbp/sky130_fd_sc_ls__dfsbp_2.pex.spice
index 9026f20..492dbad 100644
--- a/cells/dfsbp/sky130_fd_sc_ls__dfsbp_2.pex.spice
+++ b/cells/dfsbp/sky130_fd_sc_ls__dfsbp_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dfsbp_2.pex.spice
-* Created: Fri Aug 28 13:15:08 2020
+* Created: Wed Sep 2 11:01:35 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dfsbp/sky130_fd_sc_ls__dfsbp_2.pxi.spice b/cells/dfsbp/sky130_fd_sc_ls__dfsbp_2.pxi.spice
index 593b4b2..87fc2bd 100644
--- a/cells/dfsbp/sky130_fd_sc_ls__dfsbp_2.pxi.spice
+++ b/cells/dfsbp/sky130_fd_sc_ls__dfsbp_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dfsbp_2.pxi.spice
-* Created: Fri Aug 28 13:15:08 2020
+* Created: Wed Sep 2 11:01:35 2020
*
x_PM_SKY130_FD_SC_LS__DFSBP_2%D N_D_c_278_n N_D_c_283_n N_D_M1027_g N_D_c_284_n
+ N_D_M1017_g D D N_D_c_280_n N_D_c_281_n N_D_c_286_n
diff --git a/cells/dfsbp/sky130_fd_sc_ls__dfsbp_2.spice b/cells/dfsbp/sky130_fd_sc_ls__dfsbp_2.spice
index 5b13d1f..3da3421 100644
--- a/cells/dfsbp/sky130_fd_sc_ls__dfsbp_2.spice
+++ b/cells/dfsbp/sky130_fd_sc_ls__dfsbp_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dfsbp_2.spice
-* Created: Fri Aug 28 13:15:08 2020
+* Created: Wed Sep 2 11:01:35 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dfstp/sky130_fd_sc_ls__dfstp_1.lvs.report b/cells/dfstp/sky130_fd_sc_ls__dfstp_1.lvs.report
new file mode 100644
index 0000000..4da6f2e
--- /dev/null
+++ b/cells/dfstp/sky130_fd_sc_ls__dfstp_1.lvs.report
@@ -0,0 +1,470 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__dfstp_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__dfstp_1.sp ('sky130_fd_sc_ls__dfstp_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/dfstp/sky130_fd_sc_ls__dfstp_1.spice ('sky130_fd_sc_ls__dfstp_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:01:39 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__dfstp_1 sky130_fd_sc_ls__dfstp_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__dfstp_1
+SOURCE CELL NAME: sky130_fd_sc_ls__dfstp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 24 24
+
+ Instances: 16 16 MN (4 pins)
+ 16 16 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 33 32
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 16 16
+
+ Instances: 7 7 MN (4 pins)
+ 10 10 MP (4 pins)
+ 3 3 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ 3 3 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 24 24
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 16 16 0 0
+
+ Instances: 7 7 0 0 MN(NSHORT)
+ 10 10 0 0 MP(PHIGHVT)
+ 3 3 0 0 SMN2
+ 1 1 0 0 SMN3
+ 3 3 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 24 24 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D CLK SET_B VPWR Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dfstp/sky130_fd_sc_ls__dfstp_1.pex.spice b/cells/dfstp/sky130_fd_sc_ls__dfstp_1.pex.spice
index b47b278..7e33c00 100644
--- a/cells/dfstp/sky130_fd_sc_ls__dfstp_1.pex.spice
+++ b/cells/dfstp/sky130_fd_sc_ls__dfstp_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dfstp_1.pex.spice
-* Created: Fri Aug 28 13:15:25 2020
+* Created: Wed Sep 2 11:01:42 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dfstp/sky130_fd_sc_ls__dfstp_1.pxi.spice b/cells/dfstp/sky130_fd_sc_ls__dfstp_1.pxi.spice
index f881b01..0371b96 100644
--- a/cells/dfstp/sky130_fd_sc_ls__dfstp_1.pxi.spice
+++ b/cells/dfstp/sky130_fd_sc_ls__dfstp_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dfstp_1.pxi.spice
-* Created: Fri Aug 28 13:15:25 2020
+* Created: Wed Sep 2 11:01:42 2020
*
x_PM_SKY130_FD_SC_LS__DFSTP_1%D N_D_c_240_n N_D_c_245_n N_D_M1024_g N_D_c_246_n
+ N_D_M1021_g D D N_D_c_242_n N_D_c_243_n N_D_c_248_n
diff --git a/cells/dfstp/sky130_fd_sc_ls__dfstp_1.spice b/cells/dfstp/sky130_fd_sc_ls__dfstp_1.spice
index e060847..4155244 100644
--- a/cells/dfstp/sky130_fd_sc_ls__dfstp_1.spice
+++ b/cells/dfstp/sky130_fd_sc_ls__dfstp_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dfstp_1.spice
-* Created: Fri Aug 28 13:15:25 2020
+* Created: Wed Sep 2 11:01:42 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dfstp/sky130_fd_sc_ls__dfstp_2.lvs.report b/cells/dfstp/sky130_fd_sc_ls__dfstp_2.lvs.report
new file mode 100644
index 0000000..6d1fdb9
--- /dev/null
+++ b/cells/dfstp/sky130_fd_sc_ls__dfstp_2.lvs.report
@@ -0,0 +1,475 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__dfstp_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__dfstp_2.sp ('sky130_fd_sc_ls__dfstp_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/dfstp/sky130_fd_sc_ls__dfstp_2.spice ('sky130_fd_sc_ls__dfstp_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:01:46 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__dfstp_2 sky130_fd_sc_ls__dfstp_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__dfstp_2
+SOURCE CELL NAME: sky130_fd_sc_ls__dfstp_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 24 24
+
+ Instances: 17 17 MN (4 pins)
+ 17 17 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 35 34
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 16 16
+
+ Instances: 7 7 MN (4 pins)
+ 10 10 MP (4 pins)
+ 3 3 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ 3 3 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 24 24
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 16 16 0 0
+
+ Instances: 7 7 0 0 MN(NSHORT)
+ 10 10 0 0 MP(PHIGHVT)
+ 3 3 0 0 SMN2
+ 1 1 0 0 SMN3
+ 3 3 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 24 24 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D CLK SET_B VPWR Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dfstp/sky130_fd_sc_ls__dfstp_2.pex.spice b/cells/dfstp/sky130_fd_sc_ls__dfstp_2.pex.spice
index 30e09f5..eb3f6d7 100644
--- a/cells/dfstp/sky130_fd_sc_ls__dfstp_2.pex.spice
+++ b/cells/dfstp/sky130_fd_sc_ls__dfstp_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dfstp_2.pex.spice
-* Created: Fri Aug 28 13:15:46 2020
+* Created: Wed Sep 2 11:01:49 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dfstp/sky130_fd_sc_ls__dfstp_2.pxi.spice b/cells/dfstp/sky130_fd_sc_ls__dfstp_2.pxi.spice
index 33ab20c..a203da9 100644
--- a/cells/dfstp/sky130_fd_sc_ls__dfstp_2.pxi.spice
+++ b/cells/dfstp/sky130_fd_sc_ls__dfstp_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dfstp_2.pxi.spice
-* Created: Fri Aug 28 13:15:46 2020
+* Created: Wed Sep 2 11:01:49 2020
*
x_PM_SKY130_FD_SC_LS__DFSTP_2%D N_D_c_245_n N_D_c_250_n N_D_M1026_g N_D_c_251_n
+ N_D_M1018_g D D N_D_c_247_n N_D_c_248_n N_D_c_253_n
diff --git a/cells/dfstp/sky130_fd_sc_ls__dfstp_2.spice b/cells/dfstp/sky130_fd_sc_ls__dfstp_2.spice
index 2a8c737..306bd43 100644
--- a/cells/dfstp/sky130_fd_sc_ls__dfstp_2.spice
+++ b/cells/dfstp/sky130_fd_sc_ls__dfstp_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dfstp_2.spice
-* Created: Fri Aug 28 13:15:46 2020
+* Created: Wed Sep 2 11:01:49 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dfstp/sky130_fd_sc_ls__dfstp_4.lvs.report b/cells/dfstp/sky130_fd_sc_ls__dfstp_4.lvs.report
new file mode 100644
index 0000000..89ada0a
--- /dev/null
+++ b/cells/dfstp/sky130_fd_sc_ls__dfstp_4.lvs.report
@@ -0,0 +1,475 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__dfstp_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__dfstp_4.sp ('sky130_fd_sc_ls__dfstp_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/dfstp/sky130_fd_sc_ls__dfstp_4.spice ('sky130_fd_sc_ls__dfstp_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:01:53 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__dfstp_4 sky130_fd_sc_ls__dfstp_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__dfstp_4
+SOURCE CELL NAME: sky130_fd_sc_ls__dfstp_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 24 24
+
+ Instances: 19 19 MN (4 pins)
+ 20 20 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 40 39
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 16 16
+
+ Instances: 7 7 MN (4 pins)
+ 10 10 MP (4 pins)
+ 3 3 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ 3 3 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 24 24
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 16 16 0 0
+
+ Instances: 7 7 0 0 MN(NSHORT)
+ 10 10 0 0 MP(PHIGHVT)
+ 3 3 0 0 SMN2
+ 1 1 0 0 SMN3
+ 3 3 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 24 24 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 10 layout mos transistors were reduced to 3.
+ 7 mos transistors were deleted by parallel reduction.
+ 10 source mos transistors were reduced to 3.
+ 7 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D CLK SET_B VPWR Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dfstp/sky130_fd_sc_ls__dfstp_4.pex.spice b/cells/dfstp/sky130_fd_sc_ls__dfstp_4.pex.spice
index ed91d1d..853b7a4 100644
--- a/cells/dfstp/sky130_fd_sc_ls__dfstp_4.pex.spice
+++ b/cells/dfstp/sky130_fd_sc_ls__dfstp_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dfstp_4.pex.spice
-* Created: Fri Aug 28 13:15:56 2020
+* Created: Wed Sep 2 11:01:56 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dfstp/sky130_fd_sc_ls__dfstp_4.pxi.spice b/cells/dfstp/sky130_fd_sc_ls__dfstp_4.pxi.spice
index 37b7f8b..0b962fb 100644
--- a/cells/dfstp/sky130_fd_sc_ls__dfstp_4.pxi.spice
+++ b/cells/dfstp/sky130_fd_sc_ls__dfstp_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dfstp_4.pxi.spice
-* Created: Fri Aug 28 13:15:56 2020
+* Created: Wed Sep 2 11:01:56 2020
*
x_PM_SKY130_FD_SC_LS__DFSTP_4%D N_D_c_270_n N_D_c_275_n N_D_M1035_g N_D_c_276_n
+ N_D_M1033_g D D N_D_c_272_n N_D_c_273_n N_D_c_278_n
diff --git a/cells/dfstp/sky130_fd_sc_ls__dfstp_4.spice b/cells/dfstp/sky130_fd_sc_ls__dfstp_4.spice
index 1c14e66..b293cc3 100644
--- a/cells/dfstp/sky130_fd_sc_ls__dfstp_4.spice
+++ b/cells/dfstp/sky130_fd_sc_ls__dfstp_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dfstp_4.spice
-* Created: Fri Aug 28 13:15:56 2020
+* Created: Wed Sep 2 11:01:56 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dfxbp/sky130_fd_sc_ls__dfxbp_1.lvs.report b/cells/dfxbp/sky130_fd_sc_ls__dfxbp_1.lvs.report
new file mode 100644
index 0000000..aeae790
--- /dev/null
+++ b/cells/dfxbp/sky130_fd_sc_ls__dfxbp_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__dfxbp_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__dfxbp_1.sp ('sky130_fd_sc_ls__dfxbp_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/dfxbp/sky130_fd_sc_ls__dfxbp_1.spice ('sky130_fd_sc_ls__dfxbp_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:02:00 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__dfxbp_1 sky130_fd_sc_ls__dfxbp_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__dfxbp_1
+SOURCE CELL NAME: sky130_fd_sc_ls__dfxbp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 20 20
+
+ Instances: 14 14 MN (4 pins)
+ 14 14 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 29 28
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 16 16
+
+ Instances: 10 10 MN (4 pins)
+ 10 10 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 24 24
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 16 16 0 0
+
+ Instances: 10 10 0 0 MN(NSHORT)
+ 10 10 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 24 24 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB CLK D VPWR Q Q_N VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dfxbp/sky130_fd_sc_ls__dfxbp_1.pex.spice b/cells/dfxbp/sky130_fd_sc_ls__dfxbp_1.pex.spice
index 84b78ea..affc6c7 100644
--- a/cells/dfxbp/sky130_fd_sc_ls__dfxbp_1.pex.spice
+++ b/cells/dfxbp/sky130_fd_sc_ls__dfxbp_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dfxbp_1.pex.spice
-* Created: Fri Aug 28 13:16:04 2020
+* Created: Wed Sep 2 11:02:04 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dfxbp/sky130_fd_sc_ls__dfxbp_1.pxi.spice b/cells/dfxbp/sky130_fd_sc_ls__dfxbp_1.pxi.spice
index 70e135a..9fd6772 100644
--- a/cells/dfxbp/sky130_fd_sc_ls__dfxbp_1.pxi.spice
+++ b/cells/dfxbp/sky130_fd_sc_ls__dfxbp_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dfxbp_1.pxi.spice
-* Created: Fri Aug 28 13:16:04 2020
+* Created: Wed Sep 2 11:02:04 2020
*
x_PM_SKY130_FD_SC_LS__DFXBP_1%CLK N_CLK_c_204_n N_CLK_M1023_g N_CLK_c_205_n
+ N_CLK_M1020_g CLK N_CLK_c_206_n PM_SKY130_FD_SC_LS__DFXBP_1%CLK
diff --git a/cells/dfxbp/sky130_fd_sc_ls__dfxbp_1.spice b/cells/dfxbp/sky130_fd_sc_ls__dfxbp_1.spice
index 73216df..246cebf 100644
--- a/cells/dfxbp/sky130_fd_sc_ls__dfxbp_1.spice
+++ b/cells/dfxbp/sky130_fd_sc_ls__dfxbp_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dfxbp_1.spice
-* Created: Fri Aug 28 13:16:04 2020
+* Created: Wed Sep 2 11:02:04 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dfxbp/sky130_fd_sc_ls__dfxbp_2.lvs.report b/cells/dfxbp/sky130_fd_sc_ls__dfxbp_2.lvs.report
new file mode 100644
index 0000000..a486a77
--- /dev/null
+++ b/cells/dfxbp/sky130_fd_sc_ls__dfxbp_2.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__dfxbp_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__dfxbp_2.sp ('sky130_fd_sc_ls__dfxbp_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/dfxbp/sky130_fd_sc_ls__dfxbp_2.spice ('sky130_fd_sc_ls__dfxbp_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:02:08 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__dfxbp_2 sky130_fd_sc_ls__dfxbp_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__dfxbp_2
+SOURCE CELL NAME: sky130_fd_sc_ls__dfxbp_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 20 20
+
+ Instances: 16 16 MN (4 pins)
+ 17 17 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 34 33
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 16 16
+
+ Instances: 10 10 MN (4 pins)
+ 10 10 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 24 24
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 16 16 0 0
+
+ Instances: 10 10 0 0 MN(NSHORT)
+ 10 10 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 24 24 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 10 layout mos transistors were reduced to 5.
+ 5 mos transistors were deleted by parallel reduction.
+ 10 source mos transistors were reduced to 5.
+ 5 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB CLK D VPWR Q Q_N VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dfxbp/sky130_fd_sc_ls__dfxbp_2.pex.spice b/cells/dfxbp/sky130_fd_sc_ls__dfxbp_2.pex.spice
index 50491a0..076b647 100644
--- a/cells/dfxbp/sky130_fd_sc_ls__dfxbp_2.pex.spice
+++ b/cells/dfxbp/sky130_fd_sc_ls__dfxbp_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dfxbp_2.pex.spice
-* Created: Fri Aug 28 13:16:13 2020
+* Created: Wed Sep 2 11:02:11 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dfxbp/sky130_fd_sc_ls__dfxbp_2.pxi.spice b/cells/dfxbp/sky130_fd_sc_ls__dfxbp_2.pxi.spice
index 8f575fb..b58833f 100644
--- a/cells/dfxbp/sky130_fd_sc_ls__dfxbp_2.pxi.spice
+++ b/cells/dfxbp/sky130_fd_sc_ls__dfxbp_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dfxbp_2.pxi.spice
-* Created: Fri Aug 28 13:16:13 2020
+* Created: Wed Sep 2 11:02:11 2020
*
x_PM_SKY130_FD_SC_LS__DFXBP_2%CLK N_CLK_c_221_n N_CLK_M1029_g N_CLK_c_222_n
+ N_CLK_M1022_g CLK N_CLK_c_223_n PM_SKY130_FD_SC_LS__DFXBP_2%CLK
diff --git a/cells/dfxbp/sky130_fd_sc_ls__dfxbp_2.spice b/cells/dfxbp/sky130_fd_sc_ls__dfxbp_2.spice
index 959e08e..b3882a4 100644
--- a/cells/dfxbp/sky130_fd_sc_ls__dfxbp_2.spice
+++ b/cells/dfxbp/sky130_fd_sc_ls__dfxbp_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dfxbp_2.spice
-* Created: Fri Aug 28 13:16:13 2020
+* Created: Wed Sep 2 11:02:11 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dfxtp/sky130_fd_sc_ls__dfxtp_1.lvs.report b/cells/dfxtp/sky130_fd_sc_ls__dfxtp_1.lvs.report
new file mode 100644
index 0000000..fc0fbba
--- /dev/null
+++ b/cells/dfxtp/sky130_fd_sc_ls__dfxtp_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__dfxtp_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__dfxtp_1.sp ('sky130_fd_sc_ls__dfxtp_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/dfxtp/sky130_fd_sc_ls__dfxtp_1.spice ('sky130_fd_sc_ls__dfxtp_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:02:15 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__dfxtp_1 sky130_fd_sc_ls__dfxtp_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__dfxtp_1
+SOURCE CELL NAME: sky130_fd_sc_ls__dfxtp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 18 18
+
+ Instances: 12 12 MN (4 pins)
+ 12 12 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 25 24
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 14 14
+
+ Instances: 8 8 MN (4 pins)
+ 8 8 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 20 20
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 14 14 0 0
+
+ Instances: 8 8 0 0 MN(NSHORT)
+ 8 8 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 20 20 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB CLK D VPWR Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dfxtp/sky130_fd_sc_ls__dfxtp_1.pex.spice b/cells/dfxtp/sky130_fd_sc_ls__dfxtp_1.pex.spice
index e9a80e3..0062275 100644
--- a/cells/dfxtp/sky130_fd_sc_ls__dfxtp_1.pex.spice
+++ b/cells/dfxtp/sky130_fd_sc_ls__dfxtp_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dfxtp_1.pex.spice
-* Created: Fri Aug 28 13:16:28 2020
+* Created: Wed Sep 2 11:02:18 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dfxtp/sky130_fd_sc_ls__dfxtp_1.pxi.spice b/cells/dfxtp/sky130_fd_sc_ls__dfxtp_1.pxi.spice
index 351871c..fe0784a 100644
--- a/cells/dfxtp/sky130_fd_sc_ls__dfxtp_1.pxi.spice
+++ b/cells/dfxtp/sky130_fd_sc_ls__dfxtp_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dfxtp_1.pxi.spice
-* Created: Fri Aug 28 13:16:28 2020
+* Created: Wed Sep 2 11:02:18 2020
*
x_PM_SKY130_FD_SC_LS__DFXTP_1%CLK N_CLK_M1022_g N_CLK_c_183_n N_CLK_M1014_g CLK
+ N_CLK_c_184_n PM_SKY130_FD_SC_LS__DFXTP_1%CLK
diff --git a/cells/dfxtp/sky130_fd_sc_ls__dfxtp_1.spice b/cells/dfxtp/sky130_fd_sc_ls__dfxtp_1.spice
index 6791a28..dbe77f4 100644
--- a/cells/dfxtp/sky130_fd_sc_ls__dfxtp_1.spice
+++ b/cells/dfxtp/sky130_fd_sc_ls__dfxtp_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dfxtp_1.spice
-* Created: Fri Aug 28 13:16:28 2020
+* Created: Wed Sep 2 11:02:18 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dfxtp/sky130_fd_sc_ls__dfxtp_2.lvs.report b/cells/dfxtp/sky130_fd_sc_ls__dfxtp_2.lvs.report
new file mode 100644
index 0000000..1d8dd63
--- /dev/null
+++ b/cells/dfxtp/sky130_fd_sc_ls__dfxtp_2.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__dfxtp_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__dfxtp_2.sp ('sky130_fd_sc_ls__dfxtp_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/dfxtp/sky130_fd_sc_ls__dfxtp_2.spice ('sky130_fd_sc_ls__dfxtp_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:02:22 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__dfxtp_2 sky130_fd_sc_ls__dfxtp_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__dfxtp_2
+SOURCE CELL NAME: sky130_fd_sc_ls__dfxtp_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 18 18
+
+ Instances: 13 13 MN (4 pins)
+ 13 13 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 27 26
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 14 14
+
+ Instances: 8 8 MN (4 pins)
+ 8 8 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 20 20
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 14 14 0 0
+
+ Instances: 8 8 0 0 MN(NSHORT)
+ 8 8 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 20 20 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB CLK D VPWR Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dfxtp/sky130_fd_sc_ls__dfxtp_2.pex.spice b/cells/dfxtp/sky130_fd_sc_ls__dfxtp_2.pex.spice
index 1cc440e..51a9f78 100644
--- a/cells/dfxtp/sky130_fd_sc_ls__dfxtp_2.pex.spice
+++ b/cells/dfxtp/sky130_fd_sc_ls__dfxtp_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dfxtp_2.pex.spice
-* Created: Fri Aug 28 13:16:47 2020
+* Created: Wed Sep 2 11:02:25 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dfxtp/sky130_fd_sc_ls__dfxtp_2.pxi.spice b/cells/dfxtp/sky130_fd_sc_ls__dfxtp_2.pxi.spice
index a2a5bc4..e73752a 100644
--- a/cells/dfxtp/sky130_fd_sc_ls__dfxtp_2.pxi.spice
+++ b/cells/dfxtp/sky130_fd_sc_ls__dfxtp_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dfxtp_2.pxi.spice
-* Created: Fri Aug 28 13:16:47 2020
+* Created: Wed Sep 2 11:02:25 2020
*
x_PM_SKY130_FD_SC_LS__DFXTP_2%CLK N_CLK_M1022_g N_CLK_c_189_n N_CLK_M1016_g CLK
+ N_CLK_c_190_n PM_SKY130_FD_SC_LS__DFXTP_2%CLK
diff --git a/cells/dfxtp/sky130_fd_sc_ls__dfxtp_2.spice b/cells/dfxtp/sky130_fd_sc_ls__dfxtp_2.spice
index 03e1818..d434209 100644
--- a/cells/dfxtp/sky130_fd_sc_ls__dfxtp_2.spice
+++ b/cells/dfxtp/sky130_fd_sc_ls__dfxtp_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dfxtp_2.spice
-* Created: Fri Aug 28 13:16:47 2020
+* Created: Wed Sep 2 11:02:25 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dfxtp/sky130_fd_sc_ls__dfxtp_4.lvs.report b/cells/dfxtp/sky130_fd_sc_ls__dfxtp_4.lvs.report
new file mode 100644
index 0000000..36d3277
--- /dev/null
+++ b/cells/dfxtp/sky130_fd_sc_ls__dfxtp_4.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__dfxtp_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__dfxtp_4.sp ('sky130_fd_sc_ls__dfxtp_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/dfxtp/sky130_fd_sc_ls__dfxtp_4.spice ('sky130_fd_sc_ls__dfxtp_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:02:29 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__dfxtp_4 sky130_fd_sc_ls__dfxtp_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__dfxtp_4
+SOURCE CELL NAME: sky130_fd_sc_ls__dfxtp_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 18 18
+
+ Instances: 15 15 MN (4 pins)
+ 16 16 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 32 31
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 14 14
+
+ Instances: 8 8 MN (4 pins)
+ 8 8 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 20 20
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 14 14 0 0
+
+ Instances: 8 8 0 0 MN(NSHORT)
+ 8 8 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 20 20 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 10 layout mos transistors were reduced to 3.
+ 7 mos transistors were deleted by parallel reduction.
+ 10 source mos transistors were reduced to 3.
+ 7 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB CLK D VPWR Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dfxtp/sky130_fd_sc_ls__dfxtp_4.pex.spice b/cells/dfxtp/sky130_fd_sc_ls__dfxtp_4.pex.spice
index 2e82801..d41cbf2 100644
--- a/cells/dfxtp/sky130_fd_sc_ls__dfxtp_4.pex.spice
+++ b/cells/dfxtp/sky130_fd_sc_ls__dfxtp_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dfxtp_4.pex.spice
-* Created: Fri Aug 28 13:16:55 2020
+* Created: Wed Sep 2 11:02:32 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dfxtp/sky130_fd_sc_ls__dfxtp_4.pxi.spice b/cells/dfxtp/sky130_fd_sc_ls__dfxtp_4.pxi.spice
index a35327d..97213f8 100644
--- a/cells/dfxtp/sky130_fd_sc_ls__dfxtp_4.pxi.spice
+++ b/cells/dfxtp/sky130_fd_sc_ls__dfxtp_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dfxtp_4.pxi.spice
-* Created: Fri Aug 28 13:16:55 2020
+* Created: Wed Sep 2 11:02:32 2020
*
x_PM_SKY130_FD_SC_LS__DFXTP_4%CLK N_CLK_M1025_g N_CLK_c_214_n N_CLK_M1015_g CLK
+ N_CLK_c_215_n PM_SKY130_FD_SC_LS__DFXTP_4%CLK
diff --git a/cells/dfxtp/sky130_fd_sc_ls__dfxtp_4.spice b/cells/dfxtp/sky130_fd_sc_ls__dfxtp_4.spice
index b4b9521..488cb96 100644
--- a/cells/dfxtp/sky130_fd_sc_ls__dfxtp_4.spice
+++ b/cells/dfxtp/sky130_fd_sc_ls__dfxtp_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dfxtp_4.spice
-* Created: Fri Aug 28 13:16:55 2020
+* Created: Wed Sep 2 11:02:32 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/diode/sky130_fd_sc_ls__diode_2.lvs.report b/cells/diode/sky130_fd_sc_ls__diode_2.lvs.report
new file mode 100644
index 0000000..8b49337
--- /dev/null
+++ b/cells/diode/sky130_fd_sc_ls__diode_2.lvs.report
@@ -0,0 +1,497 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__diode_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__diode_2.sp ('sky130_fd_sc_ls__diode_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/diode/sky130_fd_sc_ls__diode_2.spice ('sky130_fd_sc_ls__diode_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:02:37 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # # #####################
+ # # # #
+ # # INCORRECT #
+ # # # #
+ # # #####################
+
+
+ Error: Different numbers of instances.
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ INCORRECT sky130_fd_sc_ls__diode_2 sky130_fd_sc_ls__diode_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # # #####################
+ # # # #
+ # # INCORRECT #
+ # # # #
+ # # #####################
+
+
+ Error: Different numbers of instances (see below).
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__diode_2
+SOURCE CELL NAME: sky130_fd_sc_ls__diode_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 5 5
+
+ Nets: 5 5
+
+ Instances: 0 1 * D (2 pins): p n
+ 1 0 * D (2 pins): p n
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 2 1
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 5 5
+
+ Nets: 5 5
+
+ Instances: 1 0 * D (2 pins): p n
+ ------ ------
+ Total Inst: 1 0
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INCORRECT OBJECTS
+**************************************************************************************************************
+
+
+LEGEND:
+-------
+
+ ne = Naming Error (same layout name found in source
+ circuit, but object was matched otherwise).
+
+
+**************************************************************************************************************
+ INCORRECT INSTANCES
+
+DISC# LAYOUT NAME SOURCE NAME
+**************************************************************************************************************
+
+ 1 D0(0.135,0.320) D(NDIODE) ** missing instance **
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 5 5 0 0
+
+ Nets: 5 5 0 0
+
+ Instances: 0 0 1 0 D(NDIODE)
+ ------- ------- --------- ---------
+ Total Inst: 0 0 1 0
+
+
+o Statistics:
+
+ 3 passthrough layout nets were found.
+ 5 passthrough source nets were found.
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+ 1 source instance was filtered and its pins removed from adjoining nets.
+
+
+o Passthrough Layout Nets And Their Ports:
+
+ (Layout nets which are connected only to ports).
+
+ VPWR (port: VPWR), VGND (port: VGND), VPB (port: VPB),
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB DIODE VGND VPWR
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/diode/sky130_fd_sc_ls__diode_2.pex.spice b/cells/diode/sky130_fd_sc_ls__diode_2.pex.spice
index 0b89679..66aa4f0 100644
--- a/cells/diode/sky130_fd_sc_ls__diode_2.pex.spice
+++ b/cells/diode/sky130_fd_sc_ls__diode_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__diode_2.pex.spice
-* Created: Fri Aug 28 13:17:03 2020
+* Created: Wed Sep 2 11:02:40 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/diode/sky130_fd_sc_ls__diode_2.pxi.spice b/cells/diode/sky130_fd_sc_ls__diode_2.pxi.spice
index 32b869a..9adb5a3 100644
--- a/cells/diode/sky130_fd_sc_ls__diode_2.pxi.spice
+++ b/cells/diode/sky130_fd_sc_ls__diode_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__diode_2.pxi.spice
-* Created: Fri Aug 28 13:17:03 2020
+* Created: Wed Sep 2 11:02:40 2020
*
x_PM_SKY130_FD_SC_LS__DIODE_2%DIODE N_DIODE_D0_noxref_neg DIODE DIODE DIODE
+ DIODE DIODE DIODE DIODE N_DIODE_c_7_n PM_SKY130_FD_SC_LS__DIODE_2%DIODE
diff --git a/cells/diode/sky130_fd_sc_ls__diode_2.spice b/cells/diode/sky130_fd_sc_ls__diode_2.spice
index 04d95cf..109ce23 100644
--- a/cells/diode/sky130_fd_sc_ls__diode_2.spice
+++ b/cells/diode/sky130_fd_sc_ls__diode_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__diode_2.spice
-* Created: Fri Aug 28 13:17:03 2020
+* Created: Wed Sep 2 11:02:40 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dlclkp/sky130_fd_sc_ls__dlclkp_1.lvs.report b/cells/dlclkp/sky130_fd_sc_ls__dlclkp_1.lvs.report
new file mode 100644
index 0000000..3b39b4f
--- /dev/null
+++ b/cells/dlclkp/sky130_fd_sc_ls__dlclkp_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__dlclkp_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__dlclkp_1.sp ('sky130_fd_sc_ls__dlclkp_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/dlclkp/sky130_fd_sc_ls__dlclkp_1.spice ('sky130_fd_sc_ls__dlclkp_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:02:44 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__dlclkp_1 sky130_fd_sc_ls__dlclkp_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__dlclkp_1
+SOURCE CELL NAME: sky130_fd_sc_ls__dlclkp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 17 17
+
+ Instances: 10 10 MN (4 pins)
+ 10 10 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 21 20
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 12 12
+
+ Instances: 4 4 MN (4 pins)
+ 6 6 MP (4 pins)
+ 3 3 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 15 15
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 12 12 0 0
+
+ Instances: 4 4 0 0 MN(NSHORT)
+ 6 6 0 0 MP(PHIGHVT)
+ 3 3 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 15 15 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB GATE CLK VPWR GCLK VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dlclkp/sky130_fd_sc_ls__dlclkp_1.pex.spice b/cells/dlclkp/sky130_fd_sc_ls__dlclkp_1.pex.spice
index dc836c6..6ee5191 100644
--- a/cells/dlclkp/sky130_fd_sc_ls__dlclkp_1.pex.spice
+++ b/cells/dlclkp/sky130_fd_sc_ls__dlclkp_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dlclkp_1.pex.spice
-* Created: Fri Aug 28 13:17:12 2020
+* Created: Wed Sep 2 11:02:47 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dlclkp/sky130_fd_sc_ls__dlclkp_1.pxi.spice b/cells/dlclkp/sky130_fd_sc_ls__dlclkp_1.pxi.spice
index 225536a..8ba3b00 100644
--- a/cells/dlclkp/sky130_fd_sc_ls__dlclkp_1.pxi.spice
+++ b/cells/dlclkp/sky130_fd_sc_ls__dlclkp_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dlclkp_1.pxi.spice
-* Created: Fri Aug 28 13:17:12 2020
+* Created: Wed Sep 2 11:02:47 2020
*
x_PM_SKY130_FD_SC_LS__DLCLKP_1%A_83_260# N_A_83_260#_M1019_d N_A_83_260#_M1013_d
+ N_A_83_260#_M1015_g N_A_83_260#_c_122_n N_A_83_260#_M1010_g
diff --git a/cells/dlclkp/sky130_fd_sc_ls__dlclkp_1.spice b/cells/dlclkp/sky130_fd_sc_ls__dlclkp_1.spice
index 61d1452..b1399c3 100644
--- a/cells/dlclkp/sky130_fd_sc_ls__dlclkp_1.spice
+++ b/cells/dlclkp/sky130_fd_sc_ls__dlclkp_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dlclkp_1.spice
-* Created: Fri Aug 28 13:17:12 2020
+* Created: Wed Sep 2 11:02:47 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dlclkp/sky130_fd_sc_ls__dlclkp_2.lvs.report b/cells/dlclkp/sky130_fd_sc_ls__dlclkp_2.lvs.report
new file mode 100644
index 0000000..6f7c88a
--- /dev/null
+++ b/cells/dlclkp/sky130_fd_sc_ls__dlclkp_2.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__dlclkp_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__dlclkp_2.sp ('sky130_fd_sc_ls__dlclkp_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/dlclkp/sky130_fd_sc_ls__dlclkp_2.spice ('sky130_fd_sc_ls__dlclkp_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:02:51 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__dlclkp_2 sky130_fd_sc_ls__dlclkp_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__dlclkp_2
+SOURCE CELL NAME: sky130_fd_sc_ls__dlclkp_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 17 17
+
+ Instances: 11 11 MN (4 pins)
+ 11 11 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 23 22
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 12 12
+
+ Instances: 4 4 MN (4 pins)
+ 6 6 MP (4 pins)
+ 3 3 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 15 15
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 12 12 0 0
+
+ Instances: 4 4 0 0 MN(NSHORT)
+ 6 6 0 0 MP(PHIGHVT)
+ 3 3 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 15 15 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB GATE CLK VPWR GCLK VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dlclkp/sky130_fd_sc_ls__dlclkp_2.pex.spice b/cells/dlclkp/sky130_fd_sc_ls__dlclkp_2.pex.spice
index 74d6118..e504abf 100644
--- a/cells/dlclkp/sky130_fd_sc_ls__dlclkp_2.pex.spice
+++ b/cells/dlclkp/sky130_fd_sc_ls__dlclkp_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dlclkp_2.pex.spice
-* Created: Fri Aug 28 13:17:21 2020
+* Created: Wed Sep 2 11:02:54 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dlclkp/sky130_fd_sc_ls__dlclkp_2.pxi.spice b/cells/dlclkp/sky130_fd_sc_ls__dlclkp_2.pxi.spice
index 6292d8e..7c6e4dd 100644
--- a/cells/dlclkp/sky130_fd_sc_ls__dlclkp_2.pxi.spice
+++ b/cells/dlclkp/sky130_fd_sc_ls__dlclkp_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dlclkp_2.pxi.spice
-* Created: Fri Aug 28 13:17:21 2020
+* Created: Wed Sep 2 11:02:54 2020
*
x_PM_SKY130_FD_SC_LS__DLCLKP_2%A_83_244# N_A_83_244#_M1013_d N_A_83_244#_M1001_d
+ N_A_83_244#_c_139_n N_A_83_244#_M1018_g N_A_83_244#_c_140_n
diff --git a/cells/dlclkp/sky130_fd_sc_ls__dlclkp_2.spice b/cells/dlclkp/sky130_fd_sc_ls__dlclkp_2.spice
index bc9c00b..3f5021c 100644
--- a/cells/dlclkp/sky130_fd_sc_ls__dlclkp_2.spice
+++ b/cells/dlclkp/sky130_fd_sc_ls__dlclkp_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dlclkp_2.spice
-* Created: Fri Aug 28 13:17:21 2020
+* Created: Wed Sep 2 11:02:54 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dlclkp/sky130_fd_sc_ls__dlclkp_4.lvs.report b/cells/dlclkp/sky130_fd_sc_ls__dlclkp_4.lvs.report
new file mode 100644
index 0000000..8db52f7
--- /dev/null
+++ b/cells/dlclkp/sky130_fd_sc_ls__dlclkp_4.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__dlclkp_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__dlclkp_4.sp ('sky130_fd_sc_ls__dlclkp_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/dlclkp/sky130_fd_sc_ls__dlclkp_4.spice ('sky130_fd_sc_ls__dlclkp_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:02:58 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__dlclkp_4 sky130_fd_sc_ls__dlclkp_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__dlclkp_4
+SOURCE CELL NAME: sky130_fd_sc_ls__dlclkp_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 17 17
+
+ Instances: 13 13 MN (4 pins)
+ 13 13 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 27 26
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 12 12
+
+ Instances: 4 4 MN (4 pins)
+ 6 6 MP (4 pins)
+ 3 3 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 15 15
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 12 12 0 0
+
+ Instances: 4 4 0 0 MN(NSHORT)
+ 6 6 0 0 MP(PHIGHVT)
+ 3 3 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 15 15 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 8 layout mos transistors were reduced to 2.
+ 6 mos transistors were deleted by parallel reduction.
+ 8 source mos transistors were reduced to 2.
+ 6 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB GATE CLK VPWR GCLK VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dlclkp/sky130_fd_sc_ls__dlclkp_4.pex.spice b/cells/dlclkp/sky130_fd_sc_ls__dlclkp_4.pex.spice
index 2853b19..8ceb549 100644
--- a/cells/dlclkp/sky130_fd_sc_ls__dlclkp_4.pex.spice
+++ b/cells/dlclkp/sky130_fd_sc_ls__dlclkp_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dlclkp_4.pex.spice
-* Created: Fri Aug 28 13:17:35 2020
+* Created: Wed Sep 2 11:03:01 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dlclkp/sky130_fd_sc_ls__dlclkp_4.pxi.spice b/cells/dlclkp/sky130_fd_sc_ls__dlclkp_4.pxi.spice
index a48ddee..2de6a2b 100644
--- a/cells/dlclkp/sky130_fd_sc_ls__dlclkp_4.pxi.spice
+++ b/cells/dlclkp/sky130_fd_sc_ls__dlclkp_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dlclkp_4.pxi.spice
-* Created: Fri Aug 28 13:17:35 2020
+* Created: Wed Sep 2 11:03:01 2020
*
x_PM_SKY130_FD_SC_LS__DLCLKP_4%A_84_48# N_A_84_48#_M1019_d N_A_84_48#_M1003_d
+ N_A_84_48#_c_147_n N_A_84_48#_M1022_g N_A_84_48#_c_148_n N_A_84_48#_M1024_g
diff --git a/cells/dlclkp/sky130_fd_sc_ls__dlclkp_4.spice b/cells/dlclkp/sky130_fd_sc_ls__dlclkp_4.spice
index c18efb4..da2455d 100644
--- a/cells/dlclkp/sky130_fd_sc_ls__dlclkp_4.spice
+++ b/cells/dlclkp/sky130_fd_sc_ls__dlclkp_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dlclkp_4.spice
-* Created: Fri Aug 28 13:17:35 2020
+* Created: Wed Sep 2 11:03:01 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dlrbn/sky130_fd_sc_ls__dlrbn_1.lvs.report b/cells/dlrbn/sky130_fd_sc_ls__dlrbn_1.lvs.report
new file mode 100644
index 0000000..729d776
--- /dev/null
+++ b/cells/dlrbn/sky130_fd_sc_ls__dlrbn_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__dlrbn_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__dlrbn_1.sp ('sky130_fd_sc_ls__dlrbn_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/dlrbn/sky130_fd_sc_ls__dlrbn_1.spice ('sky130_fd_sc_ls__dlrbn_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:03:06 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__dlrbn_1 sky130_fd_sc_ls__dlrbn_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__dlrbn_1
+SOURCE CELL NAME: sky130_fd_sc_ls__dlrbn_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 20 20
+
+ Instances: 12 12 MN (4 pins)
+ 12 12 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 25 24
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 15 15
+
+ Instances: 6 6 MN (4 pins)
+ 8 8 MP (4 pins)
+ 3 3 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 19 19
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 15 15 0 0
+
+ Instances: 6 6 0 0 MN(NSHORT)
+ 8 8 0 0 MP(PHIGHVT)
+ 3 3 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 19 19 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D GATE_N RESET_B VPWR Q Q_N VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dlrbn/sky130_fd_sc_ls__dlrbn_1.pex.spice b/cells/dlrbn/sky130_fd_sc_ls__dlrbn_1.pex.spice
index 6280704..0822814 100644
--- a/cells/dlrbn/sky130_fd_sc_ls__dlrbn_1.pex.spice
+++ b/cells/dlrbn/sky130_fd_sc_ls__dlrbn_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dlrbn_1.pex.spice
-* Created: Fri Aug 28 13:17:54 2020
+* Created: Wed Sep 2 11:03:09 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dlrbn/sky130_fd_sc_ls__dlrbn_1.pxi.spice b/cells/dlrbn/sky130_fd_sc_ls__dlrbn_1.pxi.spice
index 69a6dc7..46a9fcb 100644
--- a/cells/dlrbn/sky130_fd_sc_ls__dlrbn_1.pxi.spice
+++ b/cells/dlrbn/sky130_fd_sc_ls__dlrbn_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dlrbn_1.pxi.spice
-* Created: Fri Aug 28 13:17:54 2020
+* Created: Wed Sep 2 11:03:09 2020
*
x_PM_SKY130_FD_SC_LS__DLRBN_1%D N_D_c_155_n N_D_M1008_g N_D_c_160_n N_D_M1016_g
+ D N_D_c_158_n PM_SKY130_FD_SC_LS__DLRBN_1%D
diff --git a/cells/dlrbn/sky130_fd_sc_ls__dlrbn_1.spice b/cells/dlrbn/sky130_fd_sc_ls__dlrbn_1.spice
index 6418248..97437b4 100644
--- a/cells/dlrbn/sky130_fd_sc_ls__dlrbn_1.spice
+++ b/cells/dlrbn/sky130_fd_sc_ls__dlrbn_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dlrbn_1.spice
-* Created: Fri Aug 28 13:17:54 2020
+* Created: Wed Sep 2 11:03:09 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dlrbn/sky130_fd_sc_ls__dlrbn_2.lvs.report b/cells/dlrbn/sky130_fd_sc_ls__dlrbn_2.lvs.report
new file mode 100644
index 0000000..15f8f59
--- /dev/null
+++ b/cells/dlrbn/sky130_fd_sc_ls__dlrbn_2.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__dlrbn_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__dlrbn_2.sp ('sky130_fd_sc_ls__dlrbn_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/dlrbn/sky130_fd_sc_ls__dlrbn_2.spice ('sky130_fd_sc_ls__dlrbn_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:03:13 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__dlrbn_2 sky130_fd_sc_ls__dlrbn_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__dlrbn_2
+SOURCE CELL NAME: sky130_fd_sc_ls__dlrbn_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 20 20
+
+ Instances: 14 14 MN (4 pins)
+ 14 14 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 29 28
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 15 15
+
+ Instances: 6 6 MN (4 pins)
+ 8 8 MP (4 pins)
+ 3 3 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 19 19
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 15 15 0 0
+
+ Instances: 6 6 0 0 MN(NSHORT)
+ 8 8 0 0 MP(PHIGHVT)
+ 3 3 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 19 19 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 8 layout mos transistors were reduced to 4.
+ 4 mos transistors were deleted by parallel reduction.
+ 8 source mos transistors were reduced to 4.
+ 4 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D GATE_N RESET_B VPWR Q Q_N VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dlrbn/sky130_fd_sc_ls__dlrbn_2.pex.spice b/cells/dlrbn/sky130_fd_sc_ls__dlrbn_2.pex.spice
index a5aa5ac..a9d395c 100644
--- a/cells/dlrbn/sky130_fd_sc_ls__dlrbn_2.pex.spice
+++ b/cells/dlrbn/sky130_fd_sc_ls__dlrbn_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dlrbn_2.pex.spice
-* Created: Fri Aug 28 13:18:03 2020
+* Created: Wed Sep 2 11:03:16 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dlrbn/sky130_fd_sc_ls__dlrbn_2.pxi.spice b/cells/dlrbn/sky130_fd_sc_ls__dlrbn_2.pxi.spice
index f4583c6..30035a2 100644
--- a/cells/dlrbn/sky130_fd_sc_ls__dlrbn_2.pxi.spice
+++ b/cells/dlrbn/sky130_fd_sc_ls__dlrbn_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dlrbn_2.pxi.spice
-* Created: Fri Aug 28 13:18:03 2020
+* Created: Wed Sep 2 11:03:16 2020
*
x_PM_SKY130_FD_SC_LS__DLRBN_2%D N_D_c_176_n N_D_M1009_g N_D_c_181_n N_D_M1013_g
+ D N_D_c_179_n PM_SKY130_FD_SC_LS__DLRBN_2%D
diff --git a/cells/dlrbn/sky130_fd_sc_ls__dlrbn_2.spice b/cells/dlrbn/sky130_fd_sc_ls__dlrbn_2.spice
index f9bb25b..cd69773 100644
--- a/cells/dlrbn/sky130_fd_sc_ls__dlrbn_2.spice
+++ b/cells/dlrbn/sky130_fd_sc_ls__dlrbn_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dlrbn_2.spice
-* Created: Fri Aug 28 13:18:03 2020
+* Created: Wed Sep 2 11:03:16 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dlrbp/sky130_fd_sc_ls__dlrbp_1.lvs.report b/cells/dlrbp/sky130_fd_sc_ls__dlrbp_1.lvs.report
new file mode 100644
index 0000000..1ec5127
--- /dev/null
+++ b/cells/dlrbp/sky130_fd_sc_ls__dlrbp_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__dlrbp_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__dlrbp_1.sp ('sky130_fd_sc_ls__dlrbp_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/dlrbp/sky130_fd_sc_ls__dlrbp_1.spice ('sky130_fd_sc_ls__dlrbp_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:03:20 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__dlrbp_1 sky130_fd_sc_ls__dlrbp_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__dlrbp_1
+SOURCE CELL NAME: sky130_fd_sc_ls__dlrbp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 20 20
+
+ Instances: 12 12 MN (4 pins)
+ 12 12 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 25 24
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 15 15
+
+ Instances: 6 6 MN (4 pins)
+ 8 8 MP (4 pins)
+ 3 3 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 19 19
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 15 15 0 0
+
+ Instances: 6 6 0 0 MN(NSHORT)
+ 8 8 0 0 MP(PHIGHVT)
+ 3 3 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 19 19 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D GATE RESET_B VPWR Q Q_N VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dlrbp/sky130_fd_sc_ls__dlrbp_1.pex.spice b/cells/dlrbp/sky130_fd_sc_ls__dlrbp_1.pex.spice
index 0d332fc..afdda37 100644
--- a/cells/dlrbp/sky130_fd_sc_ls__dlrbp_1.pex.spice
+++ b/cells/dlrbp/sky130_fd_sc_ls__dlrbp_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dlrbp_1.pex.spice
-* Created: Fri Aug 28 13:18:11 2020
+* Created: Wed Sep 2 11:03:24 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dlrbp/sky130_fd_sc_ls__dlrbp_1.pxi.spice b/cells/dlrbp/sky130_fd_sc_ls__dlrbp_1.pxi.spice
index 211d355..68622c1 100644
--- a/cells/dlrbp/sky130_fd_sc_ls__dlrbp_1.pxi.spice
+++ b/cells/dlrbp/sky130_fd_sc_ls__dlrbp_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dlrbp_1.pxi.spice
-* Created: Fri Aug 28 13:18:11 2020
+* Created: Wed Sep 2 11:03:24 2020
*
x_PM_SKY130_FD_SC_LS__DLRBP_1%D N_D_M1001_g N_D_c_159_n N_D_M1021_g D
+ PM_SKY130_FD_SC_LS__DLRBP_1%D
diff --git a/cells/dlrbp/sky130_fd_sc_ls__dlrbp_1.spice b/cells/dlrbp/sky130_fd_sc_ls__dlrbp_1.spice
index c2e268d..08aa608 100644
--- a/cells/dlrbp/sky130_fd_sc_ls__dlrbp_1.spice
+++ b/cells/dlrbp/sky130_fd_sc_ls__dlrbp_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dlrbp_1.spice
-* Created: Fri Aug 28 13:18:11 2020
+* Created: Wed Sep 2 11:03:24 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dlrbp/sky130_fd_sc_ls__dlrbp_2.lvs.report b/cells/dlrbp/sky130_fd_sc_ls__dlrbp_2.lvs.report
new file mode 100644
index 0000000..4cb05c1
--- /dev/null
+++ b/cells/dlrbp/sky130_fd_sc_ls__dlrbp_2.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__dlrbp_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__dlrbp_2.sp ('sky130_fd_sc_ls__dlrbp_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/dlrbp/sky130_fd_sc_ls__dlrbp_2.spice ('sky130_fd_sc_ls__dlrbp_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:03:27 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__dlrbp_2 sky130_fd_sc_ls__dlrbp_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__dlrbp_2
+SOURCE CELL NAME: sky130_fd_sc_ls__dlrbp_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 20 20
+
+ Instances: 14 14 MN (4 pins)
+ 14 14 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 29 28
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 15 15
+
+ Instances: 6 6 MN (4 pins)
+ 8 8 MP (4 pins)
+ 3 3 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 19 19
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 15 15 0 0
+
+ Instances: 6 6 0 0 MN(NSHORT)
+ 8 8 0 0 MP(PHIGHVT)
+ 3 3 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 19 19 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 8 layout mos transistors were reduced to 4.
+ 4 mos transistors were deleted by parallel reduction.
+ 8 source mos transistors were reduced to 4.
+ 4 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D GATE RESET_B VPWR Q Q_N VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dlrbp/sky130_fd_sc_ls__dlrbp_2.pex.spice b/cells/dlrbp/sky130_fd_sc_ls__dlrbp_2.pex.spice
index fb33104..fe12774 100644
--- a/cells/dlrbp/sky130_fd_sc_ls__dlrbp_2.pex.spice
+++ b/cells/dlrbp/sky130_fd_sc_ls__dlrbp_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dlrbp_2.pex.spice
-* Created: Fri Aug 28 13:18:19 2020
+* Created: Wed Sep 2 11:03:31 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dlrbp/sky130_fd_sc_ls__dlrbp_2.pxi.spice b/cells/dlrbp/sky130_fd_sc_ls__dlrbp_2.pxi.spice
index e3c469f..002af4d 100644
--- a/cells/dlrbp/sky130_fd_sc_ls__dlrbp_2.pxi.spice
+++ b/cells/dlrbp/sky130_fd_sc_ls__dlrbp_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dlrbp_2.pxi.spice
-* Created: Fri Aug 28 13:18:19 2020
+* Created: Wed Sep 2 11:03:31 2020
*
x_PM_SKY130_FD_SC_LS__DLRBP_2%D N_D_M1012_g N_D_c_173_n N_D_M1019_g D
+ PM_SKY130_FD_SC_LS__DLRBP_2%D
diff --git a/cells/dlrbp/sky130_fd_sc_ls__dlrbp_2.spice b/cells/dlrbp/sky130_fd_sc_ls__dlrbp_2.spice
index 015041f..7cf3757 100644
--- a/cells/dlrbp/sky130_fd_sc_ls__dlrbp_2.spice
+++ b/cells/dlrbp/sky130_fd_sc_ls__dlrbp_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dlrbp_2.spice
-* Created: Fri Aug 28 13:18:19 2020
+* Created: Wed Sep 2 11:03:31 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dlrtn/sky130_fd_sc_ls__dlrtn_1.lvs.report b/cells/dlrtn/sky130_fd_sc_ls__dlrtn_1.lvs.report
new file mode 100644
index 0000000..0b27587
--- /dev/null
+++ b/cells/dlrtn/sky130_fd_sc_ls__dlrtn_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__dlrtn_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__dlrtn_1.sp ('sky130_fd_sc_ls__dlrtn_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/dlrtn/sky130_fd_sc_ls__dlrtn_1.spice ('sky130_fd_sc_ls__dlrtn_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:03:35 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__dlrtn_1 sky130_fd_sc_ls__dlrtn_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__dlrtn_1
+SOURCE CELL NAME: sky130_fd_sc_ls__dlrtn_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 18 18
+
+ Instances: 10 10 MN (4 pins)
+ 10 10 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 21 20
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 13 13
+
+ Instances: 4 4 MN (4 pins)
+ 6 6 MP (4 pins)
+ 3 3 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 15 15
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 13 13 0 0
+
+ Instances: 4 4 0 0 MN(NSHORT)
+ 6 6 0 0 MP(PHIGHVT)
+ 3 3 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 15 15 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D GATE_N RESET_B VPWR Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dlrtn/sky130_fd_sc_ls__dlrtn_1.pex.spice b/cells/dlrtn/sky130_fd_sc_ls__dlrtn_1.pex.spice
index e545934..46da828 100644
--- a/cells/dlrtn/sky130_fd_sc_ls__dlrtn_1.pex.spice
+++ b/cells/dlrtn/sky130_fd_sc_ls__dlrtn_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dlrtn_1.pex.spice
-* Created: Fri Aug 28 13:18:28 2020
+* Created: Wed Sep 2 11:03:38 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dlrtn/sky130_fd_sc_ls__dlrtn_1.pxi.spice b/cells/dlrtn/sky130_fd_sc_ls__dlrtn_1.pxi.spice
index d306421..43ac944 100644
--- a/cells/dlrtn/sky130_fd_sc_ls__dlrtn_1.pxi.spice
+++ b/cells/dlrtn/sky130_fd_sc_ls__dlrtn_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dlrtn_1.pxi.spice
-* Created: Fri Aug 28 13:18:28 2020
+* Created: Wed Sep 2 11:03:38 2020
*
x_PM_SKY130_FD_SC_LS__DLRTN_1%D N_D_M1012_g N_D_c_126_n N_D_M1000_g D
+ PM_SKY130_FD_SC_LS__DLRTN_1%D
diff --git a/cells/dlrtn/sky130_fd_sc_ls__dlrtn_1.spice b/cells/dlrtn/sky130_fd_sc_ls__dlrtn_1.spice
index 7185c93..1e9bbe2 100644
--- a/cells/dlrtn/sky130_fd_sc_ls__dlrtn_1.spice
+++ b/cells/dlrtn/sky130_fd_sc_ls__dlrtn_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dlrtn_1.spice
-* Created: Fri Aug 28 13:18:28 2020
+* Created: Wed Sep 2 11:03:38 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dlrtn/sky130_fd_sc_ls__dlrtn_2.lvs.report b/cells/dlrtn/sky130_fd_sc_ls__dlrtn_2.lvs.report
new file mode 100644
index 0000000..6342325
--- /dev/null
+++ b/cells/dlrtn/sky130_fd_sc_ls__dlrtn_2.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__dlrtn_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__dlrtn_2.sp ('sky130_fd_sc_ls__dlrtn_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/dlrtn/sky130_fd_sc_ls__dlrtn_2.spice ('sky130_fd_sc_ls__dlrtn_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:03:42 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__dlrtn_2 sky130_fd_sc_ls__dlrtn_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__dlrtn_2
+SOURCE CELL NAME: sky130_fd_sc_ls__dlrtn_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 18 18
+
+ Instances: 11 11 MN (4 pins)
+ 11 11 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 23 22
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 13 13
+
+ Instances: 4 4 MN (4 pins)
+ 6 6 MP (4 pins)
+ 3 3 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 15 15
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 13 13 0 0
+
+ Instances: 4 4 0 0 MN(NSHORT)
+ 6 6 0 0 MP(PHIGHVT)
+ 3 3 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 15 15 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D GATE_N RESET_B VPWR Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dlrtn/sky130_fd_sc_ls__dlrtn_2.pex.spice b/cells/dlrtn/sky130_fd_sc_ls__dlrtn_2.pex.spice
index 75d8a4a..75d4d61 100644
--- a/cells/dlrtn/sky130_fd_sc_ls__dlrtn_2.pex.spice
+++ b/cells/dlrtn/sky130_fd_sc_ls__dlrtn_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dlrtn_2.pex.spice
-* Created: Fri Aug 28 13:18:42 2020
+* Created: Wed Sep 2 11:03:45 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dlrtn/sky130_fd_sc_ls__dlrtn_2.pxi.spice b/cells/dlrtn/sky130_fd_sc_ls__dlrtn_2.pxi.spice
index 331d4f5..29cc20d 100644
--- a/cells/dlrtn/sky130_fd_sc_ls__dlrtn_2.pxi.spice
+++ b/cells/dlrtn/sky130_fd_sc_ls__dlrtn_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dlrtn_2.pxi.spice
-* Created: Fri Aug 28 13:18:42 2020
+* Created: Wed Sep 2 11:03:45 2020
*
x_PM_SKY130_FD_SC_LS__DLRTN_2%D N_D_M1013_g N_D_c_142_n N_D_M1014_g D
+ PM_SKY130_FD_SC_LS__DLRTN_2%D
diff --git a/cells/dlrtn/sky130_fd_sc_ls__dlrtn_2.spice b/cells/dlrtn/sky130_fd_sc_ls__dlrtn_2.spice
index d1d3494..9444256 100644
--- a/cells/dlrtn/sky130_fd_sc_ls__dlrtn_2.spice
+++ b/cells/dlrtn/sky130_fd_sc_ls__dlrtn_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dlrtn_2.spice
-* Created: Fri Aug 28 13:18:42 2020
+* Created: Wed Sep 2 11:03:45 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dlrtn/sky130_fd_sc_ls__dlrtn_4.lvs.report b/cells/dlrtn/sky130_fd_sc_ls__dlrtn_4.lvs.report
new file mode 100644
index 0000000..106642d
--- /dev/null
+++ b/cells/dlrtn/sky130_fd_sc_ls__dlrtn_4.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__dlrtn_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__dlrtn_4.sp ('sky130_fd_sc_ls__dlrtn_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/dlrtn/sky130_fd_sc_ls__dlrtn_4.spice ('sky130_fd_sc_ls__dlrtn_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:03:48 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__dlrtn_4 sky130_fd_sc_ls__dlrtn_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__dlrtn_4
+SOURCE CELL NAME: sky130_fd_sc_ls__dlrtn_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 18 18
+
+ Instances: 15 15 MN (4 pins)
+ 15 15 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 31 30
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 13 13
+
+ Instances: 4 4 MN (4 pins)
+ 6 6 MP (4 pins)
+ 3 3 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 15 15
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 13 13 0 0
+
+ Instances: 4 4 0 0 MN(NSHORT)
+ 6 6 0 0 MP(PHIGHVT)
+ 3 3 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 15 15 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 16 layout mos transistors were reduced to 6.
+ 10 mos transistors were deleted by parallel reduction.
+ 16 source mos transistors were reduced to 6.
+ 10 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D GATE_N RESET_B VPWR Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dlrtn/sky130_fd_sc_ls__dlrtn_4.pex.spice b/cells/dlrtn/sky130_fd_sc_ls__dlrtn_4.pex.spice
index d89db5a..57757db 100644
--- a/cells/dlrtn/sky130_fd_sc_ls__dlrtn_4.pex.spice
+++ b/cells/dlrtn/sky130_fd_sc_ls__dlrtn_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dlrtn_4.pex.spice
-* Created: Fri Aug 28 13:19:01 2020
+* Created: Wed Sep 2 11:03:51 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dlrtn/sky130_fd_sc_ls__dlrtn_4.pxi.spice b/cells/dlrtn/sky130_fd_sc_ls__dlrtn_4.pxi.spice
index 9208156..4d527df 100644
--- a/cells/dlrtn/sky130_fd_sc_ls__dlrtn_4.pxi.spice
+++ b/cells/dlrtn/sky130_fd_sc_ls__dlrtn_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dlrtn_4.pxi.spice
-* Created: Fri Aug 28 13:19:01 2020
+* Created: Wed Sep 2 11:03:51 2020
*
x_PM_SKY130_FD_SC_LS__DLRTN_4%D N_D_M1025_g N_D_c_169_n N_D_M1014_g D
+ PM_SKY130_FD_SC_LS__DLRTN_4%D
diff --git a/cells/dlrtn/sky130_fd_sc_ls__dlrtn_4.spice b/cells/dlrtn/sky130_fd_sc_ls__dlrtn_4.spice
index 32856c7..9239ba7 100644
--- a/cells/dlrtn/sky130_fd_sc_ls__dlrtn_4.spice
+++ b/cells/dlrtn/sky130_fd_sc_ls__dlrtn_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dlrtn_4.spice
-* Created: Fri Aug 28 13:19:01 2020
+* Created: Wed Sep 2 11:03:51 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dlrtp/sky130_fd_sc_ls__dlrtp_1.lvs.report b/cells/dlrtp/sky130_fd_sc_ls__dlrtp_1.lvs.report
new file mode 100644
index 0000000..f8f3a60
--- /dev/null
+++ b/cells/dlrtp/sky130_fd_sc_ls__dlrtp_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__dlrtp_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__dlrtp_1.sp ('sky130_fd_sc_ls__dlrtp_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/dlrtp/sky130_fd_sc_ls__dlrtp_1.spice ('sky130_fd_sc_ls__dlrtp_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:03:55 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__dlrtp_1 sky130_fd_sc_ls__dlrtp_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__dlrtp_1
+SOURCE CELL NAME: sky130_fd_sc_ls__dlrtp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 18 18
+
+ Instances: 10 10 MN (4 pins)
+ 10 10 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 21 20
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 13 13
+
+ Instances: 4 4 MN (4 pins)
+ 6 6 MP (4 pins)
+ 3 3 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 15 15
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 13 13 0 0
+
+ Instances: 4 4 0 0 MN(NSHORT)
+ 6 6 0 0 MP(PHIGHVT)
+ 3 3 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 15 15 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D GATE RESET_B VPWR Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dlrtp/sky130_fd_sc_ls__dlrtp_1.pex.spice b/cells/dlrtp/sky130_fd_sc_ls__dlrtp_1.pex.spice
index e47473b..8bedc77 100644
--- a/cells/dlrtp/sky130_fd_sc_ls__dlrtp_1.pex.spice
+++ b/cells/dlrtp/sky130_fd_sc_ls__dlrtp_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dlrtp_1.pex.spice
-* Created: Fri Aug 28 13:19:09 2020
+* Created: Wed Sep 2 11:03:58 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dlrtp/sky130_fd_sc_ls__dlrtp_1.pxi.spice b/cells/dlrtp/sky130_fd_sc_ls__dlrtp_1.pxi.spice
index c9467b2..578a2cb 100644
--- a/cells/dlrtp/sky130_fd_sc_ls__dlrtp_1.pxi.spice
+++ b/cells/dlrtp/sky130_fd_sc_ls__dlrtp_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dlrtp_1.pxi.spice
-* Created: Fri Aug 28 13:19:09 2020
+* Created: Wed Sep 2 11:03:58 2020
*
x_PM_SKY130_FD_SC_LS__DLRTP_1%D N_D_c_137_n N_D_c_138_n N_D_M1011_g N_D_M1016_g
+ D N_D_c_135_n N_D_c_136_n PM_SKY130_FD_SC_LS__DLRTP_1%D
diff --git a/cells/dlrtp/sky130_fd_sc_ls__dlrtp_1.spice b/cells/dlrtp/sky130_fd_sc_ls__dlrtp_1.spice
index b803220..8fbad1f 100644
--- a/cells/dlrtp/sky130_fd_sc_ls__dlrtp_1.spice
+++ b/cells/dlrtp/sky130_fd_sc_ls__dlrtp_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dlrtp_1.spice
-* Created: Fri Aug 28 13:19:09 2020
+* Created: Wed Sep 2 11:03:58 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dlrtp/sky130_fd_sc_ls__dlrtp_2.lvs.report b/cells/dlrtp/sky130_fd_sc_ls__dlrtp_2.lvs.report
new file mode 100644
index 0000000..c8ca15c
--- /dev/null
+++ b/cells/dlrtp/sky130_fd_sc_ls__dlrtp_2.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__dlrtp_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__dlrtp_2.sp ('sky130_fd_sc_ls__dlrtp_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/dlrtp/sky130_fd_sc_ls__dlrtp_2.spice ('sky130_fd_sc_ls__dlrtp_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:04:02 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__dlrtp_2 sky130_fd_sc_ls__dlrtp_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__dlrtp_2
+SOURCE CELL NAME: sky130_fd_sc_ls__dlrtp_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 18 18
+
+ Instances: 11 11 MN (4 pins)
+ 11 11 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 23 22
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 13 13
+
+ Instances: 4 4 MN (4 pins)
+ 6 6 MP (4 pins)
+ 3 3 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 15 15
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 13 13 0 0
+
+ Instances: 4 4 0 0 MN(NSHORT)
+ 6 6 0 0 MP(PHIGHVT)
+ 3 3 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 15 15 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D GATE RESET_B VPWR Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dlrtp/sky130_fd_sc_ls__dlrtp_2.pex.spice b/cells/dlrtp/sky130_fd_sc_ls__dlrtp_2.pex.spice
index 40e2bf4..ba862bf 100644
--- a/cells/dlrtp/sky130_fd_sc_ls__dlrtp_2.pex.spice
+++ b/cells/dlrtp/sky130_fd_sc_ls__dlrtp_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dlrtp_2.pex.spice
-* Created: Fri Aug 28 13:19:17 2020
+* Created: Wed Sep 2 11:04:05 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dlrtp/sky130_fd_sc_ls__dlrtp_2.pxi.spice b/cells/dlrtp/sky130_fd_sc_ls__dlrtp_2.pxi.spice
index 27161d0..b0b0d77 100644
--- a/cells/dlrtp/sky130_fd_sc_ls__dlrtp_2.pxi.spice
+++ b/cells/dlrtp/sky130_fd_sc_ls__dlrtp_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dlrtp_2.pxi.spice
-* Created: Fri Aug 28 13:19:17 2020
+* Created: Wed Sep 2 11:04:05 2020
*
x_PM_SKY130_FD_SC_LS__DLRTP_2%D N_D_c_139_n N_D_M1012_g N_D_M1006_g D
+ N_D_c_141_n PM_SKY130_FD_SC_LS__DLRTP_2%D
diff --git a/cells/dlrtp/sky130_fd_sc_ls__dlrtp_2.spice b/cells/dlrtp/sky130_fd_sc_ls__dlrtp_2.spice
index f563c5a..15f58da 100644
--- a/cells/dlrtp/sky130_fd_sc_ls__dlrtp_2.spice
+++ b/cells/dlrtp/sky130_fd_sc_ls__dlrtp_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dlrtp_2.spice
-* Created: Fri Aug 28 13:19:17 2020
+* Created: Wed Sep 2 11:04:05 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dlrtp/sky130_fd_sc_ls__dlrtp_4.lvs.report b/cells/dlrtp/sky130_fd_sc_ls__dlrtp_4.lvs.report
new file mode 100644
index 0000000..950d820
--- /dev/null
+++ b/cells/dlrtp/sky130_fd_sc_ls__dlrtp_4.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__dlrtp_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__dlrtp_4.sp ('sky130_fd_sc_ls__dlrtp_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/dlrtp/sky130_fd_sc_ls__dlrtp_4.spice ('sky130_fd_sc_ls__dlrtp_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:04:08 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__dlrtp_4 sky130_fd_sc_ls__dlrtp_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__dlrtp_4
+SOURCE CELL NAME: sky130_fd_sc_ls__dlrtp_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 18 18
+
+ Instances: 15 15 MN (4 pins)
+ 15 15 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 31 30
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 13 13
+
+ Instances: 4 4 MN (4 pins)
+ 6 6 MP (4 pins)
+ 3 3 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 15 15
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 13 13 0 0
+
+ Instances: 4 4 0 0 MN(NSHORT)
+ 6 6 0 0 MP(PHIGHVT)
+ 3 3 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 15 15 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 16 layout mos transistors were reduced to 6.
+ 10 mos transistors were deleted by parallel reduction.
+ 16 source mos transistors were reduced to 6.
+ 10 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D GATE RESET_B VPWR Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dlrtp/sky130_fd_sc_ls__dlrtp_4.pex.spice b/cells/dlrtp/sky130_fd_sc_ls__dlrtp_4.pex.spice
index 5ae3618..798c003 100644
--- a/cells/dlrtp/sky130_fd_sc_ls__dlrtp_4.pex.spice
+++ b/cells/dlrtp/sky130_fd_sc_ls__dlrtp_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dlrtp_4.pex.spice
-* Created: Fri Aug 28 13:19:26 2020
+* Created: Wed Sep 2 11:04:11 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dlrtp/sky130_fd_sc_ls__dlrtp_4.pxi.spice b/cells/dlrtp/sky130_fd_sc_ls__dlrtp_4.pxi.spice
index 217c8a0..0e2a63a 100644
--- a/cells/dlrtp/sky130_fd_sc_ls__dlrtp_4.pxi.spice
+++ b/cells/dlrtp/sky130_fd_sc_ls__dlrtp_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dlrtp_4.pxi.spice
-* Created: Fri Aug 28 13:19:26 2020
+* Created: Wed Sep 2 11:04:11 2020
*
x_PM_SKY130_FD_SC_LS__DLRTP_4%D N_D_M1014_g N_D_c_179_n N_D_M1004_g D
+ N_D_c_180_n PM_SKY130_FD_SC_LS__DLRTP_4%D
diff --git a/cells/dlrtp/sky130_fd_sc_ls__dlrtp_4.spice b/cells/dlrtp/sky130_fd_sc_ls__dlrtp_4.spice
index e5b5131..eb2471e 100644
--- a/cells/dlrtp/sky130_fd_sc_ls__dlrtp_4.spice
+++ b/cells/dlrtp/sky130_fd_sc_ls__dlrtp_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dlrtp_4.spice
-* Created: Fri Aug 28 13:19:26 2020
+* Created: Wed Sep 2 11:04:11 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dlxbn/sky130_fd_sc_ls__dlxbn_1.lvs.report b/cells/dlxbn/sky130_fd_sc_ls__dlxbn_1.lvs.report
new file mode 100644
index 0000000..b7f2835
--- /dev/null
+++ b/cells/dlxbn/sky130_fd_sc_ls__dlxbn_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__dlxbn_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__dlxbn_1.sp ('sky130_fd_sc_ls__dlxbn_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/dlxbn/sky130_fd_sc_ls__dlxbn_1.spice ('sky130_fd_sc_ls__dlxbn_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:04:15 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__dlxbn_1 sky130_fd_sc_ls__dlxbn_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__dlxbn_1
+SOURCE CELL NAME: sky130_fd_sc_ls__dlxbn_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 18 18
+
+ Instances: 11 11 MN (4 pins)
+ 11 11 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 23 22
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 14 14
+
+ Instances: 7 7 MN (4 pins)
+ 7 7 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 18 18
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 14 14 0 0
+
+ Instances: 7 7 0 0 MN(NSHORT)
+ 7 7 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 18 18 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D GATE_N VPWR Q Q_N VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dlxbn/sky130_fd_sc_ls__dlxbn_1.pex.spice b/cells/dlxbn/sky130_fd_sc_ls__dlxbn_1.pex.spice
index f88510c..cd3f29b 100644
--- a/cells/dlxbn/sky130_fd_sc_ls__dlxbn_1.pex.spice
+++ b/cells/dlxbn/sky130_fd_sc_ls__dlxbn_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dlxbn_1.pex.spice
-* Created: Fri Aug 28 13:19:34 2020
+* Created: Wed Sep 2 11:04:18 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dlxbn/sky130_fd_sc_ls__dlxbn_1.pxi.spice b/cells/dlxbn/sky130_fd_sc_ls__dlxbn_1.pxi.spice
index bbab71f..45b0d6f 100644
--- a/cells/dlxbn/sky130_fd_sc_ls__dlxbn_1.pxi.spice
+++ b/cells/dlxbn/sky130_fd_sc_ls__dlxbn_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dlxbn_1.pxi.spice
-* Created: Fri Aug 28 13:19:34 2020
+* Created: Wed Sep 2 11:04:18 2020
*
x_PM_SKY130_FD_SC_LS__DLXBN_1%D N_D_M1017_g N_D_c_139_n N_D_c_144_n N_D_M1006_g
+ D N_D_c_141_n N_D_c_142_n PM_SKY130_FD_SC_LS__DLXBN_1%D
diff --git a/cells/dlxbn/sky130_fd_sc_ls__dlxbn_1.spice b/cells/dlxbn/sky130_fd_sc_ls__dlxbn_1.spice
index 7cb06d5..74a0b0f 100644
--- a/cells/dlxbn/sky130_fd_sc_ls__dlxbn_1.spice
+++ b/cells/dlxbn/sky130_fd_sc_ls__dlxbn_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dlxbn_1.spice
-* Created: Fri Aug 28 13:19:34 2020
+* Created: Wed Sep 2 11:04:18 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dlxbn/sky130_fd_sc_ls__dlxbn_2.lvs.report b/cells/dlxbn/sky130_fd_sc_ls__dlxbn_2.lvs.report
new file mode 100644
index 0000000..6304a1d
--- /dev/null
+++ b/cells/dlxbn/sky130_fd_sc_ls__dlxbn_2.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__dlxbn_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__dlxbn_2.sp ('sky130_fd_sc_ls__dlxbn_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/dlxbn/sky130_fd_sc_ls__dlxbn_2.spice ('sky130_fd_sc_ls__dlxbn_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:04:22 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__dlxbn_2 sky130_fd_sc_ls__dlxbn_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__dlxbn_2
+SOURCE CELL NAME: sky130_fd_sc_ls__dlxbn_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 18 18
+
+ Instances: 13 13 MN (4 pins)
+ 13 13 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 27 26
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 14 14
+
+ Instances: 7 7 MN (4 pins)
+ 7 7 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 18 18
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 14 14 0 0
+
+ Instances: 7 7 0 0 MN(NSHORT)
+ 7 7 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 18 18 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 8 layout mos transistors were reduced to 4.
+ 4 mos transistors were deleted by parallel reduction.
+ 8 source mos transistors were reduced to 4.
+ 4 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D GATE_N VPWR Q Q_N VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dlxbn/sky130_fd_sc_ls__dlxbn_2.pex.spice b/cells/dlxbn/sky130_fd_sc_ls__dlxbn_2.pex.spice
index 3b86227..2b2602c 100644
--- a/cells/dlxbn/sky130_fd_sc_ls__dlxbn_2.pex.spice
+++ b/cells/dlxbn/sky130_fd_sc_ls__dlxbn_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dlxbn_2.pex.spice
-* Created: Fri Aug 28 13:19:49 2020
+* Created: Wed Sep 2 11:04:25 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dlxbn/sky130_fd_sc_ls__dlxbn_2.pxi.spice b/cells/dlxbn/sky130_fd_sc_ls__dlxbn_2.pxi.spice
index 127fa29..442ae06 100644
--- a/cells/dlxbn/sky130_fd_sc_ls__dlxbn_2.pxi.spice
+++ b/cells/dlxbn/sky130_fd_sc_ls__dlxbn_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dlxbn_2.pxi.spice
-* Created: Fri Aug 28 13:19:49 2020
+* Created: Wed Sep 2 11:04:25 2020
*
x_PM_SKY130_FD_SC_LS__DLXBN_2%D N_D_M1021_g N_D_c_167_n N_D_c_168_n N_D_M1000_g
+ D N_D_c_166_n PM_SKY130_FD_SC_LS__DLXBN_2%D
diff --git a/cells/dlxbn/sky130_fd_sc_ls__dlxbn_2.spice b/cells/dlxbn/sky130_fd_sc_ls__dlxbn_2.spice
index 29ddd19..79e2f6d 100644
--- a/cells/dlxbn/sky130_fd_sc_ls__dlxbn_2.spice
+++ b/cells/dlxbn/sky130_fd_sc_ls__dlxbn_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dlxbn_2.spice
-* Created: Fri Aug 28 13:19:49 2020
+* Created: Wed Sep 2 11:04:25 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dlxbp/sky130_fd_sc_ls__dlxbp_1.lvs.report b/cells/dlxbp/sky130_fd_sc_ls__dlxbp_1.lvs.report
new file mode 100644
index 0000000..9261c53
--- /dev/null
+++ b/cells/dlxbp/sky130_fd_sc_ls__dlxbp_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__dlxbp_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__dlxbp_1.sp ('sky130_fd_sc_ls__dlxbp_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/dlxbp/sky130_fd_sc_ls__dlxbp_1.spice ('sky130_fd_sc_ls__dlxbp_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:04:29 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__dlxbp_1 sky130_fd_sc_ls__dlxbp_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__dlxbp_1
+SOURCE CELL NAME: sky130_fd_sc_ls__dlxbp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 18 18
+
+ Instances: 11 11 MN (4 pins)
+ 11 11 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 23 22
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 14 14
+
+ Instances: 7 7 MN (4 pins)
+ 7 7 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 18 18
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 14 14 0 0
+
+ Instances: 7 7 0 0 MN(NSHORT)
+ 7 7 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 18 18 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D GATE VPWR Q Q_N VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dlxbp/sky130_fd_sc_ls__dlxbp_1.pex.spice b/cells/dlxbp/sky130_fd_sc_ls__dlxbp_1.pex.spice
index 8ae6f28..bb23386 100644
--- a/cells/dlxbp/sky130_fd_sc_ls__dlxbp_1.pex.spice
+++ b/cells/dlxbp/sky130_fd_sc_ls__dlxbp_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dlxbp_1.pex.spice
-* Created: Fri Aug 28 13:20:08 2020
+* Created: Wed Sep 2 11:04:33 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dlxbp/sky130_fd_sc_ls__dlxbp_1.pxi.spice b/cells/dlxbp/sky130_fd_sc_ls__dlxbp_1.pxi.spice
index 4203ca5..657bdae 100644
--- a/cells/dlxbp/sky130_fd_sc_ls__dlxbp_1.pxi.spice
+++ b/cells/dlxbp/sky130_fd_sc_ls__dlxbp_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dlxbp_1.pxi.spice
-* Created: Fri Aug 28 13:20:08 2020
+* Created: Wed Sep 2 11:04:33 2020
*
x_PM_SKY130_FD_SC_LS__DLXBP_1%D N_D_c_143_n N_D_M1003_g N_D_c_148_n N_D_M1017_g
+ D N_D_c_145_n N_D_c_146_n PM_SKY130_FD_SC_LS__DLXBP_1%D
diff --git a/cells/dlxbp/sky130_fd_sc_ls__dlxbp_1.spice b/cells/dlxbp/sky130_fd_sc_ls__dlxbp_1.spice
index e50646d..1971032 100644
--- a/cells/dlxbp/sky130_fd_sc_ls__dlxbp_1.spice
+++ b/cells/dlxbp/sky130_fd_sc_ls__dlxbp_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dlxbp_1.spice
-* Created: Fri Aug 28 13:20:08 2020
+* Created: Wed Sep 2 11:04:33 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dlxtn/sky130_fd_sc_ls__dlxtn_1.lvs.report b/cells/dlxtn/sky130_fd_sc_ls__dlxtn_1.lvs.report
new file mode 100644
index 0000000..f79cba0
--- /dev/null
+++ b/cells/dlxtn/sky130_fd_sc_ls__dlxtn_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__dlxtn_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__dlxtn_1.sp ('sky130_fd_sc_ls__dlxtn_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/dlxtn/sky130_fd_sc_ls__dlxtn_1.spice ('sky130_fd_sc_ls__dlxtn_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:04:37 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__dlxtn_1 sky130_fd_sc_ls__dlxtn_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__dlxtn_1
+SOURCE CELL NAME: sky130_fd_sc_ls__dlxtn_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 16 16
+
+ Instances: 9 9 MN (4 pins)
+ 9 9 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 19 18
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 12 12
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 14 14
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 12 12 0 0
+
+ Instances: 5 5 0 0 MN(NSHORT)
+ 5 5 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 14 14 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D GATE_N VPWR Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dlxtn/sky130_fd_sc_ls__dlxtn_1.pex.spice b/cells/dlxtn/sky130_fd_sc_ls__dlxtn_1.pex.spice
index ef242ec..079154d 100644
--- a/cells/dlxtn/sky130_fd_sc_ls__dlxtn_1.pex.spice
+++ b/cells/dlxtn/sky130_fd_sc_ls__dlxtn_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dlxtn_1.pex.spice
-* Created: Fri Aug 28 13:20:16 2020
+* Created: Wed Sep 2 11:04:40 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dlxtn/sky130_fd_sc_ls__dlxtn_1.pxi.spice b/cells/dlxtn/sky130_fd_sc_ls__dlxtn_1.pxi.spice
index 5ff2fb6..9fca88c 100644
--- a/cells/dlxtn/sky130_fd_sc_ls__dlxtn_1.pxi.spice
+++ b/cells/dlxtn/sky130_fd_sc_ls__dlxtn_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dlxtn_1.pxi.spice
-* Created: Fri Aug 28 13:20:16 2020
+* Created: Wed Sep 2 11:04:40 2020
*
x_PM_SKY130_FD_SC_LS__DLXTN_1%D N_D_c_127_n N_D_M1004_g N_D_c_128_n N_D_c_132_n
+ N_D_M1010_g D N_D_c_130_n PM_SKY130_FD_SC_LS__DLXTN_1%D
diff --git a/cells/dlxtn/sky130_fd_sc_ls__dlxtn_1.spice b/cells/dlxtn/sky130_fd_sc_ls__dlxtn_1.spice
index f5f59b6..8255b53 100644
--- a/cells/dlxtn/sky130_fd_sc_ls__dlxtn_1.spice
+++ b/cells/dlxtn/sky130_fd_sc_ls__dlxtn_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dlxtn_1.spice
-* Created: Fri Aug 28 13:20:16 2020
+* Created: Wed Sep 2 11:04:40 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dlxtn/sky130_fd_sc_ls__dlxtn_2.lvs.report b/cells/dlxtn/sky130_fd_sc_ls__dlxtn_2.lvs.report
new file mode 100644
index 0000000..93f5a85
--- /dev/null
+++ b/cells/dlxtn/sky130_fd_sc_ls__dlxtn_2.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__dlxtn_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__dlxtn_2.sp ('sky130_fd_sc_ls__dlxtn_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/dlxtn/sky130_fd_sc_ls__dlxtn_2.spice ('sky130_fd_sc_ls__dlxtn_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:04:44 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__dlxtn_2 sky130_fd_sc_ls__dlxtn_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__dlxtn_2
+SOURCE CELL NAME: sky130_fd_sc_ls__dlxtn_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 16 16
+
+ Instances: 10 10 MN (4 pins)
+ 10 10 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 21 20
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 12 12
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 14 14
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 12 12 0 0
+
+ Instances: 5 5 0 0 MN(NSHORT)
+ 5 5 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 14 14 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D GATE_N VPWR Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dlxtn/sky130_fd_sc_ls__dlxtn_2.pex.spice b/cells/dlxtn/sky130_fd_sc_ls__dlxtn_2.pex.spice
index b8f101e..f8b68f3 100644
--- a/cells/dlxtn/sky130_fd_sc_ls__dlxtn_2.pex.spice
+++ b/cells/dlxtn/sky130_fd_sc_ls__dlxtn_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dlxtn_2.pex.spice
-* Created: Fri Aug 28 13:20:25 2020
+* Created: Wed Sep 2 11:04:47 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dlxtn/sky130_fd_sc_ls__dlxtn_2.pxi.spice b/cells/dlxtn/sky130_fd_sc_ls__dlxtn_2.pxi.spice
index 83ccb7b..5ab38be 100644
--- a/cells/dlxtn/sky130_fd_sc_ls__dlxtn_2.pxi.spice
+++ b/cells/dlxtn/sky130_fd_sc_ls__dlxtn_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dlxtn_2.pxi.spice
-* Created: Fri Aug 28 13:20:25 2020
+* Created: Wed Sep 2 11:04:47 2020
*
x_PM_SKY130_FD_SC_LS__DLXTN_2%D N_D_M1014_g N_D_c_136_n N_D_c_140_n N_D_M1013_g
+ D N_D_c_137_n N_D_c_138_n PM_SKY130_FD_SC_LS__DLXTN_2%D
diff --git a/cells/dlxtn/sky130_fd_sc_ls__dlxtn_2.spice b/cells/dlxtn/sky130_fd_sc_ls__dlxtn_2.spice
index 0ec6097..93d47fb 100644
--- a/cells/dlxtn/sky130_fd_sc_ls__dlxtn_2.spice
+++ b/cells/dlxtn/sky130_fd_sc_ls__dlxtn_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dlxtn_2.spice
-* Created: Fri Aug 28 13:20:25 2020
+* Created: Wed Sep 2 11:04:47 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dlxtn/sky130_fd_sc_ls__dlxtn_4.lvs.report b/cells/dlxtn/sky130_fd_sc_ls__dlxtn_4.lvs.report
new file mode 100644
index 0000000..d0fde0f
--- /dev/null
+++ b/cells/dlxtn/sky130_fd_sc_ls__dlxtn_4.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__dlxtn_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__dlxtn_4.sp ('sky130_fd_sc_ls__dlxtn_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/dlxtn/sky130_fd_sc_ls__dlxtn_4.spice ('sky130_fd_sc_ls__dlxtn_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:04:51 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__dlxtn_4 sky130_fd_sc_ls__dlxtn_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__dlxtn_4
+SOURCE CELL NAME: sky130_fd_sc_ls__dlxtn_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 16 16
+
+ Instances: 13 13 MN (4 pins)
+ 13 13 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 27 26
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 12 12
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 14 14
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 12 12 0 0
+
+ Instances: 5 5 0 0 MN(NSHORT)
+ 5 5 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 14 14 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 12 layout mos transistors were reduced to 4.
+ 8 mos transistors were deleted by parallel reduction.
+ 12 source mos transistors were reduced to 4.
+ 8 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D GATE_N VPWR Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dlxtn/sky130_fd_sc_ls__dlxtn_4.pex.spice b/cells/dlxtn/sky130_fd_sc_ls__dlxtn_4.pex.spice
index dc7e3c9..8cddabe 100644
--- a/cells/dlxtn/sky130_fd_sc_ls__dlxtn_4.pex.spice
+++ b/cells/dlxtn/sky130_fd_sc_ls__dlxtn_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dlxtn_4.pex.spice
-* Created: Fri Aug 28 13:20:34 2020
+* Created: Wed Sep 2 11:04:54 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dlxtn/sky130_fd_sc_ls__dlxtn_4.pxi.spice b/cells/dlxtn/sky130_fd_sc_ls__dlxtn_4.pxi.spice
index 9d151f9..83d7667 100644
--- a/cells/dlxtn/sky130_fd_sc_ls__dlxtn_4.pxi.spice
+++ b/cells/dlxtn/sky130_fd_sc_ls__dlxtn_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dlxtn_4.pxi.spice
-* Created: Fri Aug 28 13:20:34 2020
+* Created: Wed Sep 2 11:04:54 2020
*
x_PM_SKY130_FD_SC_LS__DLXTN_4%D N_D_M1014_g N_D_c_157_n N_D_c_161_n N_D_M1004_g
+ D N_D_c_158_n N_D_c_159_n PM_SKY130_FD_SC_LS__DLXTN_4%D
diff --git a/cells/dlxtn/sky130_fd_sc_ls__dlxtn_4.spice b/cells/dlxtn/sky130_fd_sc_ls__dlxtn_4.spice
index fb393df..4db0e91 100644
--- a/cells/dlxtn/sky130_fd_sc_ls__dlxtn_4.spice
+++ b/cells/dlxtn/sky130_fd_sc_ls__dlxtn_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dlxtn_4.spice
-* Created: Fri Aug 28 13:20:34 2020
+* Created: Wed Sep 2 11:04:54 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dlxtp/sky130_fd_sc_ls__dlxtp_1.lvs.report b/cells/dlxtp/sky130_fd_sc_ls__dlxtp_1.lvs.report
new file mode 100644
index 0000000..9e434d5
--- /dev/null
+++ b/cells/dlxtp/sky130_fd_sc_ls__dlxtp_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__dlxtp_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__dlxtp_1.sp ('sky130_fd_sc_ls__dlxtp_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/dlxtp/sky130_fd_sc_ls__dlxtp_1.spice ('sky130_fd_sc_ls__dlxtp_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:04:58 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__dlxtp_1 sky130_fd_sc_ls__dlxtp_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__dlxtp_1
+SOURCE CELL NAME: sky130_fd_sc_ls__dlxtp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 16 16
+
+ Instances: 9 9 MN (4 pins)
+ 9 9 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 19 18
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 12 12
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 14 14
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 12 12 0 0
+
+ Instances: 5 5 0 0 MN(NSHORT)
+ 5 5 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 14 14 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D GATE VPWR Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dlxtp/sky130_fd_sc_ls__dlxtp_1.pex.spice b/cells/dlxtp/sky130_fd_sc_ls__dlxtp_1.pex.spice
index 84dd50d..f438109 100644
--- a/cells/dlxtp/sky130_fd_sc_ls__dlxtp_1.pex.spice
+++ b/cells/dlxtp/sky130_fd_sc_ls__dlxtp_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dlxtp_1.pex.spice
-* Created: Fri Aug 28 13:20:42 2020
+* Created: Wed Sep 2 11:05:02 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dlxtp/sky130_fd_sc_ls__dlxtp_1.pxi.spice b/cells/dlxtp/sky130_fd_sc_ls__dlxtp_1.pxi.spice
index 254adcc..9cf89cc 100644
--- a/cells/dlxtp/sky130_fd_sc_ls__dlxtp_1.pxi.spice
+++ b/cells/dlxtp/sky130_fd_sc_ls__dlxtp_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dlxtp_1.pxi.spice
-* Created: Fri Aug 28 13:20:42 2020
+* Created: Wed Sep 2 11:05:02 2020
*
x_PM_SKY130_FD_SC_LS__DLXTP_1%D N_D_c_150_n N_D_M1009_g N_D_M1006_g N_D_c_147_n
+ D D N_D_c_149_n PM_SKY130_FD_SC_LS__DLXTP_1%D
diff --git a/cells/dlxtp/sky130_fd_sc_ls__dlxtp_1.spice b/cells/dlxtp/sky130_fd_sc_ls__dlxtp_1.spice
index 2dd50af..a3e55a6 100644
--- a/cells/dlxtp/sky130_fd_sc_ls__dlxtp_1.spice
+++ b/cells/dlxtp/sky130_fd_sc_ls__dlxtp_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dlxtp_1.spice
-* Created: Fri Aug 28 13:20:42 2020
+* Created: Wed Sep 2 11:05:02 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dlygate4sd1/sky130_fd_sc_ls__dlygate4sd1_1.lvs.report b/cells/dlygate4sd1/sky130_fd_sc_ls__dlygate4sd1_1.lvs.report
new file mode 100644
index 0000000..f842095
--- /dev/null
+++ b/cells/dlygate4sd1/sky130_fd_sc_ls__dlygate4sd1_1.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__dlygate4sd1_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__dlygate4sd1_1.sp ('sky130_fd_sc_ls__dlygate4sd1_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/dlygate4sd1/sky130_fd_sc_ls__dlygate4sd1_1.spice ('sky130_fd_sc_ls__dlygate4sd1_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:05:06 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__dlygate4sd1_1 sky130_fd_sc_ls__dlygate4sd1_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__dlygate4sd1_1
+SOURCE CELL NAME: sky130_fd_sc_ls__dlygate4sd1_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 9 9
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 9 9
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ ------ ------
+ Total Inst: 8 8
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 4 4 0 0 MN(NSHORT)
+ 4 4 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 8 8 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dlygate4sd1/sky130_fd_sc_ls__dlygate4sd1_1.pex.spice b/cells/dlygate4sd1/sky130_fd_sc_ls__dlygate4sd1_1.pex.spice
index 8123491..9dc6a60 100644
--- a/cells/dlygate4sd1/sky130_fd_sc_ls__dlygate4sd1_1.pex.spice
+++ b/cells/dlygate4sd1/sky130_fd_sc_ls__dlygate4sd1_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dlygate4sd1_1.pex.spice
-* Created: Fri Aug 28 13:20:57 2020
+* Created: Wed Sep 2 11:05:09 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dlygate4sd1/sky130_fd_sc_ls__dlygate4sd1_1.pxi.spice b/cells/dlygate4sd1/sky130_fd_sc_ls__dlygate4sd1_1.pxi.spice
index 8b81aec..31a4adc 100644
--- a/cells/dlygate4sd1/sky130_fd_sc_ls__dlygate4sd1_1.pxi.spice
+++ b/cells/dlygate4sd1/sky130_fd_sc_ls__dlygate4sd1_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dlygate4sd1_1.pxi.spice
-* Created: Fri Aug 28 13:20:57 2020
+* Created: Wed Sep 2 11:05:09 2020
*
x_PM_SKY130_FD_SC_LS__DLYGATE4SD1_1%A N_A_M1005_g N_A_c_64_n N_A_c_68_n
+ N_A_M1002_g A A N_A_c_66_n PM_SKY130_FD_SC_LS__DLYGATE4SD1_1%A
diff --git a/cells/dlygate4sd1/sky130_fd_sc_ls__dlygate4sd1_1.spice b/cells/dlygate4sd1/sky130_fd_sc_ls__dlygate4sd1_1.spice
index a8b9343..a505153 100644
--- a/cells/dlygate4sd1/sky130_fd_sc_ls__dlygate4sd1_1.spice
+++ b/cells/dlygate4sd1/sky130_fd_sc_ls__dlygate4sd1_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dlygate4sd1_1.spice
-* Created: Fri Aug 28 13:20:57 2020
+* Created: Wed Sep 2 11:05:09 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dlygate4sd2/sky130_fd_sc_ls__dlygate4sd2_1.lvs.report b/cells/dlygate4sd2/sky130_fd_sc_ls__dlygate4sd2_1.lvs.report
new file mode 100644
index 0000000..a56932c
--- /dev/null
+++ b/cells/dlygate4sd2/sky130_fd_sc_ls__dlygate4sd2_1.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__dlygate4sd2_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__dlygate4sd2_1.sp ('sky130_fd_sc_ls__dlygate4sd2_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/dlygate4sd2/sky130_fd_sc_ls__dlygate4sd2_1.spice ('sky130_fd_sc_ls__dlygate4sd2_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:05:13 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__dlygate4sd2_1 sky130_fd_sc_ls__dlygate4sd2_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__dlygate4sd2_1
+SOURCE CELL NAME: sky130_fd_sc_ls__dlygate4sd2_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 9 9
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 9 9
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ ------ ------
+ Total Inst: 8 8
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 4 4 0 0 MN(NSHORT)
+ 4 4 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 8 8 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dlygate4sd2/sky130_fd_sc_ls__dlygate4sd2_1.pex.spice b/cells/dlygate4sd2/sky130_fd_sc_ls__dlygate4sd2_1.pex.spice
index 5fd461b..6fd42b2 100644
--- a/cells/dlygate4sd2/sky130_fd_sc_ls__dlygate4sd2_1.pex.spice
+++ b/cells/dlygate4sd2/sky130_fd_sc_ls__dlygate4sd2_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dlygate4sd2_1.pex.spice
-* Created: Fri Aug 28 13:21:17 2020
+* Created: Wed Sep 2 11:05:16 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dlygate4sd2/sky130_fd_sc_ls__dlygate4sd2_1.pxi.spice b/cells/dlygate4sd2/sky130_fd_sc_ls__dlygate4sd2_1.pxi.spice
index 7df9aa5..be816cd 100644
--- a/cells/dlygate4sd2/sky130_fd_sc_ls__dlygate4sd2_1.pxi.spice
+++ b/cells/dlygate4sd2/sky130_fd_sc_ls__dlygate4sd2_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dlygate4sd2_1.pxi.spice
-* Created: Fri Aug 28 13:21:17 2020
+* Created: Wed Sep 2 11:05:16 2020
*
x_PM_SKY130_FD_SC_LS__DLYGATE4SD2_1%A N_A_M1004_g N_A_c_65_n N_A_c_69_n
+ N_A_M1000_g A A N_A_c_67_n PM_SKY130_FD_SC_LS__DLYGATE4SD2_1%A
diff --git a/cells/dlygate4sd2/sky130_fd_sc_ls__dlygate4sd2_1.spice b/cells/dlygate4sd2/sky130_fd_sc_ls__dlygate4sd2_1.spice
index b8f41f7..061aff7 100644
--- a/cells/dlygate4sd2/sky130_fd_sc_ls__dlygate4sd2_1.spice
+++ b/cells/dlygate4sd2/sky130_fd_sc_ls__dlygate4sd2_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dlygate4sd2_1.spice
-* Created: Fri Aug 28 13:21:17 2020
+* Created: Wed Sep 2 11:05:16 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dlygate4sd3/sky130_fd_sc_ls__dlygate4sd3_1.lvs.report b/cells/dlygate4sd3/sky130_fd_sc_ls__dlygate4sd3_1.lvs.report
new file mode 100644
index 0000000..348f443
--- /dev/null
+++ b/cells/dlygate4sd3/sky130_fd_sc_ls__dlygate4sd3_1.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__dlygate4sd3_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__dlygate4sd3_1.sp ('sky130_fd_sc_ls__dlygate4sd3_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/dlygate4sd3/sky130_fd_sc_ls__dlygate4sd3_1.spice ('sky130_fd_sc_ls__dlygate4sd3_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:05:20 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__dlygate4sd3_1 sky130_fd_sc_ls__dlygate4sd3_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__dlygate4sd3_1
+SOURCE CELL NAME: sky130_fd_sc_ls__dlygate4sd3_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 9 9
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 9 9
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ ------ ------
+ Total Inst: 8 8
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 4 4 0 0 MN(NSHORT)
+ 4 4 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 8 8 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dlygate4sd3/sky130_fd_sc_ls__dlygate4sd3_1.pex.spice b/cells/dlygate4sd3/sky130_fd_sc_ls__dlygate4sd3_1.pex.spice
index d9cb7d9..c14eb81 100644
--- a/cells/dlygate4sd3/sky130_fd_sc_ls__dlygate4sd3_1.pex.spice
+++ b/cells/dlygate4sd3/sky130_fd_sc_ls__dlygate4sd3_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dlygate4sd3_1.pex.spice
-* Created: Fri Aug 28 13:21:26 2020
+* Created: Wed Sep 2 11:05:23 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dlygate4sd3/sky130_fd_sc_ls__dlygate4sd3_1.pxi.spice b/cells/dlygate4sd3/sky130_fd_sc_ls__dlygate4sd3_1.pxi.spice
index cd6811e..547b76b 100644
--- a/cells/dlygate4sd3/sky130_fd_sc_ls__dlygate4sd3_1.pxi.spice
+++ b/cells/dlygate4sd3/sky130_fd_sc_ls__dlygate4sd3_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dlygate4sd3_1.pxi.spice
-* Created: Fri Aug 28 13:21:26 2020
+* Created: Wed Sep 2 11:05:23 2020
*
x_PM_SKY130_FD_SC_LS__DLYGATE4SD3_1%A N_A_M1005_g N_A_c_61_n N_A_c_65_n
+ N_A_M1002_g A A N_A_c_63_n PM_SKY130_FD_SC_LS__DLYGATE4SD3_1%A
diff --git a/cells/dlygate4sd3/sky130_fd_sc_ls__dlygate4sd3_1.spice b/cells/dlygate4sd3/sky130_fd_sc_ls__dlygate4sd3_1.spice
index bfeb26a..8e336d8 100644
--- a/cells/dlygate4sd3/sky130_fd_sc_ls__dlygate4sd3_1.spice
+++ b/cells/dlygate4sd3/sky130_fd_sc_ls__dlygate4sd3_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dlygate4sd3_1.spice
-* Created: Fri Aug 28 13:21:26 2020
+* Created: Wed Sep 2 11:05:23 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dlymetal6s2s/sky130_fd_sc_ls__dlymetal6s2s_1.lvs.report b/cells/dlymetal6s2s/sky130_fd_sc_ls__dlymetal6s2s_1.lvs.report
new file mode 100644
index 0000000..1861375
--- /dev/null
+++ b/cells/dlymetal6s2s/sky130_fd_sc_ls__dlymetal6s2s_1.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__dlymetal6s2s_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__dlymetal6s2s_1.sp ('sky130_fd_sc_ls__dlymetal6s2s_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/dlymetal6s2s/sky130_fd_sc_ls__dlymetal6s2s_1.spice ('sky130_fd_sc_ls__dlymetal6s2s_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:05:27 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__dlymetal6s2s_1 sky130_fd_sc_ls__dlymetal6s2s_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__dlymetal6s2s_1
+SOURCE CELL NAME: sky130_fd_sc_ls__dlymetal6s2s_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 11 11
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 11 11
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ ------ ------
+ Total Inst: 12 12
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 6 6 0 0 MN(NSHORT)
+ 6 6 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 12 12 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dlymetal6s2s/sky130_fd_sc_ls__dlymetal6s2s_1.pex.spice b/cells/dlymetal6s2s/sky130_fd_sc_ls__dlymetal6s2s_1.pex.spice
index 087c9c2..ae203d7 100644
--- a/cells/dlymetal6s2s/sky130_fd_sc_ls__dlymetal6s2s_1.pex.spice
+++ b/cells/dlymetal6s2s/sky130_fd_sc_ls__dlymetal6s2s_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dlymetal6s2s_1.pex.spice
-* Created: Fri Aug 28 13:21:34 2020
+* Created: Wed Sep 2 11:05:30 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dlymetal6s2s/sky130_fd_sc_ls__dlymetal6s2s_1.pxi.spice b/cells/dlymetal6s2s/sky130_fd_sc_ls__dlymetal6s2s_1.pxi.spice
index 447ef3b..4da1d0f 100644
--- a/cells/dlymetal6s2s/sky130_fd_sc_ls__dlymetal6s2s_1.pxi.spice
+++ b/cells/dlymetal6s2s/sky130_fd_sc_ls__dlymetal6s2s_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dlymetal6s2s_1.pxi.spice
-* Created: Fri Aug 28 13:21:34 2020
+* Created: Wed Sep 2 11:05:30 2020
*
x_PM_SKY130_FD_SC_LS__DLYMETAL6S2S_1%A N_A_M1004_g N_A_c_88_n N_A_M1011_g A
+ N_A_c_89_n PM_SKY130_FD_SC_LS__DLYMETAL6S2S_1%A
diff --git a/cells/dlymetal6s2s/sky130_fd_sc_ls__dlymetal6s2s_1.spice b/cells/dlymetal6s2s/sky130_fd_sc_ls__dlymetal6s2s_1.spice
index a1da75b..e08173f 100644
--- a/cells/dlymetal6s2s/sky130_fd_sc_ls__dlymetal6s2s_1.spice
+++ b/cells/dlymetal6s2s/sky130_fd_sc_ls__dlymetal6s2s_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dlymetal6s2s_1.spice
-* Created: Fri Aug 28 13:21:34 2020
+* Created: Wed Sep 2 11:05:30 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dlymetal6s4s/sky130_fd_sc_ls__dlymetal6s4s_1.lvs.report b/cells/dlymetal6s4s/sky130_fd_sc_ls__dlymetal6s4s_1.lvs.report
new file mode 100644
index 0000000..a4e9fa7
--- /dev/null
+++ b/cells/dlymetal6s4s/sky130_fd_sc_ls__dlymetal6s4s_1.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__dlymetal6s4s_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__dlymetal6s4s_1.sp ('sky130_fd_sc_ls__dlymetal6s4s_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/dlymetal6s4s/sky130_fd_sc_ls__dlymetal6s4s_1.spice ('sky130_fd_sc_ls__dlymetal6s4s_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:05:34 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__dlymetal6s4s_1 sky130_fd_sc_ls__dlymetal6s4s_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__dlymetal6s4s_1
+SOURCE CELL NAME: sky130_fd_sc_ls__dlymetal6s4s_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 11 11
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 11 11
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ ------ ------
+ Total Inst: 12 12
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 6 6 0 0 MN(NSHORT)
+ 6 6 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 12 12 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dlymetal6s4s/sky130_fd_sc_ls__dlymetal6s4s_1.pex.spice b/cells/dlymetal6s4s/sky130_fd_sc_ls__dlymetal6s4s_1.pex.spice
index 73b77b0..6761b72 100644
--- a/cells/dlymetal6s4s/sky130_fd_sc_ls__dlymetal6s4s_1.pex.spice
+++ b/cells/dlymetal6s4s/sky130_fd_sc_ls__dlymetal6s4s_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dlymetal6s4s_1.pex.spice
-* Created: Fri Aug 28 13:21:43 2020
+* Created: Wed Sep 2 11:05:38 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dlymetal6s4s/sky130_fd_sc_ls__dlymetal6s4s_1.pxi.spice b/cells/dlymetal6s4s/sky130_fd_sc_ls__dlymetal6s4s_1.pxi.spice
index 382c16e..ef24fe3 100644
--- a/cells/dlymetal6s4s/sky130_fd_sc_ls__dlymetal6s4s_1.pxi.spice
+++ b/cells/dlymetal6s4s/sky130_fd_sc_ls__dlymetal6s4s_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dlymetal6s4s_1.pxi.spice
-* Created: Fri Aug 28 13:21:43 2020
+* Created: Wed Sep 2 11:05:38 2020
*
x_PM_SKY130_FD_SC_LS__DLYMETAL6S4S_1%A N_A_M1004_g N_A_c_89_n N_A_M1011_g A
+ N_A_c_90_n PM_SKY130_FD_SC_LS__DLYMETAL6S4S_1%A
diff --git a/cells/dlymetal6s4s/sky130_fd_sc_ls__dlymetal6s4s_1.spice b/cells/dlymetal6s4s/sky130_fd_sc_ls__dlymetal6s4s_1.spice
index a674e96..dc49845 100644
--- a/cells/dlymetal6s4s/sky130_fd_sc_ls__dlymetal6s4s_1.spice
+++ b/cells/dlymetal6s4s/sky130_fd_sc_ls__dlymetal6s4s_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dlymetal6s4s_1.spice
-* Created: Fri Aug 28 13:21:43 2020
+* Created: Wed Sep 2 11:05:38 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dlymetal6s6s/sky130_fd_sc_ls__dlymetal6s6s_1.lvs.report b/cells/dlymetal6s6s/sky130_fd_sc_ls__dlymetal6s6s_1.lvs.report
new file mode 100644
index 0000000..fbcfa5f
--- /dev/null
+++ b/cells/dlymetal6s6s/sky130_fd_sc_ls__dlymetal6s6s_1.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__dlymetal6s6s_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__dlymetal6s6s_1.sp ('sky130_fd_sc_ls__dlymetal6s6s_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/dlymetal6s6s/sky130_fd_sc_ls__dlymetal6s6s_1.spice ('sky130_fd_sc_ls__dlymetal6s6s_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:05:42 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__dlymetal6s6s_1 sky130_fd_sc_ls__dlymetal6s6s_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__dlymetal6s6s_1
+SOURCE CELL NAME: sky130_fd_sc_ls__dlymetal6s6s_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 11 11
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 11 11
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ ------ ------
+ Total Inst: 12 12
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 6 6 0 0 MN(NSHORT)
+ 6 6 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 12 12 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dlymetal6s6s/sky130_fd_sc_ls__dlymetal6s6s_1.pex.spice b/cells/dlymetal6s6s/sky130_fd_sc_ls__dlymetal6s6s_1.pex.spice
index 551ae34..3f7a025 100644
--- a/cells/dlymetal6s6s/sky130_fd_sc_ls__dlymetal6s6s_1.pex.spice
+++ b/cells/dlymetal6s6s/sky130_fd_sc_ls__dlymetal6s6s_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dlymetal6s6s_1.pex.spice
-* Created: Fri Aug 28 13:21:58 2020
+* Created: Wed Sep 2 11:05:45 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dlymetal6s6s/sky130_fd_sc_ls__dlymetal6s6s_1.pxi.spice b/cells/dlymetal6s6s/sky130_fd_sc_ls__dlymetal6s6s_1.pxi.spice
index ab22441..93503a1 100644
--- a/cells/dlymetal6s6s/sky130_fd_sc_ls__dlymetal6s6s_1.pxi.spice
+++ b/cells/dlymetal6s6s/sky130_fd_sc_ls__dlymetal6s6s_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dlymetal6s6s_1.pxi.spice
-* Created: Fri Aug 28 13:21:58 2020
+* Created: Wed Sep 2 11:05:45 2020
*
x_PM_SKY130_FD_SC_LS__DLYMETAL6S6S_1%A N_A_M1004_g N_A_c_88_n N_A_M1011_g A
+ N_A_c_89_n PM_SKY130_FD_SC_LS__DLYMETAL6S6S_1%A
diff --git a/cells/dlymetal6s6s/sky130_fd_sc_ls__dlymetal6s6s_1.spice b/cells/dlymetal6s6s/sky130_fd_sc_ls__dlymetal6s6s_1.spice
index 2db9d18..be2fbfb 100644
--- a/cells/dlymetal6s6s/sky130_fd_sc_ls__dlymetal6s6s_1.spice
+++ b/cells/dlymetal6s6s/sky130_fd_sc_ls__dlymetal6s6s_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__dlymetal6s6s_1.spice
-* Created: Fri Aug 28 13:21:58 2020
+* Created: Wed Sep 2 11:05:45 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/ebufn/sky130_fd_sc_ls__ebufn_1.lvs.report b/cells/ebufn/sky130_fd_sc_ls__ebufn_1.lvs.report
new file mode 100644
index 0000000..b9118cd
--- /dev/null
+++ b/cells/ebufn/sky130_fd_sc_ls__ebufn_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__ebufn_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__ebufn_1.sp ('sky130_fd_sc_ls__ebufn_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/ebufn/sky130_fd_sc_ls__ebufn_1.spice ('sky130_fd_sc_ls__ebufn_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:05:49 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__ebufn_1 sky130_fd_sc_ls__ebufn_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__ebufn_1
+SOURCE CELL NAME: sky130_fd_sc_ls__ebufn_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 11 11
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 9 9
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB TE_B A VPWR Z VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/ebufn/sky130_fd_sc_ls__ebufn_1.pex.spice b/cells/ebufn/sky130_fd_sc_ls__ebufn_1.pex.spice
index b3d28ae..9ed580c 100644
--- a/cells/ebufn/sky130_fd_sc_ls__ebufn_1.pex.spice
+++ b/cells/ebufn/sky130_fd_sc_ls__ebufn_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__ebufn_1.pex.spice
-* Created: Fri Aug 28 13:22:17 2020
+* Created: Wed Sep 2 11:05:52 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/ebufn/sky130_fd_sc_ls__ebufn_1.pxi.spice b/cells/ebufn/sky130_fd_sc_ls__ebufn_1.pxi.spice
index d35406a..01f2c57 100644
--- a/cells/ebufn/sky130_fd_sc_ls__ebufn_1.pxi.spice
+++ b/cells/ebufn/sky130_fd_sc_ls__ebufn_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__ebufn_1.pxi.spice
-* Created: Fri Aug 28 13:22:17 2020
+* Created: Wed Sep 2 11:05:52 2020
*
x_PM_SKY130_FD_SC_LS__EBUFN_1%TE_B N_TE_B_c_68_n N_TE_B_M1001_g N_TE_B_M1007_g
+ N_TE_B_c_70_n N_TE_B_c_71_n N_TE_B_c_76_n N_TE_B_M1003_g N_TE_B_c_77_n
diff --git a/cells/ebufn/sky130_fd_sc_ls__ebufn_1.spice b/cells/ebufn/sky130_fd_sc_ls__ebufn_1.spice
index 8926dad..07bde0b 100644
--- a/cells/ebufn/sky130_fd_sc_ls__ebufn_1.spice
+++ b/cells/ebufn/sky130_fd_sc_ls__ebufn_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__ebufn_1.spice
-* Created: Fri Aug 28 13:22:17 2020
+* Created: Wed Sep 2 11:05:52 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/ebufn/sky130_fd_sc_ls__ebufn_2.lvs.report b/cells/ebufn/sky130_fd_sc_ls__ebufn_2.lvs.report
new file mode 100644
index 0000000..a32e05c
--- /dev/null
+++ b/cells/ebufn/sky130_fd_sc_ls__ebufn_2.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__ebufn_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__ebufn_2.sp ('sky130_fd_sc_ls__ebufn_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/ebufn/sky130_fd_sc_ls__ebufn_2.spice ('sky130_fd_sc_ls__ebufn_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:05:56 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__ebufn_2 sky130_fd_sc_ls__ebufn_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__ebufn_2
+SOURCE CELL NAME: sky130_fd_sc_ls__ebufn_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 11 11
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 9 9
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 8 layout mos transistors were reduced to 4.
+ 4 mos transistors were deleted by parallel reduction.
+ 8 source mos transistors were reduced to 4.
+ 4 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB TE_B A Z VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/ebufn/sky130_fd_sc_ls__ebufn_2.pex.spice b/cells/ebufn/sky130_fd_sc_ls__ebufn_2.pex.spice
index 4396c1d..a140205 100644
--- a/cells/ebufn/sky130_fd_sc_ls__ebufn_2.pex.spice
+++ b/cells/ebufn/sky130_fd_sc_ls__ebufn_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__ebufn_2.pex.spice
-* Created: Fri Aug 28 13:22:26 2020
+* Created: Wed Sep 2 11:05:59 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/ebufn/sky130_fd_sc_ls__ebufn_2.pxi.spice b/cells/ebufn/sky130_fd_sc_ls__ebufn_2.pxi.spice
index da4a713..3f8f5d6 100644
--- a/cells/ebufn/sky130_fd_sc_ls__ebufn_2.pxi.spice
+++ b/cells/ebufn/sky130_fd_sc_ls__ebufn_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__ebufn_2.pxi.spice
-* Created: Fri Aug 28 13:22:26 2020
+* Created: Wed Sep 2 11:05:59 2020
*
x_PM_SKY130_FD_SC_LS__EBUFN_2%A_84_48# N_A_84_48#_M1000_d N_A_84_48#_M1006_d
+ N_A_84_48#_M1007_g N_A_84_48#_c_86_n N_A_84_48#_M1010_g N_A_84_48#_M1008_g
diff --git a/cells/ebufn/sky130_fd_sc_ls__ebufn_2.spice b/cells/ebufn/sky130_fd_sc_ls__ebufn_2.spice
index 4ddd79a..1fd8072 100644
--- a/cells/ebufn/sky130_fd_sc_ls__ebufn_2.spice
+++ b/cells/ebufn/sky130_fd_sc_ls__ebufn_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__ebufn_2.spice
-* Created: Fri Aug 28 13:22:26 2020
+* Created: Wed Sep 2 11:05:59 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/ebufn/sky130_fd_sc_ls__ebufn_4.lvs.report b/cells/ebufn/sky130_fd_sc_ls__ebufn_4.lvs.report
new file mode 100644
index 0000000..451decf
--- /dev/null
+++ b/cells/ebufn/sky130_fd_sc_ls__ebufn_4.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__ebufn_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__ebufn_4.sp ('sky130_fd_sc_ls__ebufn_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/ebufn/sky130_fd_sc_ls__ebufn_4.spice ('sky130_fd_sc_ls__ebufn_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:06:03 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__ebufn_4 sky130_fd_sc_ls__ebufn_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__ebufn_4
+SOURCE CELL NAME: sky130_fd_sc_ls__ebufn_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 11 11
+
+ Instances: 10 10 MN (4 pins)
+ 10 10 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 21 20
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 9 9
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 16 layout mos transistors were reduced to 4.
+ 12 mos transistors were deleted by parallel reduction.
+ 16 source mos transistors were reduced to 4.
+ 12 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A TE_B VPWR Z VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/ebufn/sky130_fd_sc_ls__ebufn_4.pex.spice b/cells/ebufn/sky130_fd_sc_ls__ebufn_4.pex.spice
index e740aa2..762c1e9 100644
--- a/cells/ebufn/sky130_fd_sc_ls__ebufn_4.pex.spice
+++ b/cells/ebufn/sky130_fd_sc_ls__ebufn_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__ebufn_4.pex.spice
-* Created: Fri Aug 28 13:22:35 2020
+* Created: Wed Sep 2 11:06:06 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/ebufn/sky130_fd_sc_ls__ebufn_4.pxi.spice b/cells/ebufn/sky130_fd_sc_ls__ebufn_4.pxi.spice
index b1a0833..5ced9cc 100644
--- a/cells/ebufn/sky130_fd_sc_ls__ebufn_4.pxi.spice
+++ b/cells/ebufn/sky130_fd_sc_ls__ebufn_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__ebufn_4.pxi.spice
-* Created: Fri Aug 28 13:22:35 2020
+* Created: Wed Sep 2 11:06:06 2020
*
x_PM_SKY130_FD_SC_LS__EBUFN_4%A N_A_c_124_n N_A_M1015_g N_A_M1003_g A
+ PM_SKY130_FD_SC_LS__EBUFN_4%A
diff --git a/cells/ebufn/sky130_fd_sc_ls__ebufn_4.spice b/cells/ebufn/sky130_fd_sc_ls__ebufn_4.spice
index ce165ee..672dd62 100644
--- a/cells/ebufn/sky130_fd_sc_ls__ebufn_4.spice
+++ b/cells/ebufn/sky130_fd_sc_ls__ebufn_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__ebufn_4.spice
-* Created: Fri Aug 28 13:22:35 2020
+* Created: Wed Sep 2 11:06:06 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/ebufn/sky130_fd_sc_ls__ebufn_8.lvs.report b/cells/ebufn/sky130_fd_sc_ls__ebufn_8.lvs.report
new file mode 100644
index 0000000..438e556
--- /dev/null
+++ b/cells/ebufn/sky130_fd_sc_ls__ebufn_8.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__ebufn_8.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__ebufn_8.sp ('sky130_fd_sc_ls__ebufn_8')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/ebufn/sky130_fd_sc_ls__ebufn_8.spice ('sky130_fd_sc_ls__ebufn_8')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:06:10 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__ebufn_8 sky130_fd_sc_ls__ebufn_8
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__ebufn_8
+SOURCE CELL NAME: sky130_fd_sc_ls__ebufn_8
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 11 11
+
+ Instances: 19 19 MN (4 pins)
+ 19 19 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 39 38
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 9 9
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 36 layout mos transistors were reduced to 6.
+ 30 mos transistors were deleted by parallel reduction.
+ 36 source mos transistors were reduced to 6.
+ 30 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB TE_B A Z VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/ebufn/sky130_fd_sc_ls__ebufn_8.pex.spice b/cells/ebufn/sky130_fd_sc_ls__ebufn_8.pex.spice
index 2744f54..47f01c8 100644
--- a/cells/ebufn/sky130_fd_sc_ls__ebufn_8.pex.spice
+++ b/cells/ebufn/sky130_fd_sc_ls__ebufn_8.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__ebufn_8.pex.spice
-* Created: Fri Aug 28 13:22:43 2020
+* Created: Wed Sep 2 11:06:14 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/ebufn/sky130_fd_sc_ls__ebufn_8.pxi.spice b/cells/ebufn/sky130_fd_sc_ls__ebufn_8.pxi.spice
index 27992dc..7e32c5b 100644
--- a/cells/ebufn/sky130_fd_sc_ls__ebufn_8.pxi.spice
+++ b/cells/ebufn/sky130_fd_sc_ls__ebufn_8.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__ebufn_8.pxi.spice
-* Created: Fri Aug 28 13:22:43 2020
+* Created: Wed Sep 2 11:06:14 2020
*
x_PM_SKY130_FD_SC_LS__EBUFN_8%A_84_48# N_A_84_48#_M1008_d N_A_84_48#_M1005_s
+ N_A_84_48#_M1006_g N_A_84_48#_c_218_n N_A_84_48#_M1003_g N_A_84_48#_M1010_g
diff --git a/cells/ebufn/sky130_fd_sc_ls__ebufn_8.spice b/cells/ebufn/sky130_fd_sc_ls__ebufn_8.spice
index 1944534..4135f4e 100644
--- a/cells/ebufn/sky130_fd_sc_ls__ebufn_8.spice
+++ b/cells/ebufn/sky130_fd_sc_ls__ebufn_8.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__ebufn_8.spice
-* Created: Fri Aug 28 13:22:43 2020
+* Created: Wed Sep 2 11:06:14 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/edfxbp/sky130_fd_sc_ls__edfxbp_1.lvs.report b/cells/edfxbp/sky130_fd_sc_ls__edfxbp_1.lvs.report
new file mode 100644
index 0000000..445ba7b
--- /dev/null
+++ b/cells/edfxbp/sky130_fd_sc_ls__edfxbp_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__edfxbp_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__edfxbp_1.sp ('sky130_fd_sc_ls__edfxbp_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/edfxbp/sky130_fd_sc_ls__edfxbp_1.spice ('sky130_fd_sc_ls__edfxbp_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:06:18 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__edfxbp_1 sky130_fd_sc_ls__edfxbp_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__edfxbp_1
+SOURCE CELL NAME: sky130_fd_sc_ls__edfxbp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 27 27
+
+ Instances: 18 18 MN (4 pins)
+ 18 18 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 37 36
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 17 17
+
+ Instances: 8 8 MN (4 pins)
+ 8 8 MP (4 pins)
+ 5 5 SMN2 (4 pins)
+ 5 5 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 26 26
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 17 17 0 0
+
+ Instances: 8 8 0 0 MN(NSHORT)
+ 8 8 0 0 MP(PHIGHVT)
+ 5 5 0 0 SMN2
+ 5 5 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 26 26 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D DE CLK VPWR Q Q_N VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/edfxbp/sky130_fd_sc_ls__edfxbp_1.pex.spice b/cells/edfxbp/sky130_fd_sc_ls__edfxbp_1.pex.spice
index ea00de6..93e16b5 100644
--- a/cells/edfxbp/sky130_fd_sc_ls__edfxbp_1.pex.spice
+++ b/cells/edfxbp/sky130_fd_sc_ls__edfxbp_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__edfxbp_1.pex.spice
-* Created: Fri Aug 28 13:22:58 2020
+* Created: Wed Sep 2 11:06:21 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/edfxbp/sky130_fd_sc_ls__edfxbp_1.pxi.spice b/cells/edfxbp/sky130_fd_sc_ls__edfxbp_1.pxi.spice
index 4a88f74..a8e1c3f 100644
--- a/cells/edfxbp/sky130_fd_sc_ls__edfxbp_1.pxi.spice
+++ b/cells/edfxbp/sky130_fd_sc_ls__edfxbp_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__edfxbp_1.pxi.spice
-* Created: Fri Aug 28 13:22:58 2020
+* Created: Wed Sep 2 11:06:21 2020
*
x_PM_SKY130_FD_SC_LS__EDFXBP_1%D N_D_c_285_n N_D_c_290_n N_D_c_291_n N_D_M1024_g
+ N_D_M1031_g D D N_D_c_287_n N_D_c_288_n N_D_c_293_n
diff --git a/cells/edfxbp/sky130_fd_sc_ls__edfxbp_1.spice b/cells/edfxbp/sky130_fd_sc_ls__edfxbp_1.spice
index 1f50ef6..ef59849 100644
--- a/cells/edfxbp/sky130_fd_sc_ls__edfxbp_1.spice
+++ b/cells/edfxbp/sky130_fd_sc_ls__edfxbp_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__edfxbp_1.spice
-* Created: Fri Aug 28 13:22:58 2020
+* Created: Wed Sep 2 11:06:21 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/edfxtp/sky130_fd_sc_ls__edfxtp_1.lvs.report b/cells/edfxtp/sky130_fd_sc_ls__edfxtp_1.lvs.report
new file mode 100644
index 0000000..8d5e8e3
--- /dev/null
+++ b/cells/edfxtp/sky130_fd_sc_ls__edfxtp_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__edfxtp_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__edfxtp_1.sp ('sky130_fd_sc_ls__edfxtp_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/edfxtp/sky130_fd_sc_ls__edfxtp_1.spice ('sky130_fd_sc_ls__edfxtp_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:06:25 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__edfxtp_1 sky130_fd_sc_ls__edfxtp_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__edfxtp_1
+SOURCE CELL NAME: sky130_fd_sc_ls__edfxtp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 26 26
+
+ Instances: 17 17 MN (4 pins)
+ 17 17 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 35 34
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 16 16
+
+ Instances: 7 7 MN (4 pins)
+ 7 7 MP (4 pins)
+ 5 5 SMN2 (4 pins)
+ 5 5 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 24 24
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 16 16 0 0
+
+ Instances: 7 7 0 0 MN(NSHORT)
+ 7 7 0 0 MP(PHIGHVT)
+ 5 5 0 0 SMN2
+ 5 5 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 24 24 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D DE CLK VPWR Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/edfxtp/sky130_fd_sc_ls__edfxtp_1.pex.spice b/cells/edfxtp/sky130_fd_sc_ls__edfxtp_1.pex.spice
index f95763d..7b3a96a 100644
--- a/cells/edfxtp/sky130_fd_sc_ls__edfxtp_1.pex.spice
+++ b/cells/edfxtp/sky130_fd_sc_ls__edfxtp_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__edfxtp_1.pex.spice
-* Created: Fri Aug 28 13:23:13 2020
+* Created: Wed Sep 2 11:06:28 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/edfxtp/sky130_fd_sc_ls__edfxtp_1.pxi.spice b/cells/edfxtp/sky130_fd_sc_ls__edfxtp_1.pxi.spice
index 2fe88c5..2f50815 100644
--- a/cells/edfxtp/sky130_fd_sc_ls__edfxtp_1.pxi.spice
+++ b/cells/edfxtp/sky130_fd_sc_ls__edfxtp_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__edfxtp_1.pxi.spice
-* Created: Fri Aug 28 13:23:13 2020
+* Created: Wed Sep 2 11:06:28 2020
*
x_PM_SKY130_FD_SC_LS__EDFXTP_1%D N_D_c_269_n N_D_c_270_n N_D_M1024_g N_D_M1007_g
+ D D N_D_c_266_n N_D_c_267_n N_D_c_268_n N_D_c_273_n
diff --git a/cells/edfxtp/sky130_fd_sc_ls__edfxtp_1.spice b/cells/edfxtp/sky130_fd_sc_ls__edfxtp_1.spice
index 975d115..9f99865 100644
--- a/cells/edfxtp/sky130_fd_sc_ls__edfxtp_1.spice
+++ b/cells/edfxtp/sky130_fd_sc_ls__edfxtp_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__edfxtp_1.spice
-* Created: Fri Aug 28 13:23:13 2020
+* Created: Wed Sep 2 11:06:28 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/einvn/sky130_fd_sc_ls__einvn_1.lvs.report b/cells/einvn/sky130_fd_sc_ls__einvn_1.lvs.report
new file mode 100644
index 0000000..53db670
--- /dev/null
+++ b/cells/einvn/sky130_fd_sc_ls__einvn_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__einvn_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__einvn_1.sp ('sky130_fd_sc_ls__einvn_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/einvn/sky130_fd_sc_ls__einvn_1.spice ('sky130_fd_sc_ls__einvn_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:06:32 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__einvn_1 sky130_fd_sc_ls__einvn_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__einvn_1
+SOURCE CELL NAME: sky130_fd_sc_ls__einvn_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 10 10
+
+ Instances: 3 3 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 7 6
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB TE_B A VPWR Z VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/einvn/sky130_fd_sc_ls__einvn_1.pex.spice b/cells/einvn/sky130_fd_sc_ls__einvn_1.pex.spice
index 86a9638..0e56cd0 100644
--- a/cells/einvn/sky130_fd_sc_ls__einvn_1.pex.spice
+++ b/cells/einvn/sky130_fd_sc_ls__einvn_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__einvn_1.pex.spice
-* Created: Fri Aug 28 13:23:26 2020
+* Created: Wed Sep 2 11:06:35 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/einvn/sky130_fd_sc_ls__einvn_1.pxi.spice b/cells/einvn/sky130_fd_sc_ls__einvn_1.pxi.spice
index d5e989c..fdca7c4 100644
--- a/cells/einvn/sky130_fd_sc_ls__einvn_1.pxi.spice
+++ b/cells/einvn/sky130_fd_sc_ls__einvn_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__einvn_1.pxi.spice
-* Created: Fri Aug 28 13:23:26 2020
+* Created: Wed Sep 2 11:06:35 2020
*
x_PM_SKY130_FD_SC_LS__EINVN_1%A_22_46# N_A_22_46#_M1004_s N_A_22_46#_M1005_s
+ N_A_22_46#_c_42_n N_A_22_46#_c_43_n N_A_22_46#_M1000_g N_A_22_46#_c_44_n
diff --git a/cells/einvn/sky130_fd_sc_ls__einvn_1.spice b/cells/einvn/sky130_fd_sc_ls__einvn_1.spice
index 366d18c..d94f483 100644
--- a/cells/einvn/sky130_fd_sc_ls__einvn_1.spice
+++ b/cells/einvn/sky130_fd_sc_ls__einvn_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__einvn_1.spice
-* Created: Fri Aug 28 13:23:26 2020
+* Created: Wed Sep 2 11:06:35 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/einvn/sky130_fd_sc_ls__einvn_2.lvs.report b/cells/einvn/sky130_fd_sc_ls__einvn_2.lvs.report
new file mode 100644
index 0000000..51892aa
--- /dev/null
+++ b/cells/einvn/sky130_fd_sc_ls__einvn_2.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__einvn_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__einvn_2.sp ('sky130_fd_sc_ls__einvn_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/einvn/sky130_fd_sc_ls__einvn_2.spice ('sky130_fd_sc_ls__einvn_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:06:39 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__einvn_2 sky130_fd_sc_ls__einvn_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__einvn_2
+SOURCE CELL NAME: sky130_fd_sc_ls__einvn_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 10 10
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 8 layout mos transistors were reduced to 4.
+ 4 mos transistors were deleted by parallel reduction.
+ 8 source mos transistors were reduced to 4.
+ 4 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB TE_B A VPWR Z VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/einvn/sky130_fd_sc_ls__einvn_2.pex.spice b/cells/einvn/sky130_fd_sc_ls__einvn_2.pex.spice
index 0d72912..108b102 100644
--- a/cells/einvn/sky130_fd_sc_ls__einvn_2.pex.spice
+++ b/cells/einvn/sky130_fd_sc_ls__einvn_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__einvn_2.pex.spice
-* Created: Fri Aug 28 13:23:35 2020
+* Created: Wed Sep 2 11:06:43 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/einvn/sky130_fd_sc_ls__einvn_2.pxi.spice b/cells/einvn/sky130_fd_sc_ls__einvn_2.pxi.spice
index c0d65fa..a10fa20 100644
--- a/cells/einvn/sky130_fd_sc_ls__einvn_2.pxi.spice
+++ b/cells/einvn/sky130_fd_sc_ls__einvn_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__einvn_2.pxi.spice
-* Created: Fri Aug 28 13:23:35 2020
+* Created: Wed Sep 2 11:06:43 2020
*
x_PM_SKY130_FD_SC_LS__EINVN_2%A_115_464# N_A_115_464#_M1009_d
+ N_A_115_464#_M1006_d N_A_115_464#_c_68_n N_A_115_464#_M1001_g
diff --git a/cells/einvn/sky130_fd_sc_ls__einvn_2.spice b/cells/einvn/sky130_fd_sc_ls__einvn_2.spice
index d851a06..4e0dcbc 100644
--- a/cells/einvn/sky130_fd_sc_ls__einvn_2.spice
+++ b/cells/einvn/sky130_fd_sc_ls__einvn_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__einvn_2.spice
-* Created: Fri Aug 28 13:23:35 2020
+* Created: Wed Sep 2 11:06:43 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/einvn/sky130_fd_sc_ls__einvn_4.lvs.report b/cells/einvn/sky130_fd_sc_ls__einvn_4.lvs.report
new file mode 100644
index 0000000..f8618a7
--- /dev/null
+++ b/cells/einvn/sky130_fd_sc_ls__einvn_4.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__einvn_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__einvn_4.sp ('sky130_fd_sc_ls__einvn_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/einvn/sky130_fd_sc_ls__einvn_4.spice ('sky130_fd_sc_ls__einvn_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:06:46 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__einvn_4 sky130_fd_sc_ls__einvn_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__einvn_4
+SOURCE CELL NAME: sky130_fd_sc_ls__einvn_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 10 10
+
+ Instances: 9 9 MN (4 pins)
+ 9 9 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 19 18
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 16 layout mos transistors were reduced to 4.
+ 12 mos transistors were deleted by parallel reduction.
+ 16 source mos transistors were reduced to 4.
+ 12 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB TE_B A VPWR Z VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/einvn/sky130_fd_sc_ls__einvn_4.pex.spice b/cells/einvn/sky130_fd_sc_ls__einvn_4.pex.spice
index 0839e83..d5271f3 100644
--- a/cells/einvn/sky130_fd_sc_ls__einvn_4.pex.spice
+++ b/cells/einvn/sky130_fd_sc_ls__einvn_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__einvn_4.pex.spice
-* Created: Fri Aug 28 13:23:45 2020
+* Created: Wed Sep 2 11:06:50 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/einvn/sky130_fd_sc_ls__einvn_4.pxi.spice b/cells/einvn/sky130_fd_sc_ls__einvn_4.pxi.spice
index da8f8a1..226ae0b 100644
--- a/cells/einvn/sky130_fd_sc_ls__einvn_4.pxi.spice
+++ b/cells/einvn/sky130_fd_sc_ls__einvn_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__einvn_4.pxi.spice
-* Created: Fri Aug 28 13:23:45 2020
+* Created: Wed Sep 2 11:06:50 2020
*
x_PM_SKY130_FD_SC_LS__EINVN_4%A_114_74# N_A_114_74#_M1013_d N_A_114_74#_M1006_d
+ N_A_114_74#_c_98_n N_A_114_74#_c_99_n N_A_114_74#_c_100_n N_A_114_74#_M1002_g
diff --git a/cells/einvn/sky130_fd_sc_ls__einvn_4.spice b/cells/einvn/sky130_fd_sc_ls__einvn_4.spice
index a448df5..8f4ee53 100644
--- a/cells/einvn/sky130_fd_sc_ls__einvn_4.spice
+++ b/cells/einvn/sky130_fd_sc_ls__einvn_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__einvn_4.spice
-* Created: Fri Aug 28 13:23:45 2020
+* Created: Wed Sep 2 11:06:50 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/einvn/sky130_fd_sc_ls__einvn_8.lvs.report b/cells/einvn/sky130_fd_sc_ls__einvn_8.lvs.report
new file mode 100644
index 0000000..befb7e1
--- /dev/null
+++ b/cells/einvn/sky130_fd_sc_ls__einvn_8.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__einvn_8.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__einvn_8.sp ('sky130_fd_sc_ls__einvn_8')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/einvn/sky130_fd_sc_ls__einvn_8.spice ('sky130_fd_sc_ls__einvn_8')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:06:54 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__einvn_8 sky130_fd_sc_ls__einvn_8
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__einvn_8
+SOURCE CELL NAME: sky130_fd_sc_ls__einvn_8
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 10 10
+
+ Instances: 17 17 MN (4 pins)
+ 17 17 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 35 34
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 32 layout mos transistors were reduced to 4.
+ 28 mos transistors were deleted by parallel reduction.
+ 32 source mos transistors were reduced to 4.
+ 28 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB TE_B A VPWR Z VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/einvn/sky130_fd_sc_ls__einvn_8.pex.spice b/cells/einvn/sky130_fd_sc_ls__einvn_8.pex.spice
index a4fae3d..677ebca 100644
--- a/cells/einvn/sky130_fd_sc_ls__einvn_8.pex.spice
+++ b/cells/einvn/sky130_fd_sc_ls__einvn_8.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__einvn_8.pex.spice
-* Created: Fri Aug 28 13:24:00 2020
+* Created: Wed Sep 2 11:06:57 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/einvn/sky130_fd_sc_ls__einvn_8.pxi.spice b/cells/einvn/sky130_fd_sc_ls__einvn_8.pxi.spice
index 5ed1a4f..9c84562 100644
--- a/cells/einvn/sky130_fd_sc_ls__einvn_8.pxi.spice
+++ b/cells/einvn/sky130_fd_sc_ls__einvn_8.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__einvn_8.pxi.spice
-* Created: Fri Aug 28 13:24:00 2020
+* Created: Wed Sep 2 11:06:57 2020
*
x_PM_SKY130_FD_SC_LS__EINVN_8%A_126_74# N_A_126_74#_M1032_d N_A_126_74#_M1020_d
+ N_A_126_74#_c_173_n N_A_126_74#_c_174_n N_A_126_74#_c_175_n
diff --git a/cells/einvn/sky130_fd_sc_ls__einvn_8.spice b/cells/einvn/sky130_fd_sc_ls__einvn_8.spice
index 5cdf0ee..ee3fac6 100644
--- a/cells/einvn/sky130_fd_sc_ls__einvn_8.spice
+++ b/cells/einvn/sky130_fd_sc_ls__einvn_8.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__einvn_8.spice
-* Created: Fri Aug 28 13:24:00 2020
+* Created: Wed Sep 2 11:06:57 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/einvp/sky130_fd_sc_ls__einvp_1.lvs.report b/cells/einvp/sky130_fd_sc_ls__einvp_1.lvs.report
new file mode 100644
index 0000000..1b6e206
--- /dev/null
+++ b/cells/einvp/sky130_fd_sc_ls__einvp_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__einvp_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__einvp_1.sp ('sky130_fd_sc_ls__einvp_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/einvp/sky130_fd_sc_ls__einvp_1.spice ('sky130_fd_sc_ls__einvp_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:07:01 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__einvp_1 sky130_fd_sc_ls__einvp_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__einvp_1
+SOURCE CELL NAME: sky130_fd_sc_ls__einvp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 10 10
+
+ Instances: 3 3 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 7 6
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB TE A VPWR Z VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/einvp/sky130_fd_sc_ls__einvp_1.pex.spice b/cells/einvp/sky130_fd_sc_ls__einvp_1.pex.spice
index 2dbb66e..2b011f9 100644
--- a/cells/einvp/sky130_fd_sc_ls__einvp_1.pex.spice
+++ b/cells/einvp/sky130_fd_sc_ls__einvp_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__einvp_1.pex.spice
-* Created: Fri Aug 28 13:24:15 2020
+* Created: Wed Sep 2 11:07:05 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/einvp/sky130_fd_sc_ls__einvp_1.pxi.spice b/cells/einvp/sky130_fd_sc_ls__einvp_1.pxi.spice
index 6ad03e4..3c1dba6 100644
--- a/cells/einvp/sky130_fd_sc_ls__einvp_1.pxi.spice
+++ b/cells/einvp/sky130_fd_sc_ls__einvp_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__einvp_1.pxi.spice
-* Created: Fri Aug 28 13:24:15 2020
+* Created: Wed Sep 2 11:07:05 2020
*
x_PM_SKY130_FD_SC_LS__EINVP_1%TE N_TE_c_51_n N_TE_M1000_g N_TE_M1003_g
+ N_TE_c_46_n N_TE_c_47_n N_TE_M1001_g TE TE N_TE_c_50_n
diff --git a/cells/einvp/sky130_fd_sc_ls__einvp_1.spice b/cells/einvp/sky130_fd_sc_ls__einvp_1.spice
index aefe714..ba7eacb 100644
--- a/cells/einvp/sky130_fd_sc_ls__einvp_1.spice
+++ b/cells/einvp/sky130_fd_sc_ls__einvp_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__einvp_1.spice
-* Created: Fri Aug 28 13:24:15 2020
+* Created: Wed Sep 2 11:07:05 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/einvp/sky130_fd_sc_ls__einvp_2.lvs.report b/cells/einvp/sky130_fd_sc_ls__einvp_2.lvs.report
new file mode 100644
index 0000000..3347a41
--- /dev/null
+++ b/cells/einvp/sky130_fd_sc_ls__einvp_2.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__einvp_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__einvp_2.sp ('sky130_fd_sc_ls__einvp_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/einvp/sky130_fd_sc_ls__einvp_2.spice ('sky130_fd_sc_ls__einvp_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:07:08 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__einvp_2 sky130_fd_sc_ls__einvp_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__einvp_2
+SOURCE CELL NAME: sky130_fd_sc_ls__einvp_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 10 10
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 8 layout mos transistors were reduced to 4.
+ 4 mos transistors were deleted by parallel reduction.
+ 8 source mos transistors were reduced to 4.
+ 4 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A TE Z VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/einvp/sky130_fd_sc_ls__einvp_2.pex.spice b/cells/einvp/sky130_fd_sc_ls__einvp_2.pex.spice
index 31bd85e..6314e87 100644
--- a/cells/einvp/sky130_fd_sc_ls__einvp_2.pex.spice
+++ b/cells/einvp/sky130_fd_sc_ls__einvp_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__einvp_2.pex.spice
-* Created: Fri Aug 28 13:24:28 2020
+* Created: Wed Sep 2 11:07:12 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/einvp/sky130_fd_sc_ls__einvp_2.pxi.spice b/cells/einvp/sky130_fd_sc_ls__einvp_2.pxi.spice
index be98eea..c70e8fc 100644
--- a/cells/einvp/sky130_fd_sc_ls__einvp_2.pxi.spice
+++ b/cells/einvp/sky130_fd_sc_ls__einvp_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__einvp_2.pxi.spice
-* Created: Fri Aug 28 13:24:28 2020
+* Created: Wed Sep 2 11:07:12 2020
*
x_PM_SKY130_FD_SC_LS__EINVP_2%A N_A_c_75_n N_A_M1004_g N_A_c_71_n N_A_M1001_g
+ N_A_c_76_n N_A_M1005_g N_A_c_72_n N_A_M1008_g A N_A_c_74_n
diff --git a/cells/einvp/sky130_fd_sc_ls__einvp_2.spice b/cells/einvp/sky130_fd_sc_ls__einvp_2.spice
index 023a5bc..5fd8bf9 100644
--- a/cells/einvp/sky130_fd_sc_ls__einvp_2.spice
+++ b/cells/einvp/sky130_fd_sc_ls__einvp_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__einvp_2.spice
-* Created: Fri Aug 28 13:24:28 2020
+* Created: Wed Sep 2 11:07:12 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/einvp/sky130_fd_sc_ls__einvp_4.lvs.report b/cells/einvp/sky130_fd_sc_ls__einvp_4.lvs.report
new file mode 100644
index 0000000..64f4a53
--- /dev/null
+++ b/cells/einvp/sky130_fd_sc_ls__einvp_4.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__einvp_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__einvp_4.sp ('sky130_fd_sc_ls__einvp_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/einvp/sky130_fd_sc_ls__einvp_4.spice ('sky130_fd_sc_ls__einvp_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:07:15 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__einvp_4 sky130_fd_sc_ls__einvp_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__einvp_4
+SOURCE CELL NAME: sky130_fd_sc_ls__einvp_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 10 10
+
+ Instances: 9 9 MN (4 pins)
+ 9 9 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 19 18
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 16 layout mos transistors were reduced to 4.
+ 12 mos transistors were deleted by parallel reduction.
+ 16 source mos transistors were reduced to 4.
+ 12 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A TE Z VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/einvp/sky130_fd_sc_ls__einvp_4.pex.spice b/cells/einvp/sky130_fd_sc_ls__einvp_4.pex.spice
index 75516cc..feca604 100644
--- a/cells/einvp/sky130_fd_sc_ls__einvp_4.pex.spice
+++ b/cells/einvp/sky130_fd_sc_ls__einvp_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__einvp_4.pex.spice
-* Created: Fri Aug 28 13:24:36 2020
+* Created: Wed Sep 2 11:07:18 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/einvp/sky130_fd_sc_ls__einvp_4.pxi.spice b/cells/einvp/sky130_fd_sc_ls__einvp_4.pxi.spice
index a5665ad..98eb99c 100644
--- a/cells/einvp/sky130_fd_sc_ls__einvp_4.pxi.spice
+++ b/cells/einvp/sky130_fd_sc_ls__einvp_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__einvp_4.pxi.spice
-* Created: Fri Aug 28 13:24:36 2020
+* Created: Wed Sep 2 11:07:18 2020
*
x_PM_SKY130_FD_SC_LS__EINVP_4%A N_A_M1002_g N_A_c_120_n N_A_M1000_g N_A_M1005_g
+ N_A_c_121_n N_A_M1008_g N_A_c_122_n N_A_M1009_g N_A_M1014_g N_A_c_114_n
diff --git a/cells/einvp/sky130_fd_sc_ls__einvp_4.spice b/cells/einvp/sky130_fd_sc_ls__einvp_4.spice
index e2f20e3..a644b1e 100644
--- a/cells/einvp/sky130_fd_sc_ls__einvp_4.spice
+++ b/cells/einvp/sky130_fd_sc_ls__einvp_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__einvp_4.spice
-* Created: Fri Aug 28 13:24:36 2020
+* Created: Wed Sep 2 11:07:18 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/einvp/sky130_fd_sc_ls__einvp_8.lvs.report b/cells/einvp/sky130_fd_sc_ls__einvp_8.lvs.report
new file mode 100644
index 0000000..d2d5146
--- /dev/null
+++ b/cells/einvp/sky130_fd_sc_ls__einvp_8.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__einvp_8.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__einvp_8.sp ('sky130_fd_sc_ls__einvp_8')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/einvp/sky130_fd_sc_ls__einvp_8.spice ('sky130_fd_sc_ls__einvp_8')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:07:22 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__einvp_8 sky130_fd_sc_ls__einvp_8
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__einvp_8
+SOURCE CELL NAME: sky130_fd_sc_ls__einvp_8
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 10 10
+
+ Instances: 17 17 MN (4 pins)
+ 17 17 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 35 34
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 32 layout mos transistors were reduced to 4.
+ 28 mos transistors were deleted by parallel reduction.
+ 32 source mos transistors were reduced to 4.
+ 28 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A TE Z VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/einvp/sky130_fd_sc_ls__einvp_8.pex.spice b/cells/einvp/sky130_fd_sc_ls__einvp_8.pex.spice
index 0f2238a..1cf481a 100644
--- a/cells/einvp/sky130_fd_sc_ls__einvp_8.pex.spice
+++ b/cells/einvp/sky130_fd_sc_ls__einvp_8.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__einvp_8.pex.spice
-* Created: Fri Aug 28 13:24:45 2020
+* Created: Wed Sep 2 11:07:25 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/einvp/sky130_fd_sc_ls__einvp_8.pxi.spice b/cells/einvp/sky130_fd_sc_ls__einvp_8.pxi.spice
index c6ec35d..e8fd158 100644
--- a/cells/einvp/sky130_fd_sc_ls__einvp_8.pxi.spice
+++ b/cells/einvp/sky130_fd_sc_ls__einvp_8.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__einvp_8.pxi.spice
-* Created: Fri Aug 28 13:24:45 2020
+* Created: Wed Sep 2 11:07:25 2020
*
x_PM_SKY130_FD_SC_LS__EINVP_8%A N_A_c_177_n N_A_M1005_g N_A_c_187_n N_A_M1000_g
+ N_A_c_178_n N_A_M1009_g N_A_c_188_n N_A_M1003_g N_A_c_189_n N_A_M1010_g
diff --git a/cells/einvp/sky130_fd_sc_ls__einvp_8.spice b/cells/einvp/sky130_fd_sc_ls__einvp_8.spice
index a6961d3..edbd5a1 100644
--- a/cells/einvp/sky130_fd_sc_ls__einvp_8.spice
+++ b/cells/einvp/sky130_fd_sc_ls__einvp_8.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__einvp_8.spice
-* Created: Fri Aug 28 13:24:45 2020
+* Created: Wed Sep 2 11:07:25 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/fa/sky130_fd_sc_ls__fa_1.lvs.report b/cells/fa/sky130_fd_sc_ls__fa_1.lvs.report
new file mode 100644
index 0000000..7c72645
--- /dev/null
+++ b/cells/fa/sky130_fd_sc_ls__fa_1.lvs.report
@@ -0,0 +1,480 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__fa_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__fa_1.sp ('sky130_fd_sc_ls__fa_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/fa/sky130_fd_sc_ls__fa_1.spice ('sky130_fd_sc_ls__fa_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:07:28 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__fa_1 sky130_fd_sc_ls__fa_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__fa_1
+SOURCE CELL NAME: sky130_fd_sc_ls__fa_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 21 21
+
+ Instances: 14 14 MN (4 pins)
+ 14 14 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 29 28
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 11 11
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SMP3 (5 pins)
+ 1 1 SPMN_2_1 (5 pins)
+ 1 1 SPMN_3_1 (6 pins)
+ 1 1 SPMP_2_1 (5 pins)
+ 1 1 SPMP_3_1 (6 pins)
+ ------ ------
+ Total Inst: 12 12
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMN3
+ 1 1 0 0 SMP2
+ 1 1 0 0 SMP3
+ 1 1 0 0 SPMN_2_1
+ 1 1 0 0 SPMN_3_1
+ 1 1 0 0 SPMP_2_1
+ 1 1 0 0 SPMP_3_1
+ ------- ------- --------- ---------
+ Total Inst: 12 12 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A CIN B SUM VPWR COUT VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/fa/sky130_fd_sc_ls__fa_1.pex.spice b/cells/fa/sky130_fd_sc_ls__fa_1.pex.spice
index 212e1b2..b5c4655 100644
--- a/cells/fa/sky130_fd_sc_ls__fa_1.pex.spice
+++ b/cells/fa/sky130_fd_sc_ls__fa_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__fa_1.pex.spice
-* Created: Fri Aug 28 13:25:01 2020
+* Created: Wed Sep 2 11:07:31 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/fa/sky130_fd_sc_ls__fa_1.pxi.spice b/cells/fa/sky130_fd_sc_ls__fa_1.pxi.spice
index 4d5448c..91bba76 100644
--- a/cells/fa/sky130_fd_sc_ls__fa_1.pxi.spice
+++ b/cells/fa/sky130_fd_sc_ls__fa_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__fa_1.pxi.spice
-* Created: Fri Aug 28 13:25:01 2020
+* Created: Wed Sep 2 11:07:31 2020
*
x_PM_SKY130_FD_SC_LS__FA_1%A_69_260# N_A_69_260#_M1026_d N_A_69_260#_M1000_d
+ N_A_69_260#_M1024_g N_A_69_260#_c_158_n N_A_69_260#_M1021_g
diff --git a/cells/fa/sky130_fd_sc_ls__fa_1.spice b/cells/fa/sky130_fd_sc_ls__fa_1.spice
index 9b4be92..dbe306a 100644
--- a/cells/fa/sky130_fd_sc_ls__fa_1.spice
+++ b/cells/fa/sky130_fd_sc_ls__fa_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__fa_1.spice
-* Created: Fri Aug 28 13:25:01 2020
+* Created: Wed Sep 2 11:07:31 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/fa/sky130_fd_sc_ls__fa_2.lvs.report b/cells/fa/sky130_fd_sc_ls__fa_2.lvs.report
new file mode 100644
index 0000000..95f2da3
--- /dev/null
+++ b/cells/fa/sky130_fd_sc_ls__fa_2.lvs.report
@@ -0,0 +1,485 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__fa_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__fa_2.sp ('sky130_fd_sc_ls__fa_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/fa/sky130_fd_sc_ls__fa_2.spice ('sky130_fd_sc_ls__fa_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:07:34 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__fa_2 sky130_fd_sc_ls__fa_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__fa_2
+SOURCE CELL NAME: sky130_fd_sc_ls__fa_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 21 21
+
+ Instances: 16 16 MN (4 pins)
+ 16 16 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 33 32
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 11 11
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SMP3 (5 pins)
+ 1 1 SPMN_2_1 (5 pins)
+ 1 1 SPMN_3_1 (6 pins)
+ 1 1 SPMP_2_1 (5 pins)
+ 1 1 SPMP_3_1 (6 pins)
+ ------ ------
+ Total Inst: 12 12
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMN3
+ 1 1 0 0 SMP2
+ 1 1 0 0 SMP3
+ 1 1 0 0 SPMN_2_1
+ 1 1 0 0 SPMN_3_1
+ 1 1 0 0 SPMP_2_1
+ 1 1 0 0 SPMP_3_1
+ ------- ------- --------- ---------
+ Total Inst: 12 12 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 8 layout mos transistors were reduced to 4.
+ 4 mos transistors were deleted by parallel reduction.
+ 8 source mos transistors were reduced to 4.
+ 4 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A CIN B VPWR COUT SUM VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/fa/sky130_fd_sc_ls__fa_2.pex.spice b/cells/fa/sky130_fd_sc_ls__fa_2.pex.spice
index 82f9287..82d9e2d 100644
--- a/cells/fa/sky130_fd_sc_ls__fa_2.pex.spice
+++ b/cells/fa/sky130_fd_sc_ls__fa_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__fa_2.pex.spice
-* Created: Fri Aug 28 13:25:17 2020
+* Created: Wed Sep 2 11:07:38 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/fa/sky130_fd_sc_ls__fa_2.pxi.spice b/cells/fa/sky130_fd_sc_ls__fa_2.pxi.spice
index bce3425..1636528 100644
--- a/cells/fa/sky130_fd_sc_ls__fa_2.pxi.spice
+++ b/cells/fa/sky130_fd_sc_ls__fa_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__fa_2.pxi.spice
-* Created: Fri Aug 28 13:25:17 2020
+* Created: Wed Sep 2 11:07:38 2020
*
x_PM_SKY130_FD_SC_LS__FA_2%A N_A_M1015_g N_A_c_172_n N_A_M1007_g N_A_c_173_n
+ N_A_M1019_g N_A_c_174_n N_A_M1016_g N_A_c_175_n N_A_M1018_g N_A_c_176_n
diff --git a/cells/fa/sky130_fd_sc_ls__fa_2.spice b/cells/fa/sky130_fd_sc_ls__fa_2.spice
index 38c602a..68498b8 100644
--- a/cells/fa/sky130_fd_sc_ls__fa_2.spice
+++ b/cells/fa/sky130_fd_sc_ls__fa_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__fa_2.spice
-* Created: Fri Aug 28 13:25:17 2020
+* Created: Wed Sep 2 11:07:38 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/fa/sky130_fd_sc_ls__fa_4.lvs.report b/cells/fa/sky130_fd_sc_ls__fa_4.lvs.report
new file mode 100644
index 0000000..f86c6da
--- /dev/null
+++ b/cells/fa/sky130_fd_sc_ls__fa_4.lvs.report
@@ -0,0 +1,485 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__fa_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__fa_4.sp ('sky130_fd_sc_ls__fa_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/fa/sky130_fd_sc_ls__fa_4.spice ('sky130_fd_sc_ls__fa_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:07:41 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__fa_4 sky130_fd_sc_ls__fa_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__fa_4
+SOURCE CELL NAME: sky130_fd_sc_ls__fa_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 21 21
+
+ Instances: 20 20 MN (4 pins)
+ 20 20 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 41 40
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 11 11
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SMP3 (5 pins)
+ 1 1 SPMN_2_1 (5 pins)
+ 1 1 SPMN_3_1 (6 pins)
+ 1 1 SPMP_2_1 (5 pins)
+ 1 1 SPMP_3_1 (6 pins)
+ ------ ------
+ Total Inst: 12 12
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMN3
+ 1 1 0 0 SMP2
+ 1 1 0 0 SMP3
+ 1 1 0 0 SPMN_2_1
+ 1 1 0 0 SPMN_3_1
+ 1 1 0 0 SPMP_2_1
+ 1 1 0 0 SPMP_3_1
+ ------- ------- --------- ---------
+ Total Inst: 12 12 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 16 layout mos transistors were reduced to 4.
+ 12 mos transistors were deleted by parallel reduction.
+ 16 source mos transistors were reduced to 4.
+ 12 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B CIN A VPWR SUM COUT VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/fa/sky130_fd_sc_ls__fa_4.pex.spice b/cells/fa/sky130_fd_sc_ls__fa_4.pex.spice
index 96037a8..e8fdacb 100644
--- a/cells/fa/sky130_fd_sc_ls__fa_4.pex.spice
+++ b/cells/fa/sky130_fd_sc_ls__fa_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__fa_4.pex.spice
-* Created: Fri Aug 28 13:25:31 2020
+* Created: Wed Sep 2 11:07:44 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/fa/sky130_fd_sc_ls__fa_4.pxi.spice b/cells/fa/sky130_fd_sc_ls__fa_4.pxi.spice
index a9a438b..9c4012c 100644
--- a/cells/fa/sky130_fd_sc_ls__fa_4.pxi.spice
+++ b/cells/fa/sky130_fd_sc_ls__fa_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__fa_4.pxi.spice
-* Created: Fri Aug 28 13:25:31 2020
+* Created: Wed Sep 2 11:07:44 2020
*
x_PM_SKY130_FD_SC_LS__FA_4%B N_B_c_204_n N_B_M1010_g N_B_M1026_g N_B_M1023_g
+ N_B_c_195_n N_B_M1000_g N_B_M1030_g N_B_c_197_n N_B_M1003_g N_B_c_198_n
diff --git a/cells/fa/sky130_fd_sc_ls__fa_4.spice b/cells/fa/sky130_fd_sc_ls__fa_4.spice
index c4e6520..f5b8e4a 100644
--- a/cells/fa/sky130_fd_sc_ls__fa_4.spice
+++ b/cells/fa/sky130_fd_sc_ls__fa_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__fa_4.spice
-* Created: Fri Aug 28 13:25:31 2020
+* Created: Wed Sep 2 11:07:44 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/fah/sky130_fd_sc_ls__fah_1.lvs.report b/cells/fah/sky130_fd_sc_ls__fah_1.lvs.report
new file mode 100644
index 0000000..a4f181e
--- /dev/null
+++ b/cells/fah/sky130_fd_sc_ls__fah_1.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__fah_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__fah_1.sp ('sky130_fd_sc_ls__fah_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/fah/sky130_fd_sc_ls__fah_1.spice ('sky130_fd_sc_ls__fah_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:07:48 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__fah_1 sky130_fd_sc_ls__fah_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__fah_1
+SOURCE CELL NAME: sky130_fd_sc_ls__fah_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 19 19
+
+ Instances: 16 16 MN (4 pins)
+ 16 16 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 33 32
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 19 19
+
+ Instances: 16 16 MN (4 pins)
+ 16 16 MP (4 pins)
+ ------ ------
+ Total Inst: 32 32
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 19 19 0 0
+
+ Instances: 16 16 0 0 MN(NSHORT)
+ 16 16 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 32 32 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB CI B A SUM VPWR COUT VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/fah/sky130_fd_sc_ls__fah_1.pex.spice b/cells/fah/sky130_fd_sc_ls__fah_1.pex.spice
index 71143e8..0750bb2 100644
--- a/cells/fah/sky130_fd_sc_ls__fah_1.pex.spice
+++ b/cells/fah/sky130_fd_sc_ls__fah_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__fah_1.pex.spice
-* Created: Fri Aug 28 13:25:40 2020
+* Created: Wed Sep 2 11:07:52 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/fah/sky130_fd_sc_ls__fah_1.pxi.spice b/cells/fah/sky130_fd_sc_ls__fah_1.pxi.spice
index b333449..8bf850f 100644
--- a/cells/fah/sky130_fd_sc_ls__fah_1.pxi.spice
+++ b/cells/fah/sky130_fd_sc_ls__fah_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__fah_1.pxi.spice
-* Created: Fri Aug 28 13:25:40 2020
+* Created: Wed Sep 2 11:07:52 2020
*
x_PM_SKY130_FD_SC_LS__FAH_1%CI N_CI_c_284_n N_CI_M1005_g N_CI_c_285_n
+ N_CI_M1010_g CI N_CI_c_286_n PM_SKY130_FD_SC_LS__FAH_1%CI
diff --git a/cells/fah/sky130_fd_sc_ls__fah_1.spice b/cells/fah/sky130_fd_sc_ls__fah_1.spice
index 954a200..bc14eff 100644
--- a/cells/fah/sky130_fd_sc_ls__fah_1.spice
+++ b/cells/fah/sky130_fd_sc_ls__fah_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__fah_1.spice
-* Created: Fri Aug 28 13:25:40 2020
+* Created: Wed Sep 2 11:07:52 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/fah/sky130_fd_sc_ls__fah_2.lvs.report b/cells/fah/sky130_fd_sc_ls__fah_2.lvs.report
new file mode 100644
index 0000000..15f641f
--- /dev/null
+++ b/cells/fah/sky130_fd_sc_ls__fah_2.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__fah_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__fah_2.sp ('sky130_fd_sc_ls__fah_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/fah/sky130_fd_sc_ls__fah_2.spice ('sky130_fd_sc_ls__fah_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:07:56 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__fah_2 sky130_fd_sc_ls__fah_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__fah_2
+SOURCE CELL NAME: sky130_fd_sc_ls__fah_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 19 19
+
+ Instances: 18 18 MN (4 pins)
+ 18 18 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 37 36
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 19 19
+
+ Instances: 16 16 MN (4 pins)
+ 16 16 MP (4 pins)
+ ------ ------
+ Total Inst: 32 32
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 19 19 0 0
+
+ Instances: 16 16 0 0 MN(NSHORT)
+ 16 16 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 32 32 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 8 layout mos transistors were reduced to 4.
+ 4 mos transistors were deleted by parallel reduction.
+ 8 source mos transistors were reduced to 4.
+ 4 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A B CI VPWR COUT SUM VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/fah/sky130_fd_sc_ls__fah_2.pex.spice b/cells/fah/sky130_fd_sc_ls__fah_2.pex.spice
index e333755..bec148e 100644
--- a/cells/fah/sky130_fd_sc_ls__fah_2.pex.spice
+++ b/cells/fah/sky130_fd_sc_ls__fah_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__fah_2.pex.spice
-* Created: Fri Aug 28 13:25:50 2020
+* Created: Wed Sep 2 11:07:59 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/fah/sky130_fd_sc_ls__fah_2.pxi.spice b/cells/fah/sky130_fd_sc_ls__fah_2.pxi.spice
index af16656..3d49a1a 100644
--- a/cells/fah/sky130_fd_sc_ls__fah_2.pxi.spice
+++ b/cells/fah/sky130_fd_sc_ls__fah_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__fah_2.pxi.spice
-* Created: Fri Aug 28 13:25:50 2020
+* Created: Wed Sep 2 11:07:59 2020
*
x_PM_SKY130_FD_SC_LS__FAH_2%A_81_260# N_A_81_260#_M1012_s N_A_81_260#_M1016_s
+ N_A_81_260#_c_258_n N_A_81_260#_M1030_g N_A_81_260#_M1034_g
diff --git a/cells/fah/sky130_fd_sc_ls__fah_2.spice b/cells/fah/sky130_fd_sc_ls__fah_2.spice
index 4f2a753..f97d343 100644
--- a/cells/fah/sky130_fd_sc_ls__fah_2.spice
+++ b/cells/fah/sky130_fd_sc_ls__fah_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__fah_2.spice
-* Created: Fri Aug 28 13:25:50 2020
+* Created: Wed Sep 2 11:07:59 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/fah/sky130_fd_sc_ls__fah_4.lvs.report b/cells/fah/sky130_fd_sc_ls__fah_4.lvs.report
new file mode 100644
index 0000000..6f0ac36
--- /dev/null
+++ b/cells/fah/sky130_fd_sc_ls__fah_4.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__fah_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__fah_4.sp ('sky130_fd_sc_ls__fah_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/fah/sky130_fd_sc_ls__fah_4.spice ('sky130_fd_sc_ls__fah_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:08:03 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__fah_4 sky130_fd_sc_ls__fah_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__fah_4
+SOURCE CELL NAME: sky130_fd_sc_ls__fah_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 19 19
+
+ Instances: 22 22 MN (4 pins)
+ 22 22 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 45 44
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 19 19
+
+ Instances: 16 16 MN (4 pins)
+ 16 16 MP (4 pins)
+ ------ ------
+ Total Inst: 32 32
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 19 19 0 0
+
+ Instances: 16 16 0 0 MN(NSHORT)
+ 16 16 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 32 32 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 16 layout mos transistors were reduced to 4.
+ 12 mos transistors were deleted by parallel reduction.
+ 16 source mos transistors were reduced to 4.
+ 12 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A B CI VPWR COUT SUM VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 1 sec
+Total Elapsed Time: 1 sec
diff --git a/cells/fah/sky130_fd_sc_ls__fah_4.pex.spice b/cells/fah/sky130_fd_sc_ls__fah_4.pex.spice
index 1b5c82c..3dcebb8 100644
--- a/cells/fah/sky130_fd_sc_ls__fah_4.pex.spice
+++ b/cells/fah/sky130_fd_sc_ls__fah_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__fah_4.pex.spice
-* Created: Fri Aug 28 13:26:06 2020
+* Created: Wed Sep 2 11:08:07 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/fah/sky130_fd_sc_ls__fah_4.pxi.spice b/cells/fah/sky130_fd_sc_ls__fah_4.pxi.spice
index 388ea13..be42f19 100644
--- a/cells/fah/sky130_fd_sc_ls__fah_4.pxi.spice
+++ b/cells/fah/sky130_fd_sc_ls__fah_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__fah_4.pxi.spice
-* Created: Fri Aug 28 13:26:06 2020
+* Created: Wed Sep 2 11:08:07 2020
*
x_PM_SKY130_FD_SC_LS__FAH_4%A N_A_M1037_g N_A_c_309_n N_A_M1034_g N_A_M1038_g
+ N_A_c_310_n N_A_M1032_g A N_A_c_307_n N_A_c_308_n PM_SKY130_FD_SC_LS__FAH_4%A
diff --git a/cells/fah/sky130_fd_sc_ls__fah_4.spice b/cells/fah/sky130_fd_sc_ls__fah_4.spice
index 94a5c41..c9ad1d3 100644
--- a/cells/fah/sky130_fd_sc_ls__fah_4.spice
+++ b/cells/fah/sky130_fd_sc_ls__fah_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__fah_4.spice
-* Created: Fri Aug 28 13:26:06 2020
+* Created: Wed Sep 2 11:08:07 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/fahcin/sky130_fd_sc_ls__fahcin_1.lvs.report b/cells/fahcin/sky130_fd_sc_ls__fahcin_1.lvs.report
new file mode 100644
index 0000000..76f3e84
--- /dev/null
+++ b/cells/fahcin/sky130_fd_sc_ls__fahcin_1.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__fahcin_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__fahcin_1.sp ('sky130_fd_sc_ls__fahcin_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/fahcin/sky130_fd_sc_ls__fahcin_1.spice ('sky130_fd_sc_ls__fahcin_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:08:11 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__fahcin_1 sky130_fd_sc_ls__fahcin_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__fahcin_1
+SOURCE CELL NAME: sky130_fd_sc_ls__fahcin_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 19 19
+
+ Instances: 16 16 MN (4 pins)
+ 16 16 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 33 32
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 19 19
+
+ Instances: 16 16 MN (4 pins)
+ 16 16 MP (4 pins)
+ ------ ------
+ Total Inst: 32 32
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 19 19 0 0
+
+ Instances: 16 16 0 0 MN(NSHORT)
+ 16 16 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 32 32 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A B CIN VPWR COUT SUM VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/fahcin/sky130_fd_sc_ls__fahcin_1.pex.spice b/cells/fahcin/sky130_fd_sc_ls__fahcin_1.pex.spice
index f45ddc8..34c253d 100644
--- a/cells/fahcin/sky130_fd_sc_ls__fahcin_1.pex.spice
+++ b/cells/fahcin/sky130_fd_sc_ls__fahcin_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__fahcin_1.pex.spice
-* Created: Fri Aug 28 13:26:23 2020
+* Created: Wed Sep 2 11:08:14 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/fahcin/sky130_fd_sc_ls__fahcin_1.pxi.spice b/cells/fahcin/sky130_fd_sc_ls__fahcin_1.pxi.spice
index 011c8bf..0f313c1 100644
--- a/cells/fahcin/sky130_fd_sc_ls__fahcin_1.pxi.spice
+++ b/cells/fahcin/sky130_fd_sc_ls__fahcin_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__fahcin_1.pxi.spice
-* Created: Fri Aug 28 13:26:23 2020
+* Created: Wed Sep 2 11:08:14 2020
*
x_PM_SKY130_FD_SC_LS__FAHCIN_1%A N_A_M1016_g N_A_c_238_n N_A_M1009_g A
+ N_A_c_239_n PM_SKY130_FD_SC_LS__FAHCIN_1%A
diff --git a/cells/fahcin/sky130_fd_sc_ls__fahcin_1.spice b/cells/fahcin/sky130_fd_sc_ls__fahcin_1.spice
index 86d377e..fa7ea26 100644
--- a/cells/fahcin/sky130_fd_sc_ls__fahcin_1.spice
+++ b/cells/fahcin/sky130_fd_sc_ls__fahcin_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__fahcin_1.spice
-* Created: Fri Aug 28 13:26:23 2020
+* Created: Wed Sep 2 11:08:14 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/fahcon/sky130_fd_sc_ls__fahcon_1.lvs.report b/cells/fahcon/sky130_fd_sc_ls__fahcon_1.lvs.report
new file mode 100644
index 0000000..4a7e281
--- /dev/null
+++ b/cells/fahcon/sky130_fd_sc_ls__fahcon_1.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__fahcon_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__fahcon_1.sp ('sky130_fd_sc_ls__fahcon_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/fahcon/sky130_fd_sc_ls__fahcon_1.spice ('sky130_fd_sc_ls__fahcon_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:08:18 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__fahcon_1 sky130_fd_sc_ls__fahcon_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__fahcon_1
+SOURCE CELL NAME: sky130_fd_sc_ls__fahcon_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 19 19
+
+ Instances: 16 16 MN (4 pins)
+ 16 16 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 33 32
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 19 19
+
+ Instances: 16 16 MN (4 pins)
+ 16 16 MP (4 pins)
+ ------ ------
+ Total Inst: 32 32
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 19 19 0 0
+
+ Instances: 16 16 0 0 MN(NSHORT)
+ 16 16 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 32 32 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A B CI VPWR COUT_N SUM VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/fahcon/sky130_fd_sc_ls__fahcon_1.pex.spice b/cells/fahcon/sky130_fd_sc_ls__fahcon_1.pex.spice
index a6ccdf4..01f0652 100644
--- a/cells/fahcon/sky130_fd_sc_ls__fahcon_1.pex.spice
+++ b/cells/fahcon/sky130_fd_sc_ls__fahcon_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__fahcon_1.pex.spice
-* Created: Fri Aug 28 13:26:36 2020
+* Created: Wed Sep 2 11:08:21 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/fahcon/sky130_fd_sc_ls__fahcon_1.pxi.spice b/cells/fahcon/sky130_fd_sc_ls__fahcon_1.pxi.spice
index 367a438..6ad9382 100644
--- a/cells/fahcon/sky130_fd_sc_ls__fahcon_1.pxi.spice
+++ b/cells/fahcon/sky130_fd_sc_ls__fahcon_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__fahcon_1.pxi.spice
-* Created: Fri Aug 28 13:26:36 2020
+* Created: Wed Sep 2 11:08:21 2020
*
x_PM_SKY130_FD_SC_LS__FAHCON_1%A N_A_c_227_n N_A_M1013_g N_A_c_228_n N_A_M1022_g
+ A PM_SKY130_FD_SC_LS__FAHCON_1%A
diff --git a/cells/fahcon/sky130_fd_sc_ls__fahcon_1.spice b/cells/fahcon/sky130_fd_sc_ls__fahcon_1.spice
index 855ee62..4dc85b7 100644
--- a/cells/fahcon/sky130_fd_sc_ls__fahcon_1.spice
+++ b/cells/fahcon/sky130_fd_sc_ls__fahcon_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__fahcon_1.spice
-* Created: Fri Aug 28 13:26:36 2020
+* Created: Wed Sep 2 11:08:21 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/fill/sky130_fd_sc_ls__fill_1.lvs.report b/cells/fill/sky130_fd_sc_ls__fill_1.lvs.report
new file mode 100644
index 0000000..0eac6da
--- /dev/null
+++ b/cells/fill/sky130_fd_sc_ls__fill_1.lvs.report
@@ -0,0 +1,375 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__fill_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__fill_1.sp ('sky130_fd_sc_ls__fill_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/fill/sky130_fd_sc_ls__fill_1.spice ('sky130_fd_sc_ls__fill_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:08:25 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # # ########################
+ # # # #
+ # # NOT COMPARED #
+ # # # #
+ # # ########################
+
+
+ Error: Nothing in source.
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/fill/sky130_fd_sc_ls__fill_2.lvs.report b/cells/fill/sky130_fd_sc_ls__fill_2.lvs.report
new file mode 100644
index 0000000..88f7c57
--- /dev/null
+++ b/cells/fill/sky130_fd_sc_ls__fill_2.lvs.report
@@ -0,0 +1,375 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__fill_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__fill_2.sp ('sky130_fd_sc_ls__fill_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/fill/sky130_fd_sc_ls__fill_2.spice ('sky130_fd_sc_ls__fill_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:08:28 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # # ########################
+ # # # #
+ # # NOT COMPARED #
+ # # # #
+ # # ########################
+
+
+ Error: Nothing in source.
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/fill/sky130_fd_sc_ls__fill_4.lvs.report b/cells/fill/sky130_fd_sc_ls__fill_4.lvs.report
new file mode 100644
index 0000000..a43d433
--- /dev/null
+++ b/cells/fill/sky130_fd_sc_ls__fill_4.lvs.report
@@ -0,0 +1,375 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__fill_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__fill_4.sp ('sky130_fd_sc_ls__fill_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/fill/sky130_fd_sc_ls__fill_4.spice ('sky130_fd_sc_ls__fill_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:08:32 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # # ########################
+ # # # #
+ # # NOT COMPARED #
+ # # # #
+ # # ########################
+
+
+ Error: Nothing in source.
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/fill/sky130_fd_sc_ls__fill_8.lvs.report b/cells/fill/sky130_fd_sc_ls__fill_8.lvs.report
new file mode 100644
index 0000000..bb156b0
--- /dev/null
+++ b/cells/fill/sky130_fd_sc_ls__fill_8.lvs.report
@@ -0,0 +1,375 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__fill_8.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__fill_8.sp ('sky130_fd_sc_ls__fill_8')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/fill/sky130_fd_sc_ls__fill_8.spice ('sky130_fd_sc_ls__fill_8')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:08:35 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # # ########################
+ # # # #
+ # # NOT COMPARED #
+ # # # #
+ # # ########################
+
+
+ Error: Nothing in source.
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/fill_diode/sky130_fd_sc_ls__fill_diode_2.lvs.report b/cells/fill_diode/sky130_fd_sc_ls__fill_diode_2.lvs.report
new file mode 100644
index 0000000..87093dd
--- /dev/null
+++ b/cells/fill_diode/sky130_fd_sc_ls__fill_diode_2.lvs.report
@@ -0,0 +1,375 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__fill_diode_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__fill_diode_2.sp ('sky130_fd_sc_ls__fill_diode_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/fill_diode/sky130_fd_sc_ls__fill_diode_2.spice ('sky130_fd_sc_ls__fill_diode_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:08:38 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # # ########################
+ # # # #
+ # # NOT COMPARED #
+ # # # #
+ # # ########################
+
+
+ Error: Nothing in source.
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/fill_diode/sky130_fd_sc_ls__fill_diode_4.lvs.report b/cells/fill_diode/sky130_fd_sc_ls__fill_diode_4.lvs.report
new file mode 100644
index 0000000..b40a132
--- /dev/null
+++ b/cells/fill_diode/sky130_fd_sc_ls__fill_diode_4.lvs.report
@@ -0,0 +1,375 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__fill_diode_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__fill_diode_4.sp ('sky130_fd_sc_ls__fill_diode_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/fill_diode/sky130_fd_sc_ls__fill_diode_4.spice ('sky130_fd_sc_ls__fill_diode_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:08:41 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # # ########################
+ # # # #
+ # # NOT COMPARED #
+ # # # #
+ # # ########################
+
+
+ Error: Nothing in source.
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/fill_diode/sky130_fd_sc_ls__fill_diode_8.lvs.report b/cells/fill_diode/sky130_fd_sc_ls__fill_diode_8.lvs.report
new file mode 100644
index 0000000..86eb4e2
--- /dev/null
+++ b/cells/fill_diode/sky130_fd_sc_ls__fill_diode_8.lvs.report
@@ -0,0 +1,375 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__fill_diode_8.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__fill_diode_8.sp ('sky130_fd_sc_ls__fill_diode_8')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/fill_diode/sky130_fd_sc_ls__fill_diode_8.spice ('sky130_fd_sc_ls__fill_diode_8')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:08:44 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # # ########################
+ # # # #
+ # # NOT COMPARED #
+ # # # #
+ # # ########################
+
+
+ Error: Nothing in source.
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/ha/sky130_fd_sc_ls__ha_1.lvs.report b/cells/ha/sky130_fd_sc_ls__ha_1.lvs.report
new file mode 100644
index 0000000..21f091a
--- /dev/null
+++ b/cells/ha/sky130_fd_sc_ls__ha_1.lvs.report
@@ -0,0 +1,470 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__ha_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__ha_1.sp ('sky130_fd_sc_ls__ha_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/ha/sky130_fd_sc_ls__ha_1.spice ('sky130_fd_sc_ls__ha_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:08:47 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__ha_1 sky130_fd_sc_ls__ha_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__ha_1
+SOURCE CELL NAME: sky130_fd_sc_ls__ha_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 13 13
+
+ Instances: 7 7 MN (4 pins)
+ 7 7 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 15 14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 10 10
+
+ Instances: 2 2 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1 (5 pins)
+ ------ ------
+ Total Inst: 10 10
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 5 5 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1
+ ------- ------- --------- ---------
+ Total Inst: 10 10 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B A SUM VPWR COUT VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/ha/sky130_fd_sc_ls__ha_1.pex.spice b/cells/ha/sky130_fd_sc_ls__ha_1.pex.spice
index dfb6eed..2efaea3 100644
--- a/cells/ha/sky130_fd_sc_ls__ha_1.pex.spice
+++ b/cells/ha/sky130_fd_sc_ls__ha_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__ha_1.pex.spice
-* Created: Fri Aug 28 13:27:17 2020
+* Created: Wed Sep 2 11:08:50 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/ha/sky130_fd_sc_ls__ha_1.pxi.spice b/cells/ha/sky130_fd_sc_ls__ha_1.pxi.spice
index 5b07954..55dc5bc 100644
--- a/cells/ha/sky130_fd_sc_ls__ha_1.pxi.spice
+++ b/cells/ha/sky130_fd_sc_ls__ha_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__ha_1.pxi.spice
-* Created: Fri Aug 28 13:27:17 2020
+* Created: Wed Sep 2 11:08:50 2020
*
x_PM_SKY130_FD_SC_LS__HA_1%A_83_260# N_A_83_260#_M1007_s N_A_83_260#_M1002_d
+ N_A_83_260#_M1011_g N_A_83_260#_c_89_n N_A_83_260#_M1006_g N_A_83_260#_c_90_n
diff --git a/cells/ha/sky130_fd_sc_ls__ha_1.spice b/cells/ha/sky130_fd_sc_ls__ha_1.spice
index a40187e..ecd9520 100644
--- a/cells/ha/sky130_fd_sc_ls__ha_1.spice
+++ b/cells/ha/sky130_fd_sc_ls__ha_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__ha_1.spice
-* Created: Fri Aug 28 13:27:17 2020
+* Created: Wed Sep 2 11:08:50 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/ha/sky130_fd_sc_ls__ha_2.lvs.report b/cells/ha/sky130_fd_sc_ls__ha_2.lvs.report
new file mode 100644
index 0000000..c5e397c
--- /dev/null
+++ b/cells/ha/sky130_fd_sc_ls__ha_2.lvs.report
@@ -0,0 +1,475 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__ha_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__ha_2.sp ('sky130_fd_sc_ls__ha_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/ha/sky130_fd_sc_ls__ha_2.spice ('sky130_fd_sc_ls__ha_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:08:54 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__ha_2 sky130_fd_sc_ls__ha_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__ha_2
+SOURCE CELL NAME: sky130_fd_sc_ls__ha_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 13 13
+
+ Instances: 9 9 MN (4 pins)
+ 9 9 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 19 18
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 10 10
+
+ Instances: 2 2 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1 (5 pins)
+ ------ ------
+ Total Inst: 10 10
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 5 5 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1
+ ------- ------- --------- ---------
+ Total Inst: 10 10 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 8 layout mos transistors were reduced to 4.
+ 4 mos transistors were deleted by parallel reduction.
+ 8 source mos transistors were reduced to 4.
+ 4 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B A VPWR SUM COUT VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/ha/sky130_fd_sc_ls__ha_2.pex.spice b/cells/ha/sky130_fd_sc_ls__ha_2.pex.spice
index 4cf71c2..6a551bc 100644
--- a/cells/ha/sky130_fd_sc_ls__ha_2.pex.spice
+++ b/cells/ha/sky130_fd_sc_ls__ha_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__ha_2.pex.spice
-* Created: Fri Aug 28 13:27:36 2020
+* Created: Wed Sep 2 11:08:57 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/ha/sky130_fd_sc_ls__ha_2.pxi.spice b/cells/ha/sky130_fd_sc_ls__ha_2.pxi.spice
index 2f6f850..782d389 100644
--- a/cells/ha/sky130_fd_sc_ls__ha_2.pxi.spice
+++ b/cells/ha/sky130_fd_sc_ls__ha_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__ha_2.pxi.spice
-* Created: Fri Aug 28 13:27:36 2020
+* Created: Wed Sep 2 11:08:57 2020
*
x_PM_SKY130_FD_SC_LS__HA_2%B N_B_M1013_g N_B_M1005_g N_B_c_103_n N_B_M1009_g
+ N_B_c_104_n N_B_M1016_g N_B_c_105_n N_B_c_112_n N_B_c_106_n N_B_c_107_n
diff --git a/cells/ha/sky130_fd_sc_ls__ha_2.spice b/cells/ha/sky130_fd_sc_ls__ha_2.spice
index 51963dd..6168fef 100644
--- a/cells/ha/sky130_fd_sc_ls__ha_2.spice
+++ b/cells/ha/sky130_fd_sc_ls__ha_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__ha_2.spice
-* Created: Fri Aug 28 13:27:36 2020
+* Created: Wed Sep 2 11:08:57 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/ha/sky130_fd_sc_ls__ha_4.lvs.report b/cells/ha/sky130_fd_sc_ls__ha_4.lvs.report
new file mode 100644
index 0000000..4efc41a
--- /dev/null
+++ b/cells/ha/sky130_fd_sc_ls__ha_4.lvs.report
@@ -0,0 +1,475 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__ha_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__ha_4.sp ('sky130_fd_sc_ls__ha_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/ha/sky130_fd_sc_ls__ha_4.spice ('sky130_fd_sc_ls__ha_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:09:01 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__ha_4 sky130_fd_sc_ls__ha_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__ha_4
+SOURCE CELL NAME: sky130_fd_sc_ls__ha_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 13 13
+
+ Instances: 18 18 MN (4 pins)
+ 18 18 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 37 36
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 10 10
+
+ Instances: 2 2 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1 (5 pins)
+ ------ ------
+ Total Inst: 10 10
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 5 5 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1
+ ------- ------- --------- ---------
+ Total Inst: 10 10 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 36 layout mos transistors were reduced to 14.
+ 22 mos transistors were deleted by parallel reduction.
+ 36 source mos transistors were reduced to 14.
+ 22 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B A VPWR COUT SUM VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/ha/sky130_fd_sc_ls__ha_4.pex.spice b/cells/ha/sky130_fd_sc_ls__ha_4.pex.spice
index 0760ae7..1970549 100644
--- a/cells/ha/sky130_fd_sc_ls__ha_4.pex.spice
+++ b/cells/ha/sky130_fd_sc_ls__ha_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__ha_4.pex.spice
-* Created: Fri Aug 28 13:27:46 2020
+* Created: Wed Sep 2 11:09:05 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/ha/sky130_fd_sc_ls__ha_4.pxi.spice b/cells/ha/sky130_fd_sc_ls__ha_4.pxi.spice
index 741fc52..8744ffb 100644
--- a/cells/ha/sky130_fd_sc_ls__ha_4.pxi.spice
+++ b/cells/ha/sky130_fd_sc_ls__ha_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__ha_4.pxi.spice
-* Created: Fri Aug 28 13:27:46 2020
+* Created: Wed Sep 2 11:09:05 2020
*
x_PM_SKY130_FD_SC_LS__HA_4%A_435_99# N_A_435_99#_M1001_s N_A_435_99#_M1012_s
+ N_A_435_99#_M1018_s N_A_435_99#_c_195_n N_A_435_99#_M1022_g
diff --git a/cells/ha/sky130_fd_sc_ls__ha_4.spice b/cells/ha/sky130_fd_sc_ls__ha_4.spice
index 6c1690f..bc44c9a 100644
--- a/cells/ha/sky130_fd_sc_ls__ha_4.spice
+++ b/cells/ha/sky130_fd_sc_ls__ha_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__ha_4.spice
-* Created: Fri Aug 28 13:27:46 2020
+* Created: Wed Sep 2 11:09:05 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/inv/sky130_fd_sc_ls__inv_1.lvs.report b/cells/inv/sky130_fd_sc_ls__inv_1.lvs.report
new file mode 100644
index 0000000..d95479b
--- /dev/null
+++ b/cells/inv/sky130_fd_sc_ls__inv_1.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__inv_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__inv_1.sp ('sky130_fd_sc_ls__inv_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/inv/sky130_fd_sc_ls__inv_1.spice ('sky130_fd_sc_ls__inv_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:09:16 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__inv_1 sky130_fd_sc_ls__inv_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__inv_1
+SOURCE CELL NAME: sky130_fd_sc_ls__inv_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 6 6
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 3 2
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 6 6
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ ------ ------
+ Total Inst: 2 2
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 6 6 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 2 2 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/inv/sky130_fd_sc_ls__inv_1.pex.spice b/cells/inv/sky130_fd_sc_ls__inv_1.pex.spice
index 10fc288..7b3a7d9 100644
--- a/cells/inv/sky130_fd_sc_ls__inv_1.pex.spice
+++ b/cells/inv/sky130_fd_sc_ls__inv_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__inv_1.pex.spice
-* Created: Fri Aug 28 13:28:04 2020
+* Created: Wed Sep 2 11:09:19 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/inv/sky130_fd_sc_ls__inv_1.pxi.spice b/cells/inv/sky130_fd_sc_ls__inv_1.pxi.spice
index f29b77e..46ad24c 100644
--- a/cells/inv/sky130_fd_sc_ls__inv_1.pxi.spice
+++ b/cells/inv/sky130_fd_sc_ls__inv_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__inv_1.pxi.spice
-* Created: Fri Aug 28 13:28:04 2020
+* Created: Wed Sep 2 11:09:19 2020
*
x_PM_SKY130_FD_SC_LS__INV_1%A N_A_c_25_n N_A_M1000_g N_A_M1001_g N_A_c_22_n
+ N_A_c_23_n A N_A_c_24_n PM_SKY130_FD_SC_LS__INV_1%A
diff --git a/cells/inv/sky130_fd_sc_ls__inv_1.spice b/cells/inv/sky130_fd_sc_ls__inv_1.spice
index 3344a35..be781a8 100644
--- a/cells/inv/sky130_fd_sc_ls__inv_1.spice
+++ b/cells/inv/sky130_fd_sc_ls__inv_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__inv_1.spice
-* Created: Fri Aug 28 13:28:04 2020
+* Created: Wed Sep 2 11:09:19 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/inv/sky130_fd_sc_ls__inv_16.lvs.report b/cells/inv/sky130_fd_sc_ls__inv_16.lvs.report
new file mode 100644
index 0000000..47a5d14
--- /dev/null
+++ b/cells/inv/sky130_fd_sc_ls__inv_16.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__inv_16.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__inv_16.sp ('sky130_fd_sc_ls__inv_16')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/inv/sky130_fd_sc_ls__inv_16.spice ('sky130_fd_sc_ls__inv_16')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:09:09 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__inv_16 sky130_fd_sc_ls__inv_16
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__inv_16
+SOURCE CELL NAME: sky130_fd_sc_ls__inv_16
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 6 6
+
+ Instances: 16 16 MN (4 pins)
+ 16 16 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 33 32
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 6 6
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ ------ ------
+ Total Inst: 2 2
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 6 6 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 2 2 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 32 layout mos transistors were reduced to 2.
+ 30 mos transistors were deleted by parallel reduction.
+ 32 source mos transistors were reduced to 2.
+ 30 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/inv/sky130_fd_sc_ls__inv_16.pex.spice b/cells/inv/sky130_fd_sc_ls__inv_16.pex.spice
index dad5bca..a94c323 100644
--- a/cells/inv/sky130_fd_sc_ls__inv_16.pex.spice
+++ b/cells/inv/sky130_fd_sc_ls__inv_16.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__inv_16.pex.spice
-* Created: Fri Aug 28 13:27:55 2020
+* Created: Wed Sep 2 11:09:12 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/inv/sky130_fd_sc_ls__inv_16.pxi.spice b/cells/inv/sky130_fd_sc_ls__inv_16.pxi.spice
index 51d0ed9..6171b66 100644
--- a/cells/inv/sky130_fd_sc_ls__inv_16.pxi.spice
+++ b/cells/inv/sky130_fd_sc_ls__inv_16.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__inv_16.pxi.spice
-* Created: Fri Aug 28 13:27:55 2020
+* Created: Wed Sep 2 11:09:12 2020
*
x_PM_SKY130_FD_SC_LS__INV_16%A N_A_c_161_n N_A_M1000_g N_A_M1002_g N_A_c_162_n
+ N_A_M1001_g N_A_M1003_g N_A_c_163_n N_A_M1004_g N_A_M1005_g N_A_c_164_n
diff --git a/cells/inv/sky130_fd_sc_ls__inv_16.spice b/cells/inv/sky130_fd_sc_ls__inv_16.spice
index 78d6b8f..1a8849c 100644
--- a/cells/inv/sky130_fd_sc_ls__inv_16.spice
+++ b/cells/inv/sky130_fd_sc_ls__inv_16.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__inv_16.spice
-* Created: Fri Aug 28 13:27:55 2020
+* Created: Wed Sep 2 11:09:12 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/inv/sky130_fd_sc_ls__inv_2.lvs.report b/cells/inv/sky130_fd_sc_ls__inv_2.lvs.report
new file mode 100644
index 0000000..73735ab
--- /dev/null
+++ b/cells/inv/sky130_fd_sc_ls__inv_2.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__inv_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__inv_2.sp ('sky130_fd_sc_ls__inv_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/inv/sky130_fd_sc_ls__inv_2.spice ('sky130_fd_sc_ls__inv_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:09:23 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__inv_2 sky130_fd_sc_ls__inv_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__inv_2
+SOURCE CELL NAME: sky130_fd_sc_ls__inv_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 6 6
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 5 4
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 6 6
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ ------ ------
+ Total Inst: 2 2
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 6 6 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 2 2 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/inv/sky130_fd_sc_ls__inv_2.pex.spice b/cells/inv/sky130_fd_sc_ls__inv_2.pex.spice
index 7cd4cd6..cf26a4e 100644
--- a/cells/inv/sky130_fd_sc_ls__inv_2.pex.spice
+++ b/cells/inv/sky130_fd_sc_ls__inv_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__inv_2.pex.spice
-* Created: Fri Aug 28 13:28:20 2020
+* Created: Wed Sep 2 11:09:26 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/inv/sky130_fd_sc_ls__inv_2.pxi.spice b/cells/inv/sky130_fd_sc_ls__inv_2.pxi.spice
index e5a3572..8e40d94 100644
--- a/cells/inv/sky130_fd_sc_ls__inv_2.pxi.spice
+++ b/cells/inv/sky130_fd_sc_ls__inv_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__inv_2.pxi.spice
-* Created: Fri Aug 28 13:28:20 2020
+* Created: Wed Sep 2 11:09:26 2020
*
x_PM_SKY130_FD_SC_LS__INV_2%A N_A_c_29_n N_A_M1000_g N_A_M1002_g N_A_c_31_n
+ N_A_c_32_n N_A_M1003_g N_A_c_38_n N_A_M1001_g N_A_c_34_n A N_A_c_35_n
diff --git a/cells/inv/sky130_fd_sc_ls__inv_2.spice b/cells/inv/sky130_fd_sc_ls__inv_2.spice
index 4ed02a8..8076278 100644
--- a/cells/inv/sky130_fd_sc_ls__inv_2.spice
+++ b/cells/inv/sky130_fd_sc_ls__inv_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__inv_2.spice
-* Created: Fri Aug 28 13:28:20 2020
+* Created: Wed Sep 2 11:09:26 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/inv/sky130_fd_sc_ls__inv_4.lvs.report b/cells/inv/sky130_fd_sc_ls__inv_4.lvs.report
new file mode 100644
index 0000000..8a56187
--- /dev/null
+++ b/cells/inv/sky130_fd_sc_ls__inv_4.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__inv_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__inv_4.sp ('sky130_fd_sc_ls__inv_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/inv/sky130_fd_sc_ls__inv_4.spice ('sky130_fd_sc_ls__inv_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:09:30 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__inv_4 sky130_fd_sc_ls__inv_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__inv_4
+SOURCE CELL NAME: sky130_fd_sc_ls__inv_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 6 6
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 6 6
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ ------ ------
+ Total Inst: 2 2
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 6 6 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 2 2 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 8 layout mos transistors were reduced to 2.
+ 6 mos transistors were deleted by parallel reduction.
+ 8 source mos transistors were reduced to 2.
+ 6 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 1 sec
+Total Elapsed Time: 1 sec
diff --git a/cells/inv/sky130_fd_sc_ls__inv_4.pex.spice b/cells/inv/sky130_fd_sc_ls__inv_4.pex.spice
index 5961f28..9e57322 100644
--- a/cells/inv/sky130_fd_sc_ls__inv_4.pex.spice
+++ b/cells/inv/sky130_fd_sc_ls__inv_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__inv_4.pex.spice
-* Created: Fri Aug 28 13:28:39 2020
+* Created: Wed Sep 2 11:09:34 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/inv/sky130_fd_sc_ls__inv_4.pxi.spice b/cells/inv/sky130_fd_sc_ls__inv_4.pxi.spice
index 80a72c9..80586af 100644
--- a/cells/inv/sky130_fd_sc_ls__inv_4.pxi.spice
+++ b/cells/inv/sky130_fd_sc_ls__inv_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__inv_4.pxi.spice
-* Created: Fri Aug 28 13:28:39 2020
+* Created: Wed Sep 2 11:09:34 2020
*
x_PM_SKY130_FD_SC_LS__INV_4%A N_A_M1001_g N_A_c_49_n N_A_M1000_g N_A_c_50_n
+ N_A_M1002_g N_A_M1003_g N_A_c_51_n N_A_M1006_g N_A_M1004_g N_A_c_52_n
diff --git a/cells/inv/sky130_fd_sc_ls__inv_4.spice b/cells/inv/sky130_fd_sc_ls__inv_4.spice
index dccff38..49051e7 100644
--- a/cells/inv/sky130_fd_sc_ls__inv_4.spice
+++ b/cells/inv/sky130_fd_sc_ls__inv_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__inv_4.spice
-* Created: Fri Aug 28 13:28:39 2020
+* Created: Wed Sep 2 11:09:34 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/inv/sky130_fd_sc_ls__inv_8.lvs.report b/cells/inv/sky130_fd_sc_ls__inv_8.lvs.report
new file mode 100644
index 0000000..6f11287
--- /dev/null
+++ b/cells/inv/sky130_fd_sc_ls__inv_8.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__inv_8.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__inv_8.sp ('sky130_fd_sc_ls__inv_8')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/inv/sky130_fd_sc_ls__inv_8.spice ('sky130_fd_sc_ls__inv_8')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:09:38 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__inv_8 sky130_fd_sc_ls__inv_8
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__inv_8
+SOURCE CELL NAME: sky130_fd_sc_ls__inv_8
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 6 6
+
+ Instances: 8 8 MN (4 pins)
+ 8 8 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 17 16
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 6 6
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ ------ ------
+ Total Inst: 2 2
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 6 6 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 2 2 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 16 layout mos transistors were reduced to 2.
+ 14 mos transistors were deleted by parallel reduction.
+ 16 source mos transistors were reduced to 2.
+ 14 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/inv/sky130_fd_sc_ls__inv_8.pex.spice b/cells/inv/sky130_fd_sc_ls__inv_8.pex.spice
index fd05a2a..d6a7330 100644
--- a/cells/inv/sky130_fd_sc_ls__inv_8.pex.spice
+++ b/cells/inv/sky130_fd_sc_ls__inv_8.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__inv_8.pex.spice
-* Created: Fri Aug 28 13:28:49 2020
+* Created: Wed Sep 2 11:09:41 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/inv/sky130_fd_sc_ls__inv_8.pxi.spice b/cells/inv/sky130_fd_sc_ls__inv_8.pxi.spice
index 4b3644f..7652000 100644
--- a/cells/inv/sky130_fd_sc_ls__inv_8.pxi.spice
+++ b/cells/inv/sky130_fd_sc_ls__inv_8.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__inv_8.pxi.spice
-* Created: Fri Aug 28 13:28:49 2020
+* Created: Wed Sep 2 11:09:41 2020
*
x_PM_SKY130_FD_SC_LS__INV_8%A N_A_c_77_n N_A_M1000_g N_A_c_68_n N_A_M1001_g
+ N_A_c_69_n N_A_M1004_g N_A_c_78_n N_A_M1002_g N_A_M1005_g N_A_c_79_n
diff --git a/cells/inv/sky130_fd_sc_ls__inv_8.spice b/cells/inv/sky130_fd_sc_ls__inv_8.spice
index edcdfc7..0c9d686 100644
--- a/cells/inv/sky130_fd_sc_ls__inv_8.spice
+++ b/cells/inv/sky130_fd_sc_ls__inv_8.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__inv_8.spice
-* Created: Fri Aug 28 13:28:49 2020
+* Created: Wed Sep 2 11:09:41 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/maj3/sky130_fd_sc_ls__maj3_1.lvs.report b/cells/maj3/sky130_fd_sc_ls__maj3_1.lvs.report
new file mode 100644
index 0000000..6c23139
--- /dev/null
+++ b/cells/maj3/sky130_fd_sc_ls__maj3_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__maj3_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__maj3_1.sp ('sky130_fd_sc_ls__maj3_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/maj3/sky130_fd_sc_ls__maj3_1.spice ('sky130_fd_sc_ls__maj3_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:09:45 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__maj3_1 sky130_fd_sc_ls__maj3_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__maj3_1
+SOURCE CELL NAME: sky130_fd_sc_ls__maj3_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 15 15
+
+ Instances: 7 7 MN (4 pins)
+ 7 7 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 15 14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 9 9
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 3 3 SMN2 (4 pins)
+ 3 3 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 8 8
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 3 3 0 0 SMN2
+ 3 3 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 8 8 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B C A X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/maj3/sky130_fd_sc_ls__maj3_1.pex.spice b/cells/maj3/sky130_fd_sc_ls__maj3_1.pex.spice
index 83d8d68..5786423 100644
--- a/cells/maj3/sky130_fd_sc_ls__maj3_1.pex.spice
+++ b/cells/maj3/sky130_fd_sc_ls__maj3_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__maj3_1.pex.spice
-* Created: Fri Aug 28 13:28:59 2020
+* Created: Wed Sep 2 11:09:48 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/maj3/sky130_fd_sc_ls__maj3_1.pxi.spice b/cells/maj3/sky130_fd_sc_ls__maj3_1.pxi.spice
index 57440ab..718c0e3 100644
--- a/cells/maj3/sky130_fd_sc_ls__maj3_1.pxi.spice
+++ b/cells/maj3/sky130_fd_sc_ls__maj3_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__maj3_1.pxi.spice
-* Created: Fri Aug 28 13:28:59 2020
+* Created: Wed Sep 2 11:09:48 2020
*
x_PM_SKY130_FD_SC_LS__MAJ3_1%A_84_74# N_A_84_74#_M1004_d N_A_84_74#_M1008_d
+ N_A_84_74#_M1001_d N_A_84_74#_M1011_d N_A_84_74#_c_69_n N_A_84_74#_M1003_g
diff --git a/cells/maj3/sky130_fd_sc_ls__maj3_1.spice b/cells/maj3/sky130_fd_sc_ls__maj3_1.spice
index f323d2f..3d083ae 100644
--- a/cells/maj3/sky130_fd_sc_ls__maj3_1.spice
+++ b/cells/maj3/sky130_fd_sc_ls__maj3_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__maj3_1.spice
-* Created: Fri Aug 28 13:28:59 2020
+* Created: Wed Sep 2 11:09:48 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/maj3/sky130_fd_sc_ls__maj3_2.lvs.report b/cells/maj3/sky130_fd_sc_ls__maj3_2.lvs.report
new file mode 100644
index 0000000..0951357
--- /dev/null
+++ b/cells/maj3/sky130_fd_sc_ls__maj3_2.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__maj3_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__maj3_2.sp ('sky130_fd_sc_ls__maj3_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/maj3/sky130_fd_sc_ls__maj3_2.spice ('sky130_fd_sc_ls__maj3_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:09:52 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__maj3_2 sky130_fd_sc_ls__maj3_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__maj3_2
+SOURCE CELL NAME: sky130_fd_sc_ls__maj3_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 15 15
+
+ Instances: 8 8 MN (4 pins)
+ 8 8 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 17 16
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 9 9
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 3 3 SMN2 (4 pins)
+ 3 3 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 8 8
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 3 3 0 0 SMN2
+ 3 3 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 8 8 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B C A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/maj3/sky130_fd_sc_ls__maj3_2.pex.spice b/cells/maj3/sky130_fd_sc_ls__maj3_2.pex.spice
index 97aa3d2..a61508e 100644
--- a/cells/maj3/sky130_fd_sc_ls__maj3_2.pex.spice
+++ b/cells/maj3/sky130_fd_sc_ls__maj3_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__maj3_2.pex.spice
-* Created: Fri Aug 28 13:29:08 2020
+* Created: Wed Sep 2 11:09:55 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/maj3/sky130_fd_sc_ls__maj3_2.pxi.spice b/cells/maj3/sky130_fd_sc_ls__maj3_2.pxi.spice
index d302cd0..113fda1 100644
--- a/cells/maj3/sky130_fd_sc_ls__maj3_2.pxi.spice
+++ b/cells/maj3/sky130_fd_sc_ls__maj3_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__maj3_2.pxi.spice
-* Created: Fri Aug 28 13:29:08 2020
+* Created: Wed Sep 2 11:09:55 2020
*
x_PM_SKY130_FD_SC_LS__MAJ3_2%A_87_264# N_A_87_264#_M1009_d N_A_87_264#_M1012_d
+ N_A_87_264#_M1014_d N_A_87_264#_M1005_d N_A_87_264#_M1010_g N_A_87_264#_c_85_n
diff --git a/cells/maj3/sky130_fd_sc_ls__maj3_2.spice b/cells/maj3/sky130_fd_sc_ls__maj3_2.spice
index 738b3f9..cd28990 100644
--- a/cells/maj3/sky130_fd_sc_ls__maj3_2.spice
+++ b/cells/maj3/sky130_fd_sc_ls__maj3_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__maj3_2.spice
-* Created: Fri Aug 28 13:29:08 2020
+* Created: Wed Sep 2 11:09:55 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/maj3/sky130_fd_sc_ls__maj3_4.lvs.report b/cells/maj3/sky130_fd_sc_ls__maj3_4.lvs.report
new file mode 100644
index 0000000..7d0baa1
--- /dev/null
+++ b/cells/maj3/sky130_fd_sc_ls__maj3_4.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__maj3_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__maj3_4.sp ('sky130_fd_sc_ls__maj3_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/maj3/sky130_fd_sc_ls__maj3_4.spice ('sky130_fd_sc_ls__maj3_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:09:59 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__maj3_4 sky130_fd_sc_ls__maj3_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__maj3_4
+SOURCE CELL NAME: sky130_fd_sc_ls__maj3_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 15 15
+
+ Instances: 16 16 MN (4 pins)
+ 16 16 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 33 32
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 9 9
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 3 3 SMN2 (4 pins)
+ 3 3 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 8 8
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 3 3 0 0 SMN2
+ 3 3 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 8 8 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 32 layout mos transistors were reduced to 14.
+ 18 mos transistors were deleted by parallel reduction.
+ 32 source mos transistors were reduced to 14.
+ 18 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B A C VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/maj3/sky130_fd_sc_ls__maj3_4.pex.spice b/cells/maj3/sky130_fd_sc_ls__maj3_4.pex.spice
index 5147a5b..f2dcd02 100644
--- a/cells/maj3/sky130_fd_sc_ls__maj3_4.pex.spice
+++ b/cells/maj3/sky130_fd_sc_ls__maj3_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__maj3_4.pex.spice
-* Created: Fri Aug 28 13:29:25 2020
+* Created: Wed Sep 2 11:10:03 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/maj3/sky130_fd_sc_ls__maj3_4.pxi.spice b/cells/maj3/sky130_fd_sc_ls__maj3_4.pxi.spice
index 80f9891..d15fd98 100644
--- a/cells/maj3/sky130_fd_sc_ls__maj3_4.pxi.spice
+++ b/cells/maj3/sky130_fd_sc_ls__maj3_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__maj3_4.pxi.spice
-* Created: Fri Aug 28 13:29:25 2020
+* Created: Wed Sep 2 11:10:03 2020
*
x_PM_SKY130_FD_SC_LS__MAJ3_4%B N_B_c_152_n N_B_M1011_g N_B_c_144_n N_B_M1016_g
+ N_B_c_153_n N_B_M1022_g N_B_c_145_n N_B_M1023_g N_B_c_154_n N_B_M1001_g
diff --git a/cells/maj3/sky130_fd_sc_ls__maj3_4.spice b/cells/maj3/sky130_fd_sc_ls__maj3_4.spice
index da3e258..6b1c9f5 100644
--- a/cells/maj3/sky130_fd_sc_ls__maj3_4.spice
+++ b/cells/maj3/sky130_fd_sc_ls__maj3_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__maj3_4.spice
-* Created: Fri Aug 28 13:29:25 2020
+* Created: Wed Sep 2 11:10:03 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/mux2/sky130_fd_sc_ls__mux2_1.lvs.report b/cells/mux2/sky130_fd_sc_ls__mux2_1.lvs.report
new file mode 100644
index 0000000..5a0c693
--- /dev/null
+++ b/cells/mux2/sky130_fd_sc_ls__mux2_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__mux2_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__mux2_1.sp ('sky130_fd_sc_ls__mux2_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/mux2/sky130_fd_sc_ls__mux2_1.spice ('sky130_fd_sc_ls__mux2_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:10:07 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__mux2_1 sky130_fd_sc_ls__mux2_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__mux2_1
+SOURCE CELL NAME: sky130_fd_sc_ls__mux2_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 14 14
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 10 10
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 8 8
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 8 8 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB S A1 A0 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/mux2/sky130_fd_sc_ls__mux2_1.pex.spice b/cells/mux2/sky130_fd_sc_ls__mux2_1.pex.spice
index 7363141..b787b35 100644
--- a/cells/mux2/sky130_fd_sc_ls__mux2_1.pex.spice
+++ b/cells/mux2/sky130_fd_sc_ls__mux2_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__mux2_1.pex.spice
-* Created: Fri Aug 28 13:29:45 2020
+* Created: Wed Sep 2 11:10:10 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/mux2/sky130_fd_sc_ls__mux2_1.pxi.spice b/cells/mux2/sky130_fd_sc_ls__mux2_1.pxi.spice
index fe2ea9c..1fe8c21 100644
--- a/cells/mux2/sky130_fd_sc_ls__mux2_1.pxi.spice
+++ b/cells/mux2/sky130_fd_sc_ls__mux2_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__mux2_1.pxi.spice
-* Created: Fri Aug 28 13:29:45 2020
+* Created: Wed Sep 2 11:10:10 2020
*
x_PM_SKY130_FD_SC_LS__MUX2_1%S N_S_M1003_g N_S_c_78_n N_S_M1007_g N_S_c_79_n
+ N_S_M1010_g N_S_M1005_g N_S_c_74_n N_S_c_75_n N_S_c_76_n S N_S_c_77_n
diff --git a/cells/mux2/sky130_fd_sc_ls__mux2_1.spice b/cells/mux2/sky130_fd_sc_ls__mux2_1.spice
index 4bad6c3..7748fcb 100644
--- a/cells/mux2/sky130_fd_sc_ls__mux2_1.spice
+++ b/cells/mux2/sky130_fd_sc_ls__mux2_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__mux2_1.spice
-* Created: Fri Aug 28 13:29:45 2020
+* Created: Wed Sep 2 11:10:10 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/mux2/sky130_fd_sc_ls__mux2_2.lvs.report b/cells/mux2/sky130_fd_sc_ls__mux2_2.lvs.report
new file mode 100644
index 0000000..0cd07e5
--- /dev/null
+++ b/cells/mux2/sky130_fd_sc_ls__mux2_2.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__mux2_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__mux2_2.sp ('sky130_fd_sc_ls__mux2_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/mux2/sky130_fd_sc_ls__mux2_2.spice ('sky130_fd_sc_ls__mux2_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:10:14 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__mux2_2 sky130_fd_sc_ls__mux2_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__mux2_2
+SOURCE CELL NAME: sky130_fd_sc_ls__mux2_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 14 14
+
+ Instances: 7 7 MN (4 pins)
+ 7 7 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 15 14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 10 10
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 8 8
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 8 8 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A0 A1 S VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/mux2/sky130_fd_sc_ls__mux2_2.pex.spice b/cells/mux2/sky130_fd_sc_ls__mux2_2.pex.spice
index 2d39f85..3df7aa8 100644
--- a/cells/mux2/sky130_fd_sc_ls__mux2_2.pex.spice
+++ b/cells/mux2/sky130_fd_sc_ls__mux2_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__mux2_2.pex.spice
-* Created: Fri Aug 28 13:29:55 2020
+* Created: Wed Sep 2 11:10:17 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/mux2/sky130_fd_sc_ls__mux2_2.pxi.spice b/cells/mux2/sky130_fd_sc_ls__mux2_2.pxi.spice
index 44c489d..e4e70b3 100644
--- a/cells/mux2/sky130_fd_sc_ls__mux2_2.pxi.spice
+++ b/cells/mux2/sky130_fd_sc_ls__mux2_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__mux2_2.pxi.spice
-* Created: Fri Aug 28 13:29:55 2020
+* Created: Wed Sep 2 11:10:17 2020
*
x_PM_SKY130_FD_SC_LS__MUX2_2%A0 N_A0_c_93_n N_A0_M1008_g N_A0_c_94_n
+ N_A0_M1003_g A0 PM_SKY130_FD_SC_LS__MUX2_2%A0
diff --git a/cells/mux2/sky130_fd_sc_ls__mux2_2.spice b/cells/mux2/sky130_fd_sc_ls__mux2_2.spice
index 1657e6d..6e25c73 100644
--- a/cells/mux2/sky130_fd_sc_ls__mux2_2.spice
+++ b/cells/mux2/sky130_fd_sc_ls__mux2_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__mux2_2.spice
-* Created: Fri Aug 28 13:29:55 2020
+* Created: Wed Sep 2 11:10:17 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/mux2/sky130_fd_sc_ls__mux2_4.lvs.report b/cells/mux2/sky130_fd_sc_ls__mux2_4.lvs.report
new file mode 100644
index 0000000..5c919c4
--- /dev/null
+++ b/cells/mux2/sky130_fd_sc_ls__mux2_4.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__mux2_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__mux2_4.sp ('sky130_fd_sc_ls__mux2_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/mux2/sky130_fd_sc_ls__mux2_4.spice ('sky130_fd_sc_ls__mux2_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:10:21 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__mux2_4 sky130_fd_sc_ls__mux2_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__mux2_4
+SOURCE CELL NAME: sky130_fd_sc_ls__mux2_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 14 14
+
+ Instances: 13 13 MN (4 pins)
+ 13 13 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 27 26
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 10 10
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 8 8
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 8 8 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 24 layout mos transistors were reduced to 10.
+ 14 mos transistors were deleted by parallel reduction.
+ 24 source mos transistors were reduced to 10.
+ 14 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB S A0 A1 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/mux2/sky130_fd_sc_ls__mux2_4.pex.spice b/cells/mux2/sky130_fd_sc_ls__mux2_4.pex.spice
index 9423628..dc95071 100644
--- a/cells/mux2/sky130_fd_sc_ls__mux2_4.pex.spice
+++ b/cells/mux2/sky130_fd_sc_ls__mux2_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__mux2_4.pex.spice
-* Created: Fri Aug 28 13:30:05 2020
+* Created: Wed Sep 2 11:10:24 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/mux2/sky130_fd_sc_ls__mux2_4.pxi.spice b/cells/mux2/sky130_fd_sc_ls__mux2_4.pxi.spice
index f565017..f9048e4 100644
--- a/cells/mux2/sky130_fd_sc_ls__mux2_4.pxi.spice
+++ b/cells/mux2/sky130_fd_sc_ls__mux2_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__mux2_4.pxi.spice
-* Created: Fri Aug 28 13:30:05 2020
+* Created: Wed Sep 2 11:10:24 2020
*
x_PM_SKY130_FD_SC_LS__MUX2_4%S N_S_c_158_n N_S_M1012_g N_S_M1025_g N_S_M1020_g
+ N_S_c_167_n N_S_M1003_g N_S_M1023_g N_S_c_168_n N_S_M1019_g N_S_c_169_n
diff --git a/cells/mux2/sky130_fd_sc_ls__mux2_4.spice b/cells/mux2/sky130_fd_sc_ls__mux2_4.spice
index c24fcfe..98d221e 100644
--- a/cells/mux2/sky130_fd_sc_ls__mux2_4.spice
+++ b/cells/mux2/sky130_fd_sc_ls__mux2_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__mux2_4.spice
-* Created: Fri Aug 28 13:30:05 2020
+* Created: Wed Sep 2 11:10:24 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/mux2i/sky130_fd_sc_ls__mux2i_1.lvs.report b/cells/mux2i/sky130_fd_sc_ls__mux2i_1.lvs.report
new file mode 100644
index 0000000..f9f0551
--- /dev/null
+++ b/cells/mux2i/sky130_fd_sc_ls__mux2i_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__mux2i_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__mux2i_1.sp ('sky130_fd_sc_ls__mux2i_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/mux2i/sky130_fd_sc_ls__mux2i_1.spice ('sky130_fd_sc_ls__mux2i_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:10:28 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__mux2i_1 sky130_fd_sc_ls__mux2i_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__mux2i_1
+SOURCE CELL NAME: sky130_fd_sc_ls__mux2i_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 13 13
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 9 9
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB S A0 A1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/mux2i/sky130_fd_sc_ls__mux2i_1.pex.spice b/cells/mux2i/sky130_fd_sc_ls__mux2i_1.pex.spice
index 5fc4a19..e2bc5d5 100644
--- a/cells/mux2i/sky130_fd_sc_ls__mux2i_1.pex.spice
+++ b/cells/mux2i/sky130_fd_sc_ls__mux2i_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__mux2i_1.pex.spice
-* Created: Fri Aug 28 13:30:14 2020
+* Created: Wed Sep 2 11:10:32 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/mux2i/sky130_fd_sc_ls__mux2i_1.pxi.spice b/cells/mux2i/sky130_fd_sc_ls__mux2i_1.pxi.spice
index d8fa282..ee3c891 100644
--- a/cells/mux2i/sky130_fd_sc_ls__mux2i_1.pxi.spice
+++ b/cells/mux2i/sky130_fd_sc_ls__mux2i_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__mux2i_1.pxi.spice
-* Created: Fri Aug 28 13:30:14 2020
+* Created: Wed Sep 2 11:10:32 2020
*
x_PM_SKY130_FD_SC_LS__MUX2I_1%S N_S_M1007_g N_S_c_76_n N_S_M1006_g N_S_c_69_n
+ N_S_c_70_n N_S_c_78_n N_S_M1002_g N_S_c_71_n N_S_M1009_g N_S_c_72_n N_S_c_79_n
diff --git a/cells/mux2i/sky130_fd_sc_ls__mux2i_1.spice b/cells/mux2i/sky130_fd_sc_ls__mux2i_1.spice
index d92cbf8..a0e5604 100644
--- a/cells/mux2i/sky130_fd_sc_ls__mux2i_1.spice
+++ b/cells/mux2i/sky130_fd_sc_ls__mux2i_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__mux2i_1.spice
-* Created: Fri Aug 28 13:30:14 2020
+* Created: Wed Sep 2 11:10:32 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/mux2i/sky130_fd_sc_ls__mux2i_2.lvs.report b/cells/mux2i/sky130_fd_sc_ls__mux2i_2.lvs.report
new file mode 100644
index 0000000..58a49e4
--- /dev/null
+++ b/cells/mux2i/sky130_fd_sc_ls__mux2i_2.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__mux2i_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__mux2i_2.sp ('sky130_fd_sc_ls__mux2i_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/mux2i/sky130_fd_sc_ls__mux2i_2.spice ('sky130_fd_sc_ls__mux2i_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:10:35 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__mux2i_2 sky130_fd_sc_ls__mux2i_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__mux2i_2
+SOURCE CELL NAME: sky130_fd_sc_ls__mux2i_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 13 13
+
+ Instances: 9 9 MN (4 pins)
+ 9 9 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 19 18
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 9 9
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 16 layout mos transistors were reduced to 8.
+ 8 mos transistors were deleted by parallel reduction.
+ 16 source mos transistors were reduced to 8.
+ 8 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A0 A1 S Y VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/mux2i/sky130_fd_sc_ls__mux2i_2.pex.spice b/cells/mux2i/sky130_fd_sc_ls__mux2i_2.pex.spice
index cebbe1b..3c5f471 100644
--- a/cells/mux2i/sky130_fd_sc_ls__mux2i_2.pex.spice
+++ b/cells/mux2i/sky130_fd_sc_ls__mux2i_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__mux2i_2.pex.spice
-* Created: Fri Aug 28 13:30:31 2020
+* Created: Wed Sep 2 11:10:39 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/mux2i/sky130_fd_sc_ls__mux2i_2.pxi.spice b/cells/mux2i/sky130_fd_sc_ls__mux2i_2.pxi.spice
index eba51c3..eb8f488 100644
--- a/cells/mux2i/sky130_fd_sc_ls__mux2i_2.pxi.spice
+++ b/cells/mux2i/sky130_fd_sc_ls__mux2i_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__mux2i_2.pxi.spice
-* Created: Fri Aug 28 13:30:31 2020
+* Created: Wed Sep 2 11:10:39 2020
*
x_PM_SKY130_FD_SC_LS__MUX2I_2%A0 N_A0_c_90_n N_A0_M1006_g N_A0_c_94_n
+ N_A0_M1003_g N_A0_c_95_n N_A0_M1007_g N_A0_c_91_n N_A0_M1015_g A0 A0
diff --git a/cells/mux2i/sky130_fd_sc_ls__mux2i_2.spice b/cells/mux2i/sky130_fd_sc_ls__mux2i_2.spice
index 9881c3e..27a9898 100644
--- a/cells/mux2i/sky130_fd_sc_ls__mux2i_2.spice
+++ b/cells/mux2i/sky130_fd_sc_ls__mux2i_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__mux2i_2.spice
-* Created: Fri Aug 28 13:30:31 2020
+* Created: Wed Sep 2 11:10:39 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/mux2i/sky130_fd_sc_ls__mux2i_4.lvs.report b/cells/mux2i/sky130_fd_sc_ls__mux2i_4.lvs.report
new file mode 100644
index 0000000..0dec5af
--- /dev/null
+++ b/cells/mux2i/sky130_fd_sc_ls__mux2i_4.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__mux2i_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__mux2i_4.sp ('sky130_fd_sc_ls__mux2i_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/mux2i/sky130_fd_sc_ls__mux2i_4.spice ('sky130_fd_sc_ls__mux2i_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:10:42 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__mux2i_4 sky130_fd_sc_ls__mux2i_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__mux2i_4
+SOURCE CELL NAME: sky130_fd_sc_ls__mux2i_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 13 13
+
+ Instances: 17 17 MN (4 pins)
+ 18 18 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 36 35
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 9 9
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 34 layout mos transistors were reduced to 9.
+ 25 mos transistors were deleted by parallel reduction.
+ 34 source mos transistors were reduced to 9.
+ 25 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1 A0 S Y VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/mux2i/sky130_fd_sc_ls__mux2i_4.pex.spice b/cells/mux2i/sky130_fd_sc_ls__mux2i_4.pex.spice
index 3f4ff9f..ae5a141 100644
--- a/cells/mux2i/sky130_fd_sc_ls__mux2i_4.pex.spice
+++ b/cells/mux2i/sky130_fd_sc_ls__mux2i_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__mux2i_4.pex.spice
-* Created: Fri Aug 28 13:30:51 2020
+* Created: Wed Sep 2 11:10:45 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/mux2i/sky130_fd_sc_ls__mux2i_4.pxi.spice b/cells/mux2i/sky130_fd_sc_ls__mux2i_4.pxi.spice
index d309e5b..74ec672 100644
--- a/cells/mux2i/sky130_fd_sc_ls__mux2i_4.pxi.spice
+++ b/cells/mux2i/sky130_fd_sc_ls__mux2i_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__mux2i_4.pxi.spice
-* Created: Fri Aug 28 13:30:51 2020
+* Created: Wed Sep 2 11:10:45 2020
*
x_PM_SKY130_FD_SC_LS__MUX2I_4%A1 N_A1_M1011_g N_A1_c_133_n N_A1_M1000_g
+ N_A1_M1012_g N_A1_c_134_n N_A1_M1014_g N_A1_M1032_g N_A1_c_135_n N_A1_M1015_g
diff --git a/cells/mux2i/sky130_fd_sc_ls__mux2i_4.spice b/cells/mux2i/sky130_fd_sc_ls__mux2i_4.spice
index 075967b..e0ebf33 100644
--- a/cells/mux2i/sky130_fd_sc_ls__mux2i_4.spice
+++ b/cells/mux2i/sky130_fd_sc_ls__mux2i_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__mux2i_4.spice
-* Created: Fri Aug 28 13:30:51 2020
+* Created: Wed Sep 2 11:10:45 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/mux4/sky130_fd_sc_ls__mux4_1.lvs.report b/cells/mux4/sky130_fd_sc_ls__mux4_1.lvs.report
new file mode 100644
index 0000000..44a6779
--- /dev/null
+++ b/cells/mux4/sky130_fd_sc_ls__mux4_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__mux4_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__mux4_1.sp ('sky130_fd_sc_ls__mux4_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/mux4/sky130_fd_sc_ls__mux4_1.spice ('sky130_fd_sc_ls__mux4_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:10:49 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__mux4_1 sky130_fd_sc_ls__mux4_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__mux4_1
+SOURCE CELL NAME: sky130_fd_sc_ls__mux4_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 11 11
+
+ Nets: 24 24
+
+ Instances: 13 13 MN (4 pins)
+ 13 13 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 27 26
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 11 11
+
+ Nets: 16 16
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 4 4 SMN2 (4 pins)
+ 4 4 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 18 18
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 11 11 0 0
+
+ Nets: 16 16 0 0
+
+ Instances: 5 5 0 0 MN(NSHORT)
+ 5 5 0 0 MP(PHIGHVT)
+ 4 4 0 0 SMN2
+ 4 4 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 18 18 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A0 A1 A2 S0 A3 S1 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/mux4/sky130_fd_sc_ls__mux4_1.pex.spice b/cells/mux4/sky130_fd_sc_ls__mux4_1.pex.spice
index 7ab2317..985447a 100644
--- a/cells/mux4/sky130_fd_sc_ls__mux4_1.pex.spice
+++ b/cells/mux4/sky130_fd_sc_ls__mux4_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__mux4_1.pex.spice
-* Created: Fri Aug 28 13:31:02 2020
+* Created: Wed Sep 2 11:10:52 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/mux4/sky130_fd_sc_ls__mux4_1.pxi.spice b/cells/mux4/sky130_fd_sc_ls__mux4_1.pxi.spice
index 2606def..f5ee55b 100644
--- a/cells/mux4/sky130_fd_sc_ls__mux4_1.pxi.spice
+++ b/cells/mux4/sky130_fd_sc_ls__mux4_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__mux4_1.pxi.spice
-* Created: Fri Aug 28 13:31:02 2020
+* Created: Wed Sep 2 11:10:52 2020
*
x_PM_SKY130_FD_SC_LS__MUX4_1%A0 N_A0_c_181_n N_A0_M1004_g N_A0_M1007_g A0
+ N_A0_c_183_n PM_SKY130_FD_SC_LS__MUX4_1%A0
diff --git a/cells/mux4/sky130_fd_sc_ls__mux4_1.spice b/cells/mux4/sky130_fd_sc_ls__mux4_1.spice
index d13dbd7..9d1fcb0 100644
--- a/cells/mux4/sky130_fd_sc_ls__mux4_1.spice
+++ b/cells/mux4/sky130_fd_sc_ls__mux4_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__mux4_1.spice
-* Created: Fri Aug 28 13:31:02 2020
+* Created: Wed Sep 2 11:10:52 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/mux4/sky130_fd_sc_ls__mux4_2.lvs.report b/cells/mux4/sky130_fd_sc_ls__mux4_2.lvs.report
new file mode 100644
index 0000000..0165e8a
--- /dev/null
+++ b/cells/mux4/sky130_fd_sc_ls__mux4_2.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__mux4_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__mux4_2.sp ('sky130_fd_sc_ls__mux4_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/mux4/sky130_fd_sc_ls__mux4_2.spice ('sky130_fd_sc_ls__mux4_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:10:55 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__mux4_2 sky130_fd_sc_ls__mux4_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__mux4_2
+SOURCE CELL NAME: sky130_fd_sc_ls__mux4_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 11 11
+
+ Nets: 24 24
+
+ Instances: 14 14 MN (4 pins)
+ 14 14 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 29 28
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 11 11
+
+ Nets: 16 16
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 4 4 SMN2 (4 pins)
+ 4 4 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 18 18
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 11 11 0 0
+
+ Nets: 16 16 0 0
+
+ Instances: 5 5 0 0 MN(NSHORT)
+ 5 5 0 0 MP(PHIGHVT)
+ 4 4 0 0 SMN2
+ 4 4 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 18 18 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB S0 A1 A0 A3 A2 S1 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/mux4/sky130_fd_sc_ls__mux4_2.pex.spice b/cells/mux4/sky130_fd_sc_ls__mux4_2.pex.spice
index 321c48e..bad3fb9 100644
--- a/cells/mux4/sky130_fd_sc_ls__mux4_2.pex.spice
+++ b/cells/mux4/sky130_fd_sc_ls__mux4_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__mux4_2.pex.spice
-* Created: Fri Aug 28 13:31:12 2020
+* Created: Wed Sep 2 11:10:59 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/mux4/sky130_fd_sc_ls__mux4_2.pxi.spice b/cells/mux4/sky130_fd_sc_ls__mux4_2.pxi.spice
index 2b2dedb..1f288dc 100644
--- a/cells/mux4/sky130_fd_sc_ls__mux4_2.pxi.spice
+++ b/cells/mux4/sky130_fd_sc_ls__mux4_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__mux4_2.pxi.spice
-* Created: Fri Aug 28 13:31:12 2020
+* Created: Wed Sep 2 11:10:59 2020
*
x_PM_SKY130_FD_SC_LS__MUX4_2%S0 N_S0_M1026_g N_S0_c_165_n N_S0_c_183_n
+ N_S0_M1001_g N_S0_M1011_g N_S0_c_167_n N_S0_M1010_g N_S0_M1015_g N_S0_c_168_n
diff --git a/cells/mux4/sky130_fd_sc_ls__mux4_2.spice b/cells/mux4/sky130_fd_sc_ls__mux4_2.spice
index 245b8c0..3e8f9d9 100644
--- a/cells/mux4/sky130_fd_sc_ls__mux4_2.spice
+++ b/cells/mux4/sky130_fd_sc_ls__mux4_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__mux4_2.spice
-* Created: Fri Aug 28 13:31:12 2020
+* Created: Wed Sep 2 11:10:59 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/mux4/sky130_fd_sc_ls__mux4_4.lvs.report b/cells/mux4/sky130_fd_sc_ls__mux4_4.lvs.report
new file mode 100644
index 0000000..7977b24
--- /dev/null
+++ b/cells/mux4/sky130_fd_sc_ls__mux4_4.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__mux4_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__mux4_4.sp ('sky130_fd_sc_ls__mux4_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/mux4/sky130_fd_sc_ls__mux4_4.spice ('sky130_fd_sc_ls__mux4_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:11:03 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__mux4_4 sky130_fd_sc_ls__mux4_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__mux4_4
+SOURCE CELL NAME: sky130_fd_sc_ls__mux4_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 11 11
+
+ Nets: 24 24
+
+ Instances: 26 26 MN (4 pins)
+ 26 26 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 53 52
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 11 11
+
+ Nets: 16 16
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 4 4 SMN2 (4 pins)
+ 4 4 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 18 18
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 11 11 0 0
+
+ Nets: 16 16 0 0
+
+ Instances: 5 5 0 0 MN(NSHORT)
+ 5 5 0 0 MP(PHIGHVT)
+ 4 4 0 0 SMN2
+ 4 4 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 18 18 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 48 layout mos transistors were reduced to 22.
+ 26 mos transistors were deleted by parallel reduction.
+ 48 source mos transistors were reduced to 22.
+ 26 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1 A0 S0 A2 A3 S1 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/mux4/sky130_fd_sc_ls__mux4_4.pex.spice b/cells/mux4/sky130_fd_sc_ls__mux4_4.pex.spice
index 216681e..8f9d523 100644
--- a/cells/mux4/sky130_fd_sc_ls__mux4_4.pex.spice
+++ b/cells/mux4/sky130_fd_sc_ls__mux4_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__mux4_4.pex.spice
-* Created: Fri Aug 28 13:31:21 2020
+* Created: Wed Sep 2 11:11:06 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/mux4/sky130_fd_sc_ls__mux4_4.pxi.spice b/cells/mux4/sky130_fd_sc_ls__mux4_4.pxi.spice
index 173aaa3..ece4ec4 100644
--- a/cells/mux4/sky130_fd_sc_ls__mux4_4.pxi.spice
+++ b/cells/mux4/sky130_fd_sc_ls__mux4_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__mux4_4.pxi.spice
-* Created: Fri Aug 28 13:31:21 2020
+* Created: Wed Sep 2 11:11:06 2020
*
x_PM_SKY130_FD_SC_LS__MUX4_4%A1 N_A1_M1025_g N_A1_c_318_n N_A1_M1039_g
+ N_A1_M1028_g N_A1_c_319_n N_A1_M1041_g A1 A1 N_A1_c_317_n
diff --git a/cells/mux4/sky130_fd_sc_ls__mux4_4.spice b/cells/mux4/sky130_fd_sc_ls__mux4_4.spice
index de1b6a0..c049365 100644
--- a/cells/mux4/sky130_fd_sc_ls__mux4_4.spice
+++ b/cells/mux4/sky130_fd_sc_ls__mux4_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__mux4_4.spice
-* Created: Fri Aug 28 13:31:21 2020
+* Created: Wed Sep 2 11:11:06 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nand2/sky130_fd_sc_ls__nand2_1.lvs.report b/cells/nand2/sky130_fd_sc_ls__nand2_1.lvs.report
new file mode 100644
index 0000000..03bc41f
--- /dev/null
+++ b/cells/nand2/sky130_fd_sc_ls__nand2_1.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__nand2_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__nand2_1.sp ('sky130_fd_sc_ls__nand2_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/nand2/sky130_fd_sc_ls__nand2_1.spice ('sky130_fd_sc_ls__nand2_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:11:10 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__nand2_1 sky130_fd_sc_ls__nand2_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__nand2_1
+SOURCE CELL NAME: sky130_fd_sc_ls__nand2_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 5 4
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 7 7
+
+ Instances: 2 2 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 7 7 0 0
+
+ Instances: 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B A VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nand2/sky130_fd_sc_ls__nand2_1.pex.spice b/cells/nand2/sky130_fd_sc_ls__nand2_1.pex.spice
index 716b629..14881b2 100644
--- a/cells/nand2/sky130_fd_sc_ls__nand2_1.pex.spice
+++ b/cells/nand2/sky130_fd_sc_ls__nand2_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nand2_1.pex.spice
-* Created: Fri Aug 28 13:31:39 2020
+* Created: Wed Sep 2 11:11:14 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nand2/sky130_fd_sc_ls__nand2_1.pxi.spice b/cells/nand2/sky130_fd_sc_ls__nand2_1.pxi.spice
index abb36c4..84d9b85 100644
--- a/cells/nand2/sky130_fd_sc_ls__nand2_1.pxi.spice
+++ b/cells/nand2/sky130_fd_sc_ls__nand2_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nand2_1.pxi.spice
-* Created: Fri Aug 28 13:31:39 2020
+* Created: Wed Sep 2 11:11:14 2020
*
x_PM_SKY130_FD_SC_LS__NAND2_1%B N_B_c_25_n N_B_M1001_g N_B_c_26_n N_B_M1003_g B
+ PM_SKY130_FD_SC_LS__NAND2_1%B
diff --git a/cells/nand2/sky130_fd_sc_ls__nand2_1.spice b/cells/nand2/sky130_fd_sc_ls__nand2_1.spice
index 85c1b21..0445770 100644
--- a/cells/nand2/sky130_fd_sc_ls__nand2_1.spice
+++ b/cells/nand2/sky130_fd_sc_ls__nand2_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nand2_1.spice
-* Created: Fri Aug 28 13:31:39 2020
+* Created: Wed Sep 2 11:11:14 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nand2/sky130_fd_sc_ls__nand2_2.lvs.report b/cells/nand2/sky130_fd_sc_ls__nand2_2.lvs.report
new file mode 100644
index 0000000..bd516ca
--- /dev/null
+++ b/cells/nand2/sky130_fd_sc_ls__nand2_2.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__nand2_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__nand2_2.sp ('sky130_fd_sc_ls__nand2_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/nand2/sky130_fd_sc_ls__nand2_2.spice ('sky130_fd_sc_ls__nand2_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:11:17 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__nand2_2 sky130_fd_sc_ls__nand2_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__nand2_2
+SOURCE CELL NAME: sky130_fd_sc_ls__nand2_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 7 7
+
+ Instances: 2 2 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 7 7 0 0
+
+ Instances: 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 8 layout mos transistors were reduced to 4.
+ 4 mos transistors were deleted by parallel reduction.
+ 8 source mos transistors were reduced to 4.
+ 4 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B A VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nand2/sky130_fd_sc_ls__nand2_2.pex.spice b/cells/nand2/sky130_fd_sc_ls__nand2_2.pex.spice
index f80f977..8cb1cde 100644
--- a/cells/nand2/sky130_fd_sc_ls__nand2_2.pex.spice
+++ b/cells/nand2/sky130_fd_sc_ls__nand2_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nand2_2.pex.spice
-* Created: Fri Aug 28 13:31:59 2020
+* Created: Wed Sep 2 11:11:21 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nand2/sky130_fd_sc_ls__nand2_2.pxi.spice b/cells/nand2/sky130_fd_sc_ls__nand2_2.pxi.spice
index 99a60ba..e32a907 100644
--- a/cells/nand2/sky130_fd_sc_ls__nand2_2.pxi.spice
+++ b/cells/nand2/sky130_fd_sc_ls__nand2_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nand2_2.pxi.spice
-* Created: Fri Aug 28 13:31:59 2020
+* Created: Wed Sep 2 11:11:21 2020
*
x_PM_SKY130_FD_SC_LS__NAND2_2%B N_B_M1005_g N_B_c_49_n N_B_M1002_g N_B_c_50_n
+ N_B_M1003_g N_B_M1007_g B B N_B_c_48_n PM_SKY130_FD_SC_LS__NAND2_2%B
diff --git a/cells/nand2/sky130_fd_sc_ls__nand2_2.spice b/cells/nand2/sky130_fd_sc_ls__nand2_2.spice
index 0477d3c..3c16f6a 100644
--- a/cells/nand2/sky130_fd_sc_ls__nand2_2.spice
+++ b/cells/nand2/sky130_fd_sc_ls__nand2_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nand2_2.spice
-* Created: Fri Aug 28 13:31:59 2020
+* Created: Wed Sep 2 11:11:21 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nand2/sky130_fd_sc_ls__nand2_4.lvs.report b/cells/nand2/sky130_fd_sc_ls__nand2_4.lvs.report
new file mode 100644
index 0000000..8606531
--- /dev/null
+++ b/cells/nand2/sky130_fd_sc_ls__nand2_4.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__nand2_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__nand2_4.sp ('sky130_fd_sc_ls__nand2_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/nand2/sky130_fd_sc_ls__nand2_4.spice ('sky130_fd_sc_ls__nand2_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:11:25 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__nand2_4 sky130_fd_sc_ls__nand2_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__nand2_4
+SOURCE CELL NAME: sky130_fd_sc_ls__nand2_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 8 8 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 7 7
+
+ Instances: 2 2 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 7 7 0 0
+
+ Instances: 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 12 layout mos transistors were reduced to 4.
+ 8 mos transistors were deleted by parallel reduction.
+ 12 source mos transistors were reduced to 4.
+ 8 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B A VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nand2/sky130_fd_sc_ls__nand2_4.pex.spice b/cells/nand2/sky130_fd_sc_ls__nand2_4.pex.spice
index 9617fcf..1e3901a 100644
--- a/cells/nand2/sky130_fd_sc_ls__nand2_4.pex.spice
+++ b/cells/nand2/sky130_fd_sc_ls__nand2_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nand2_4.pex.spice
-* Created: Fri Aug 28 13:32:10 2020
+* Created: Wed Sep 2 11:11:29 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nand2/sky130_fd_sc_ls__nand2_4.pxi.spice b/cells/nand2/sky130_fd_sc_ls__nand2_4.pxi.spice
index 1e44080..ece2ceb 100644
--- a/cells/nand2/sky130_fd_sc_ls__nand2_4.pxi.spice
+++ b/cells/nand2/sky130_fd_sc_ls__nand2_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nand2_4.pxi.spice
-* Created: Fri Aug 28 13:32:10 2020
+* Created: Wed Sep 2 11:11:29 2020
*
x_PM_SKY130_FD_SC_LS__NAND2_4%B N_B_M1003_g N_B_c_73_n N_B_M1004_g N_B_M1008_g
+ N_B_M1010_g N_B_c_74_n N_B_M1009_g N_B_M1011_g B B B N_B_c_72_n N_B_c_77_n
diff --git a/cells/nand2/sky130_fd_sc_ls__nand2_4.spice b/cells/nand2/sky130_fd_sc_ls__nand2_4.spice
index a018a88..024cca0 100644
--- a/cells/nand2/sky130_fd_sc_ls__nand2_4.spice
+++ b/cells/nand2/sky130_fd_sc_ls__nand2_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nand2_4.spice
-* Created: Fri Aug 28 13:32:10 2020
+* Created: Wed Sep 2 11:11:29 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nand2/sky130_fd_sc_ls__nand2_8.lvs.report b/cells/nand2/sky130_fd_sc_ls__nand2_8.lvs.report
new file mode 100644
index 0000000..c9a66e7
--- /dev/null
+++ b/cells/nand2/sky130_fd_sc_ls__nand2_8.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__nand2_8.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__nand2_8.sp ('sky130_fd_sc_ls__nand2_8')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/nand2/sky130_fd_sc_ls__nand2_8.spice ('sky130_fd_sc_ls__nand2_8')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:11:33 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__nand2_8 sky130_fd_sc_ls__nand2_8
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__nand2_8
+SOURCE CELL NAME: sky130_fd_sc_ls__nand2_8
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 16 16 MN (4 pins)
+ 8 8 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 25 24
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 7 7
+
+ Instances: 2 2 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 7 7 0 0
+
+ Instances: 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 24 layout mos transistors were reduced to 4.
+ 20 mos transistors were deleted by parallel reduction.
+ 24 source mos transistors were reduced to 4.
+ 20 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B A VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nand2/sky130_fd_sc_ls__nand2_8.pex.spice b/cells/nand2/sky130_fd_sc_ls__nand2_8.pex.spice
index 6f9130c..8c6bcae 100644
--- a/cells/nand2/sky130_fd_sc_ls__nand2_8.pex.spice
+++ b/cells/nand2/sky130_fd_sc_ls__nand2_8.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nand2_8.pex.spice
-* Created: Fri Aug 28 13:32:20 2020
+* Created: Wed Sep 2 11:11:36 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nand2/sky130_fd_sc_ls__nand2_8.pxi.spice b/cells/nand2/sky130_fd_sc_ls__nand2_8.pxi.spice
index 7532fd9..5bfae78 100644
--- a/cells/nand2/sky130_fd_sc_ls__nand2_8.pxi.spice
+++ b/cells/nand2/sky130_fd_sc_ls__nand2_8.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nand2_8.pxi.spice
-* Created: Fri Aug 28 13:32:20 2020
+* Created: Wed Sep 2 11:11:36 2020
*
x_PM_SKY130_FD_SC_LS__NAND2_8%B N_B_c_108_n N_B_M1000_g N_B_c_109_n N_B_c_110_n
+ N_B_c_111_n N_B_M1010_g N_B_c_112_n N_B_c_113_n N_B_M1011_g N_B_c_114_n
diff --git a/cells/nand2/sky130_fd_sc_ls__nand2_8.spice b/cells/nand2/sky130_fd_sc_ls__nand2_8.spice
index 10095c6..505effc 100644
--- a/cells/nand2/sky130_fd_sc_ls__nand2_8.spice
+++ b/cells/nand2/sky130_fd_sc_ls__nand2_8.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nand2_8.spice
-* Created: Fri Aug 28 13:32:20 2020
+* Created: Wed Sep 2 11:11:36 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nand2b/sky130_fd_sc_ls__nand2b_1.lvs.report b/cells/nand2b/sky130_fd_sc_ls__nand2b_1.lvs.report
new file mode 100644
index 0000000..f3c1b17
--- /dev/null
+++ b/cells/nand2b/sky130_fd_sc_ls__nand2b_1.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__nand2b_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__nand2b_1.sp ('sky130_fd_sc_ls__nand2b_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/nand2b/sky130_fd_sc_ls__nand2b_1.spice ('sky130_fd_sc_ls__nand2b_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:11:40 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__nand2b_1 sky130_fd_sc_ls__nand2b_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__nand2b_1
+SOURCE CELL NAME: sky130_fd_sc_ls__nand2b_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 9 9
+
+ Instances: 3 3 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 7 6
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 1 1 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 3 3 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A_N B VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nand2b/sky130_fd_sc_ls__nand2b_1.pex.spice b/cells/nand2b/sky130_fd_sc_ls__nand2b_1.pex.spice
index 02653c8..ffe0bd3 100644
--- a/cells/nand2b/sky130_fd_sc_ls__nand2b_1.pex.spice
+++ b/cells/nand2b/sky130_fd_sc_ls__nand2b_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nand2b_1.pex.spice
-* Created: Fri Aug 28 13:32:30 2020
+* Created: Wed Sep 2 11:11:43 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nand2b/sky130_fd_sc_ls__nand2b_1.pxi.spice b/cells/nand2b/sky130_fd_sc_ls__nand2b_1.pxi.spice
index bdf36a9..d7ed039 100644
--- a/cells/nand2b/sky130_fd_sc_ls__nand2b_1.pxi.spice
+++ b/cells/nand2b/sky130_fd_sc_ls__nand2b_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nand2b_1.pxi.spice
-* Created: Fri Aug 28 13:32:30 2020
+* Created: Wed Sep 2 11:11:43 2020
*
x_PM_SKY130_FD_SC_LS__NAND2B_1%A_N N_A_N_M1002_g N_A_N_c_45_n N_A_N_M1003_g A_N
+ A_N N_A_N_c_44_n PM_SKY130_FD_SC_LS__NAND2B_1%A_N
diff --git a/cells/nand2b/sky130_fd_sc_ls__nand2b_1.spice b/cells/nand2b/sky130_fd_sc_ls__nand2b_1.spice
index a1361d8..12c9ad3 100644
--- a/cells/nand2b/sky130_fd_sc_ls__nand2b_1.spice
+++ b/cells/nand2b/sky130_fd_sc_ls__nand2b_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nand2b_1.spice
-* Created: Fri Aug 28 13:32:30 2020
+* Created: Wed Sep 2 11:11:43 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nand2b/sky130_fd_sc_ls__nand2b_2.lvs.report b/cells/nand2b/sky130_fd_sc_ls__nand2b_2.lvs.report
new file mode 100644
index 0000000..aede30d
--- /dev/null
+++ b/cells/nand2b/sky130_fd_sc_ls__nand2b_2.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__nand2b_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__nand2b_2.sp ('sky130_fd_sc_ls__nand2b_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/nand2b/sky130_fd_sc_ls__nand2b_2.spice ('sky130_fd_sc_ls__nand2b_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:11:47 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__nand2b_2 sky130_fd_sc_ls__nand2b_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__nand2b_2
+SOURCE CELL NAME: sky130_fd_sc_ls__nand2b_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 9 9
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 1 1 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 3 3 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 8 layout mos transistors were reduced to 4.
+ 4 mos transistors were deleted by parallel reduction.
+ 8 source mos transistors were reduced to 4.
+ 4 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A_N B VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nand2b/sky130_fd_sc_ls__nand2b_2.pex.spice b/cells/nand2b/sky130_fd_sc_ls__nand2b_2.pex.spice
index 170bacf..29964d3 100644
--- a/cells/nand2b/sky130_fd_sc_ls__nand2b_2.pex.spice
+++ b/cells/nand2b/sky130_fd_sc_ls__nand2b_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nand2b_2.pex.spice
-* Created: Fri Aug 28 13:32:47 2020
+* Created: Wed Sep 2 11:11:51 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nand2b/sky130_fd_sc_ls__nand2b_2.pxi.spice b/cells/nand2b/sky130_fd_sc_ls__nand2b_2.pxi.spice
index 3fa4f52..4be4b78 100644
--- a/cells/nand2b/sky130_fd_sc_ls__nand2b_2.pxi.spice
+++ b/cells/nand2b/sky130_fd_sc_ls__nand2b_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nand2b_2.pxi.spice
-* Created: Fri Aug 28 13:32:47 2020
+* Created: Wed Sep 2 11:11:51 2020
*
x_PM_SKY130_FD_SC_LS__NAND2B_2%A_N N_A_N_M1008_g N_A_N_c_72_n N_A_N_M1006_g A_N
+ N_A_N_c_73_n PM_SKY130_FD_SC_LS__NAND2B_2%A_N
diff --git a/cells/nand2b/sky130_fd_sc_ls__nand2b_2.spice b/cells/nand2b/sky130_fd_sc_ls__nand2b_2.spice
index 0b89003..e9ce5db 100644
--- a/cells/nand2b/sky130_fd_sc_ls__nand2b_2.spice
+++ b/cells/nand2b/sky130_fd_sc_ls__nand2b_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nand2b_2.spice
-* Created: Fri Aug 28 13:32:47 2020
+* Created: Wed Sep 2 11:11:51 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nand2b/sky130_fd_sc_ls__nand2b_4.lvs.report b/cells/nand2b/sky130_fd_sc_ls__nand2b_4.lvs.report
new file mode 100644
index 0000000..b645e2a
--- /dev/null
+++ b/cells/nand2b/sky130_fd_sc_ls__nand2b_4.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__nand2b_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__nand2b_4.sp ('sky130_fd_sc_ls__nand2b_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/nand2b/sky130_fd_sc_ls__nand2b_4.spice ('sky130_fd_sc_ls__nand2b_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:11:54 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__nand2b_4 sky130_fd_sc_ls__nand2b_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__nand2b_4
+SOURCE CELL NAME: sky130_fd_sc_ls__nand2b_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 9 9
+
+ Instances: 9 9 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 16 15
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 1 1 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 3 3 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 14 layout mos transistors were reduced to 5.
+ 9 mos transistors were deleted by parallel reduction.
+ 14 source mos transistors were reduced to 5.
+ 9 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A_N B VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nand2b/sky130_fd_sc_ls__nand2b_4.pex.spice b/cells/nand2b/sky130_fd_sc_ls__nand2b_4.pex.spice
index f10ca34..2bd4cc8 100644
--- a/cells/nand2b/sky130_fd_sc_ls__nand2b_4.pex.spice
+++ b/cells/nand2b/sky130_fd_sc_ls__nand2b_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nand2b_4.pex.spice
-* Created: Fri Aug 28 13:33:08 2020
+* Created: Wed Sep 2 11:11:58 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nand2b/sky130_fd_sc_ls__nand2b_4.pxi.spice b/cells/nand2b/sky130_fd_sc_ls__nand2b_4.pxi.spice
index de020b3..5ad0979 100644
--- a/cells/nand2b/sky130_fd_sc_ls__nand2b_4.pxi.spice
+++ b/cells/nand2b/sky130_fd_sc_ls__nand2b_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nand2b_4.pxi.spice
-* Created: Fri Aug 28 13:33:08 2020
+* Created: Wed Sep 2 11:11:58 2020
*
x_PM_SKY130_FD_SC_LS__NAND2B_4%A_N N_A_N_M1007_g N_A_N_c_91_n N_A_N_M1008_g
+ N_A_N_c_86_n N_A_N_c_93_n N_A_N_M1012_g N_A_N_c_87_n N_A_N_c_88_n A_N A_N
diff --git a/cells/nand2b/sky130_fd_sc_ls__nand2b_4.spice b/cells/nand2b/sky130_fd_sc_ls__nand2b_4.spice
index dbf0ebf..ced089e 100644
--- a/cells/nand2b/sky130_fd_sc_ls__nand2b_4.spice
+++ b/cells/nand2b/sky130_fd_sc_ls__nand2b_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nand2b_4.spice
-* Created: Fri Aug 28 13:33:08 2020
+* Created: Wed Sep 2 11:11:58 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nand3/sky130_fd_sc_ls__nand3_1.lvs.report b/cells/nand3/sky130_fd_sc_ls__nand3_1.lvs.report
new file mode 100644
index 0000000..ec59391
--- /dev/null
+++ b/cells/nand3/sky130_fd_sc_ls__nand3_1.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__nand3_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__nand3_1.sp ('sky130_fd_sc_ls__nand3_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/nand3/sky130_fd_sc_ls__nand3_1.spice ('sky130_fd_sc_ls__nand3_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:12:02 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__nand3_1 sky130_fd_sc_ls__nand3_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__nand3_1
+SOURCE CELL NAME: sky130_fd_sc_ls__nand3_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 10 10
+
+ Instances: 3 3 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 7 6
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 8 8
+
+ Instances: 3 3 MP (4 pins)
+ 1 1 SMN3 (5 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 3 3 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN3
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB C B A VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nand3/sky130_fd_sc_ls__nand3_1.pex.spice b/cells/nand3/sky130_fd_sc_ls__nand3_1.pex.spice
index a8f3707..f92cfce 100644
--- a/cells/nand3/sky130_fd_sc_ls__nand3_1.pex.spice
+++ b/cells/nand3/sky130_fd_sc_ls__nand3_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nand3_1.pex.spice
-* Created: Fri Aug 28 13:33:18 2020
+* Created: Wed Sep 2 11:12:05 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nand3/sky130_fd_sc_ls__nand3_1.pxi.spice b/cells/nand3/sky130_fd_sc_ls__nand3_1.pxi.spice
index 74007ae..caba8c0 100644
--- a/cells/nand3/sky130_fd_sc_ls__nand3_1.pxi.spice
+++ b/cells/nand3/sky130_fd_sc_ls__nand3_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nand3_1.pxi.spice
-* Created: Fri Aug 28 13:33:18 2020
+* Created: Wed Sep 2 11:12:05 2020
*
x_PM_SKY130_FD_SC_LS__NAND3_1%C N_C_c_36_n N_C_c_37_n N_C_M1003_g N_C_c_38_n
+ N_C_M1001_g C C PM_SKY130_FD_SC_LS__NAND3_1%C
diff --git a/cells/nand3/sky130_fd_sc_ls__nand3_1.spice b/cells/nand3/sky130_fd_sc_ls__nand3_1.spice
index b488973..7ff6a59 100644
--- a/cells/nand3/sky130_fd_sc_ls__nand3_1.spice
+++ b/cells/nand3/sky130_fd_sc_ls__nand3_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nand3_1.spice
-* Created: Fri Aug 28 13:33:18 2020
+* Created: Wed Sep 2 11:12:05 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nand3/sky130_fd_sc_ls__nand3_2.lvs.report b/cells/nand3/sky130_fd_sc_ls__nand3_2.lvs.report
new file mode 100644
index 0000000..f1a79a4
--- /dev/null
+++ b/cells/nand3/sky130_fd_sc_ls__nand3_2.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__nand3_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__nand3_2.sp ('sky130_fd_sc_ls__nand3_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/nand3/sky130_fd_sc_ls__nand3_2.spice ('sky130_fd_sc_ls__nand3_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:12:09 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__nand3_2 sky130_fd_sc_ls__nand3_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__nand3_2
+SOURCE CELL NAME: sky130_fd_sc_ls__nand3_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 10 10
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 8 8
+
+ Instances: 3 3 MP (4 pins)
+ 1 1 SMN3 (5 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 3 3 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN3
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 12 layout mos transistors were reduced to 6.
+ 6 mos transistors were deleted by parallel reduction.
+ 12 source mos transistors were reduced to 6.
+ 6 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB C B A VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nand3/sky130_fd_sc_ls__nand3_2.pex.spice b/cells/nand3/sky130_fd_sc_ls__nand3_2.pex.spice
index faa1a80..7242c34 100644
--- a/cells/nand3/sky130_fd_sc_ls__nand3_2.pex.spice
+++ b/cells/nand3/sky130_fd_sc_ls__nand3_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nand3_2.pex.spice
-* Created: Fri Aug 28 13:33:28 2020
+* Created: Wed Sep 2 11:12:12 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nand3/sky130_fd_sc_ls__nand3_2.pxi.spice b/cells/nand3/sky130_fd_sc_ls__nand3_2.pxi.spice
index 682b00f..8c4dea4 100644
--- a/cells/nand3/sky130_fd_sc_ls__nand3_2.pxi.spice
+++ b/cells/nand3/sky130_fd_sc_ls__nand3_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nand3_2.pxi.spice
-* Created: Fri Aug 28 13:33:28 2020
+* Created: Wed Sep 2 11:12:12 2020
*
x_PM_SKY130_FD_SC_LS__NAND3_2%C N_C_c_58_n N_C_M1007_g N_C_c_62_n N_C_M1005_g
+ N_C_c_59_n N_C_M1011_g N_C_c_63_n N_C_M1006_g C N_C_c_60_n N_C_c_61_n
diff --git a/cells/nand3/sky130_fd_sc_ls__nand3_2.spice b/cells/nand3/sky130_fd_sc_ls__nand3_2.spice
index 1a83a57..7513e9d 100644
--- a/cells/nand3/sky130_fd_sc_ls__nand3_2.spice
+++ b/cells/nand3/sky130_fd_sc_ls__nand3_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nand3_2.spice
-* Created: Fri Aug 28 13:33:28 2020
+* Created: Wed Sep 2 11:12:12 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nand3/sky130_fd_sc_ls__nand3_4.lvs.report b/cells/nand3/sky130_fd_sc_ls__nand3_4.lvs.report
new file mode 100644
index 0000000..1e73424
--- /dev/null
+++ b/cells/nand3/sky130_fd_sc_ls__nand3_4.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__nand3_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__nand3_4.sp ('sky130_fd_sc_ls__nand3_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/nand3/sky130_fd_sc_ls__nand3_4.spice ('sky130_fd_sc_ls__nand3_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:12:16 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__nand3_4 sky130_fd_sc_ls__nand3_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__nand3_4
+SOURCE CELL NAME: sky130_fd_sc_ls__nand3_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 10 10
+
+ Instances: 12 12 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 19 18
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 8 8
+
+ Instances: 3 3 MP (4 pins)
+ 1 1 SMN3 (5 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 3 3 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN3
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 18 layout mos transistors were reduced to 6.
+ 12 mos transistors were deleted by parallel reduction.
+ 18 source mos transistors were reduced to 6.
+ 12 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A B C VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nand3/sky130_fd_sc_ls__nand3_4.pex.spice b/cells/nand3/sky130_fd_sc_ls__nand3_4.pex.spice
index 5959958..d0afe9c 100644
--- a/cells/nand3/sky130_fd_sc_ls__nand3_4.pex.spice
+++ b/cells/nand3/sky130_fd_sc_ls__nand3_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nand3_4.pex.spice
-* Created: Fri Aug 28 13:33:38 2020
+* Created: Wed Sep 2 11:12:20 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nand3/sky130_fd_sc_ls__nand3_4.pxi.spice b/cells/nand3/sky130_fd_sc_ls__nand3_4.pxi.spice
index 852f7e6..48c31d2 100644
--- a/cells/nand3/sky130_fd_sc_ls__nand3_4.pxi.spice
+++ b/cells/nand3/sky130_fd_sc_ls__nand3_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nand3_4.pxi.spice
-* Created: Fri Aug 28 13:33:38 2020
+* Created: Wed Sep 2 11:12:20 2020
*
x_PM_SKY130_FD_SC_LS__NAND3_4%A N_A_c_87_n N_A_M1005_g N_A_c_92_n N_A_M1006_g
+ N_A_c_88_n N_A_M1012_g N_A_c_89_n N_A_M1013_g N_A_c_93_n N_A_M1011_g
diff --git a/cells/nand3/sky130_fd_sc_ls__nand3_4.spice b/cells/nand3/sky130_fd_sc_ls__nand3_4.spice
index c7c5763..c34cf9e 100644
--- a/cells/nand3/sky130_fd_sc_ls__nand3_4.spice
+++ b/cells/nand3/sky130_fd_sc_ls__nand3_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nand3_4.spice
-* Created: Fri Aug 28 13:33:38 2020
+* Created: Wed Sep 2 11:12:20 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nand3b/sky130_fd_sc_ls__nand3b_1.lvs.report b/cells/nand3b/sky130_fd_sc_ls__nand3b_1.lvs.report
new file mode 100644
index 0000000..77e1049
--- /dev/null
+++ b/cells/nand3b/sky130_fd_sc_ls__nand3b_1.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__nand3b_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__nand3b_1.sp ('sky130_fd_sc_ls__nand3b_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/nand3b/sky130_fd_sc_ls__nand3b_1.spice ('sky130_fd_sc_ls__nand3b_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:12:24 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__nand3b_1 sky130_fd_sc_ls__nand3b_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__nand3b_1
+SOURCE CELL NAME: sky130_fd_sc_ls__nand3b_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 11 11
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 9 9
+
+ Instances: 1 1 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 1 SMN3 (5 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 4 4 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN3
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A_N C B VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nand3b/sky130_fd_sc_ls__nand3b_1.pex.spice b/cells/nand3b/sky130_fd_sc_ls__nand3b_1.pex.spice
index 64cbf24..0760db1 100644
--- a/cells/nand3b/sky130_fd_sc_ls__nand3b_1.pex.spice
+++ b/cells/nand3b/sky130_fd_sc_ls__nand3b_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nand3b_1.pex.spice
-* Created: Fri Aug 28 13:33:55 2020
+* Created: Wed Sep 2 11:12:27 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nand3b/sky130_fd_sc_ls__nand3b_1.pxi.spice b/cells/nand3b/sky130_fd_sc_ls__nand3b_1.pxi.spice
index bcf941e..eeb24dd 100644
--- a/cells/nand3b/sky130_fd_sc_ls__nand3b_1.pxi.spice
+++ b/cells/nand3b/sky130_fd_sc_ls__nand3b_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nand3b_1.pxi.spice
-* Created: Fri Aug 28 13:33:55 2020
+* Created: Wed Sep 2 11:12:27 2020
*
x_PM_SKY130_FD_SC_LS__NAND3B_1%A_N N_A_N_M1003_g N_A_N_c_48_n N_A_N_M1005_g A_N
+ N_A_N_c_49_n PM_SKY130_FD_SC_LS__NAND3B_1%A_N
diff --git a/cells/nand3b/sky130_fd_sc_ls__nand3b_1.spice b/cells/nand3b/sky130_fd_sc_ls__nand3b_1.spice
index e6cc6e3..415c5c8 100644
--- a/cells/nand3b/sky130_fd_sc_ls__nand3b_1.spice
+++ b/cells/nand3b/sky130_fd_sc_ls__nand3b_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nand3b_1.spice
-* Created: Fri Aug 28 13:33:55 2020
+* Created: Wed Sep 2 11:12:27 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nand3b/sky130_fd_sc_ls__nand3b_2.lvs.report b/cells/nand3b/sky130_fd_sc_ls__nand3b_2.lvs.report
new file mode 100644
index 0000000..9386858
--- /dev/null
+++ b/cells/nand3b/sky130_fd_sc_ls__nand3b_2.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__nand3b_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__nand3b_2.sp ('sky130_fd_sc_ls__nand3b_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/nand3b/sky130_fd_sc_ls__nand3b_2.spice ('sky130_fd_sc_ls__nand3b_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:12:31 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__nand3b_2 sky130_fd_sc_ls__nand3b_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__nand3b_2
+SOURCE CELL NAME: sky130_fd_sc_ls__nand3b_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 11 11
+
+ Instances: 7 7 MN (4 pins)
+ 7 7 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 15 14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 9 9
+
+ Instances: 1 1 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 1 SMN3 (5 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 4 4 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN3
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 12 layout mos transistors were reduced to 6.
+ 6 mos transistors were deleted by parallel reduction.
+ 12 source mos transistors were reduced to 6.
+ 6 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A_N C B VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nand3b/sky130_fd_sc_ls__nand3b_2.pex.spice b/cells/nand3b/sky130_fd_sc_ls__nand3b_2.pex.spice
index c551c6b..01d7722 100644
--- a/cells/nand3b/sky130_fd_sc_ls__nand3b_2.pex.spice
+++ b/cells/nand3b/sky130_fd_sc_ls__nand3b_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nand3b_2.pex.spice
-* Created: Fri Aug 28 13:34:15 2020
+* Created: Wed Sep 2 11:12:34 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nand3b/sky130_fd_sc_ls__nand3b_2.pxi.spice b/cells/nand3b/sky130_fd_sc_ls__nand3b_2.pxi.spice
index ec9681a..9935550 100644
--- a/cells/nand3b/sky130_fd_sc_ls__nand3b_2.pxi.spice
+++ b/cells/nand3b/sky130_fd_sc_ls__nand3b_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nand3b_2.pxi.spice
-* Created: Fri Aug 28 13:34:15 2020
+* Created: Wed Sep 2 11:12:34 2020
*
x_PM_SKY130_FD_SC_LS__NAND3B_2%A_N N_A_N_M1003_g N_A_N_c_74_n N_A_N_M1002_g A_N
+ N_A_N_c_72_n N_A_N_c_73_n PM_SKY130_FD_SC_LS__NAND3B_2%A_N
diff --git a/cells/nand3b/sky130_fd_sc_ls__nand3b_2.spice b/cells/nand3b/sky130_fd_sc_ls__nand3b_2.spice
index 20924d0..f34adb4 100644
--- a/cells/nand3b/sky130_fd_sc_ls__nand3b_2.spice
+++ b/cells/nand3b/sky130_fd_sc_ls__nand3b_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nand3b_2.spice
-* Created: Fri Aug 28 13:34:15 2020
+* Created: Wed Sep 2 11:12:34 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nand3b/sky130_fd_sc_ls__nand3b_4.lvs.report b/cells/nand3b/sky130_fd_sc_ls__nand3b_4.lvs.report
new file mode 100644
index 0000000..87b3ea4
--- /dev/null
+++ b/cells/nand3b/sky130_fd_sc_ls__nand3b_4.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__nand3b_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__nand3b_4.sp ('sky130_fd_sc_ls__nand3b_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/nand3b/sky130_fd_sc_ls__nand3b_4.spice ('sky130_fd_sc_ls__nand3b_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:12:38 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__nand3b_4 sky130_fd_sc_ls__nand3b_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__nand3b_4
+SOURCE CELL NAME: sky130_fd_sc_ls__nand3b_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 11 11
+
+ Instances: 13 13 MN (4 pins)
+ 8 8 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 22 21
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 9 9
+
+ Instances: 1 1 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 1 SMN3 (5 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 4 4 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN3
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 20 layout mos transistors were reduced to 7.
+ 13 mos transistors were deleted by parallel reduction.
+ 20 source mos transistors were reduced to 7.
+ 13 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A_N C B VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nand3b/sky130_fd_sc_ls__nand3b_4.pex.spice b/cells/nand3b/sky130_fd_sc_ls__nand3b_4.pex.spice
index ee6a1f5..131667c 100644
--- a/cells/nand3b/sky130_fd_sc_ls__nand3b_4.pex.spice
+++ b/cells/nand3b/sky130_fd_sc_ls__nand3b_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nand3b_4.pex.spice
-* Created: Fri Aug 28 13:34:25 2020
+* Created: Wed Sep 2 11:12:41 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nand3b/sky130_fd_sc_ls__nand3b_4.pxi.spice b/cells/nand3b/sky130_fd_sc_ls__nand3b_4.pxi.spice
index 47efbc8..f240d61 100644
--- a/cells/nand3b/sky130_fd_sc_ls__nand3b_4.pxi.spice
+++ b/cells/nand3b/sky130_fd_sc_ls__nand3b_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nand3b_4.pxi.spice
-* Created: Fri Aug 28 13:34:25 2020
+* Created: Wed Sep 2 11:12:41 2020
*
x_PM_SKY130_FD_SC_LS__NAND3B_4%A_N N_A_N_M1020_g N_A_N_c_105_n N_A_N_M1000_g
+ N_A_N_c_102_n N_A_N_c_107_n N_A_N_M1018_g A_N N_A_N_c_103_n N_A_N_c_104_n
diff --git a/cells/nand3b/sky130_fd_sc_ls__nand3b_4.spice b/cells/nand3b/sky130_fd_sc_ls__nand3b_4.spice
index 6fbffbf..b8e9263 100644
--- a/cells/nand3b/sky130_fd_sc_ls__nand3b_4.spice
+++ b/cells/nand3b/sky130_fd_sc_ls__nand3b_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nand3b_4.spice
-* Created: Fri Aug 28 13:34:25 2020
+* Created: Wed Sep 2 11:12:41 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nand4/sky130_fd_sc_ls__nand4_1.lvs.report b/cells/nand4/sky130_fd_sc_ls__nand4_1.lvs.report
new file mode 100644
index 0000000..992f353
--- /dev/null
+++ b/cells/nand4/sky130_fd_sc_ls__nand4_1.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__nand4_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__nand4_1.sp ('sky130_fd_sc_ls__nand4_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/nand4/sky130_fd_sc_ls__nand4_1.spice ('sky130_fd_sc_ls__nand4_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:12:45 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__nand4_1 sky130_fd_sc_ls__nand4_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__nand4_1
+SOURCE CELL NAME: sky130_fd_sc_ls__nand4_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 12 12
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 9 9
+
+ Instances: 4 4 MP (4 pins)
+ 1 1 SMN4 (6 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 4 4 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN4
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D C B A VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nand4/sky130_fd_sc_ls__nand4_1.pex.spice b/cells/nand4/sky130_fd_sc_ls__nand4_1.pex.spice
index 0043bc3..75667e8 100644
--- a/cells/nand4/sky130_fd_sc_ls__nand4_1.pex.spice
+++ b/cells/nand4/sky130_fd_sc_ls__nand4_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nand4_1.pex.spice
-* Created: Fri Aug 28 13:34:35 2020
+* Created: Wed Sep 2 11:12:48 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nand4/sky130_fd_sc_ls__nand4_1.pxi.spice b/cells/nand4/sky130_fd_sc_ls__nand4_1.pxi.spice
index 7d5cb80..362c8d6 100644
--- a/cells/nand4/sky130_fd_sc_ls__nand4_1.pxi.spice
+++ b/cells/nand4/sky130_fd_sc_ls__nand4_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nand4_1.pxi.spice
-* Created: Fri Aug 28 13:34:35 2020
+* Created: Wed Sep 2 11:12:48 2020
*
x_PM_SKY130_FD_SC_LS__NAND4_1%D N_D_c_43_n N_D_M1003_g N_D_c_44_n N_D_M1000_g D
+ PM_SKY130_FD_SC_LS__NAND4_1%D
diff --git a/cells/nand4/sky130_fd_sc_ls__nand4_1.spice b/cells/nand4/sky130_fd_sc_ls__nand4_1.spice
index c7c40ca..dc65d77 100644
--- a/cells/nand4/sky130_fd_sc_ls__nand4_1.spice
+++ b/cells/nand4/sky130_fd_sc_ls__nand4_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nand4_1.spice
-* Created: Fri Aug 28 13:34:35 2020
+* Created: Wed Sep 2 11:12:48 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nand4/sky130_fd_sc_ls__nand4_2.lvs.report b/cells/nand4/sky130_fd_sc_ls__nand4_2.lvs.report
new file mode 100644
index 0000000..c107931
--- /dev/null
+++ b/cells/nand4/sky130_fd_sc_ls__nand4_2.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__nand4_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__nand4_2.sp ('sky130_fd_sc_ls__nand4_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/nand4/sky130_fd_sc_ls__nand4_2.spice ('sky130_fd_sc_ls__nand4_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:12:51 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__nand4_2 sky130_fd_sc_ls__nand4_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__nand4_2
+SOURCE CELL NAME: sky130_fd_sc_ls__nand4_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 12 12
+
+ Instances: 8 8 MN (4 pins)
+ 8 8 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 17 16
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 9 9
+
+ Instances: 4 4 MP (4 pins)
+ 1 1 SMN4 (6 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 4 4 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN4
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 16 layout mos transistors were reduced to 8.
+ 8 mos transistors were deleted by parallel reduction.
+ 16 source mos transistors were reduced to 8.
+ 8 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D C B A VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nand4/sky130_fd_sc_ls__nand4_2.pex.spice b/cells/nand4/sky130_fd_sc_ls__nand4_2.pex.spice
index 9a3bb63..11f59f2 100644
--- a/cells/nand4/sky130_fd_sc_ls__nand4_2.pex.spice
+++ b/cells/nand4/sky130_fd_sc_ls__nand4_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nand4_2.pex.spice
-* Created: Fri Aug 28 13:34:45 2020
+* Created: Wed Sep 2 11:12:54 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nand4/sky130_fd_sc_ls__nand4_2.pxi.spice b/cells/nand4/sky130_fd_sc_ls__nand4_2.pxi.spice
index 75d4834..7130b43 100644
--- a/cells/nand4/sky130_fd_sc_ls__nand4_2.pxi.spice
+++ b/cells/nand4/sky130_fd_sc_ls__nand4_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nand4_2.pxi.spice
-* Created: Fri Aug 28 13:34:45 2020
+* Created: Wed Sep 2 11:12:54 2020
*
x_PM_SKY130_FD_SC_LS__NAND4_2%D N_D_M1001_g N_D_c_84_n N_D_M1006_g N_D_c_85_n
+ N_D_M1009_g N_D_M1011_g D D N_D_c_82_n N_D_c_83_n
diff --git a/cells/nand4/sky130_fd_sc_ls__nand4_2.spice b/cells/nand4/sky130_fd_sc_ls__nand4_2.spice
index e35592a..1de16c8 100644
--- a/cells/nand4/sky130_fd_sc_ls__nand4_2.spice
+++ b/cells/nand4/sky130_fd_sc_ls__nand4_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nand4_2.spice
-* Created: Fri Aug 28 13:34:45 2020
+* Created: Wed Sep 2 11:12:54 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nand4/sky130_fd_sc_ls__nand4_4.lvs.report b/cells/nand4/sky130_fd_sc_ls__nand4_4.lvs.report
new file mode 100644
index 0000000..46212e5
--- /dev/null
+++ b/cells/nand4/sky130_fd_sc_ls__nand4_4.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__nand4_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__nand4_4.sp ('sky130_fd_sc_ls__nand4_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/nand4/sky130_fd_sc_ls__nand4_4.spice ('sky130_fd_sc_ls__nand4_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:12:58 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__nand4_4 sky130_fd_sc_ls__nand4_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__nand4_4
+SOURCE CELL NAME: sky130_fd_sc_ls__nand4_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 12 12
+
+ Instances: 16 16 MN (4 pins)
+ 8 8 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 25 24
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 9 9
+
+ Instances: 4 4 MP (4 pins)
+ 1 1 SMN4 (6 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 4 4 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN4
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 24 layout mos transistors were reduced to 8.
+ 16 mos transistors were deleted by parallel reduction.
+ 24 source mos transistors were reduced to 8.
+ 16 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D C B A VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nand4/sky130_fd_sc_ls__nand4_4.pex.spice b/cells/nand4/sky130_fd_sc_ls__nand4_4.pex.spice
index 7b1d276..9213f35 100644
--- a/cells/nand4/sky130_fd_sc_ls__nand4_4.pex.spice
+++ b/cells/nand4/sky130_fd_sc_ls__nand4_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nand4_4.pex.spice
-* Created: Fri Aug 28 13:35:03 2020
+* Created: Wed Sep 2 11:13:01 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nand4/sky130_fd_sc_ls__nand4_4.pxi.spice b/cells/nand4/sky130_fd_sc_ls__nand4_4.pxi.spice
index 5ef8a0d..0bbbf76 100644
--- a/cells/nand4/sky130_fd_sc_ls__nand4_4.pxi.spice
+++ b/cells/nand4/sky130_fd_sc_ls__nand4_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nand4_4.pxi.spice
-* Created: Fri Aug 28 13:35:03 2020
+* Created: Wed Sep 2 11:13:01 2020
*
x_PM_SKY130_FD_SC_LS__NAND4_4%D N_D_M1007_g N_D_M1009_g N_D_c_109_n N_D_M1014_g
+ N_D_c_118_n N_D_M1000_g N_D_M1018_g N_D_c_119_n N_D_M1005_g N_D_c_112_n
diff --git a/cells/nand4/sky130_fd_sc_ls__nand4_4.spice b/cells/nand4/sky130_fd_sc_ls__nand4_4.spice
index 4ee7416..1622921 100644
--- a/cells/nand4/sky130_fd_sc_ls__nand4_4.spice
+++ b/cells/nand4/sky130_fd_sc_ls__nand4_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nand4_4.spice
-* Created: Fri Aug 28 13:35:03 2020
+* Created: Wed Sep 2 11:13:01 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nand4b/sky130_fd_sc_ls__nand4b_1.lvs.report b/cells/nand4b/sky130_fd_sc_ls__nand4b_1.lvs.report
new file mode 100644
index 0000000..fd7d6d2
--- /dev/null
+++ b/cells/nand4b/sky130_fd_sc_ls__nand4b_1.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__nand4b_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__nand4b_1.sp ('sky130_fd_sc_ls__nand4b_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/nand4b/sky130_fd_sc_ls__nand4b_1.spice ('sky130_fd_sc_ls__nand4b_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:13:04 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__nand4b_1 sky130_fd_sc_ls__nand4b_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__nand4b_1
+SOURCE CELL NAME: sky130_fd_sc_ls__nand4b_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 1 1 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 1 SMN4 (6 pins)
+ ------ ------
+ Total Inst: 7 7
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 5 5 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN4
+ ------- ------- --------- ---------
+ Total Inst: 7 7 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A_N D C B VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nand4b/sky130_fd_sc_ls__nand4b_1.pex.spice b/cells/nand4b/sky130_fd_sc_ls__nand4b_1.pex.spice
index 275be09..4cd8d4f 100644
--- a/cells/nand4b/sky130_fd_sc_ls__nand4b_1.pex.spice
+++ b/cells/nand4b/sky130_fd_sc_ls__nand4b_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nand4b_1.pex.spice
-* Created: Fri Aug 28 13:35:23 2020
+* Created: Wed Sep 2 11:13:07 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nand4b/sky130_fd_sc_ls__nand4b_1.pxi.spice b/cells/nand4b/sky130_fd_sc_ls__nand4b_1.pxi.spice
index f9745dc..c6d95ee 100644
--- a/cells/nand4b/sky130_fd_sc_ls__nand4b_1.pxi.spice
+++ b/cells/nand4b/sky130_fd_sc_ls__nand4b_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nand4b_1.pxi.spice
-* Created: Fri Aug 28 13:35:23 2020
+* Created: Wed Sep 2 11:13:07 2020
*
x_PM_SKY130_FD_SC_LS__NAND4B_1%A_N N_A_N_c_52_n N_A_N_M1000_g N_A_N_c_53_n
+ N_A_N_M1007_g A_N PM_SKY130_FD_SC_LS__NAND4B_1%A_N
diff --git a/cells/nand4b/sky130_fd_sc_ls__nand4b_1.spice b/cells/nand4b/sky130_fd_sc_ls__nand4b_1.spice
index ebe6f7f..873cde4 100644
--- a/cells/nand4b/sky130_fd_sc_ls__nand4b_1.spice
+++ b/cells/nand4b/sky130_fd_sc_ls__nand4b_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nand4b_1.spice
-* Created: Fri Aug 28 13:35:23 2020
+* Created: Wed Sep 2 11:13:07 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nand4b/sky130_fd_sc_ls__nand4b_2.lvs.report b/cells/nand4b/sky130_fd_sc_ls__nand4b_2.lvs.report
new file mode 100644
index 0000000..2859cc2
--- /dev/null
+++ b/cells/nand4b/sky130_fd_sc_ls__nand4b_2.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__nand4b_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__nand4b_2.sp ('sky130_fd_sc_ls__nand4b_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/nand4b/sky130_fd_sc_ls__nand4b_2.spice ('sky130_fd_sc_ls__nand4b_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:13:11 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__nand4b_2 sky130_fd_sc_ls__nand4b_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__nand4b_2
+SOURCE CELL NAME: sky130_fd_sc_ls__nand4b_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 9 9 MN (4 pins)
+ 9 9 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 19 18
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 1 1 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 1 SMN4 (6 pins)
+ ------ ------
+ Total Inst: 7 7
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 5 5 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN4
+ ------- ------- --------- ---------
+ Total Inst: 7 7 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 16 layout mos transistors were reduced to 8.
+ 8 mos transistors were deleted by parallel reduction.
+ 16 source mos transistors were reduced to 8.
+ 8 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A_N B C D VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nand4b/sky130_fd_sc_ls__nand4b_2.pex.spice b/cells/nand4b/sky130_fd_sc_ls__nand4b_2.pex.spice
index 1e193f7..6f7e1c0 100644
--- a/cells/nand4b/sky130_fd_sc_ls__nand4b_2.pex.spice
+++ b/cells/nand4b/sky130_fd_sc_ls__nand4b_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nand4b_2.pex.spice
-* Created: Fri Aug 28 13:35:34 2020
+* Created: Wed Sep 2 11:13:14 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nand4b/sky130_fd_sc_ls__nand4b_2.pxi.spice b/cells/nand4b/sky130_fd_sc_ls__nand4b_2.pxi.spice
index 665ca25..623d1bb 100644
--- a/cells/nand4b/sky130_fd_sc_ls__nand4b_2.pxi.spice
+++ b/cells/nand4b/sky130_fd_sc_ls__nand4b_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nand4b_2.pxi.spice
-* Created: Fri Aug 28 13:35:34 2020
+* Created: Wed Sep 2 11:13:14 2020
*
x_PM_SKY130_FD_SC_LS__NAND4B_2%A_N N_A_N_M1015_g N_A_N_c_94_n N_A_N_c_98_n
+ N_A_N_M1014_g A_N A_N N_A_N_c_95_n N_A_N_c_96_n
diff --git a/cells/nand4b/sky130_fd_sc_ls__nand4b_2.spice b/cells/nand4b/sky130_fd_sc_ls__nand4b_2.spice
index 61f0a1e..8ab1847 100644
--- a/cells/nand4b/sky130_fd_sc_ls__nand4b_2.spice
+++ b/cells/nand4b/sky130_fd_sc_ls__nand4b_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nand4b_2.spice
-* Created: Fri Aug 28 13:35:34 2020
+* Created: Wed Sep 2 11:13:14 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nand4b/sky130_fd_sc_ls__nand4b_4.lvs.report b/cells/nand4b/sky130_fd_sc_ls__nand4b_4.lvs.report
new file mode 100644
index 0000000..8108afe
--- /dev/null
+++ b/cells/nand4b/sky130_fd_sc_ls__nand4b_4.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__nand4b_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__nand4b_4.sp ('sky130_fd_sc_ls__nand4b_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/nand4b/sky130_fd_sc_ls__nand4b_4.spice ('sky130_fd_sc_ls__nand4b_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:13:18 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__nand4b_4 sky130_fd_sc_ls__nand4b_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__nand4b_4
+SOURCE CELL NAME: sky130_fd_sc_ls__nand4b_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 17 17 MN (4 pins)
+ 10 10 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 28 27
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 1 1 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 1 SMN4 (6 pins)
+ ------ ------
+ Total Inst: 7 7
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 5 5 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN4
+ ------- ------- --------- ---------
+ Total Inst: 7 7 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 26 layout mos transistors were reduced to 9.
+ 17 mos transistors were deleted by parallel reduction.
+ 26 source mos transistors were reduced to 9.
+ 17 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A_N B C D VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nand4b/sky130_fd_sc_ls__nand4b_4.pex.spice b/cells/nand4b/sky130_fd_sc_ls__nand4b_4.pex.spice
index 445c2e8..ccfefdb 100644
--- a/cells/nand4b/sky130_fd_sc_ls__nand4b_4.pex.spice
+++ b/cells/nand4b/sky130_fd_sc_ls__nand4b_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nand4b_4.pex.spice
-* Created: Fri Aug 28 13:35:44 2020
+* Created: Wed Sep 2 11:13:21 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nand4b/sky130_fd_sc_ls__nand4b_4.pxi.spice b/cells/nand4b/sky130_fd_sc_ls__nand4b_4.pxi.spice
index 0a93660..8d31670 100644
--- a/cells/nand4b/sky130_fd_sc_ls__nand4b_4.pxi.spice
+++ b/cells/nand4b/sky130_fd_sc_ls__nand4b_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nand4b_4.pxi.spice
-* Created: Fri Aug 28 13:35:44 2020
+* Created: Wed Sep 2 11:13:21 2020
*
x_PM_SKY130_FD_SC_LS__NAND4B_4%A_N N_A_N_M1020_g N_A_N_c_121_n N_A_N_M1000_g
+ N_A_N_c_118_n N_A_N_c_119_n N_A_N_c_124_n N_A_N_M1019_g A_N A_N
diff --git a/cells/nand4b/sky130_fd_sc_ls__nand4b_4.spice b/cells/nand4b/sky130_fd_sc_ls__nand4b_4.spice
index 5e4b480..cf5de2f 100644
--- a/cells/nand4b/sky130_fd_sc_ls__nand4b_4.spice
+++ b/cells/nand4b/sky130_fd_sc_ls__nand4b_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nand4b_4.spice
-* Created: Fri Aug 28 13:35:44 2020
+* Created: Wed Sep 2 11:13:21 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nand4bb/sky130_fd_sc_ls__nand4bb_1.lvs.report b/cells/nand4bb/sky130_fd_sc_ls__nand4bb_1.lvs.report
new file mode 100644
index 0000000..a85c360
--- /dev/null
+++ b/cells/nand4bb/sky130_fd_sc_ls__nand4bb_1.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__nand4bb_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__nand4bb_1.sp ('sky130_fd_sc_ls__nand4bb_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/nand4bb/sky130_fd_sc_ls__nand4bb_1.spice ('sky130_fd_sc_ls__nand4bb_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:13:25 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__nand4bb_1 sky130_fd_sc_ls__nand4bb_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__nand4bb_1
+SOURCE CELL NAME: sky130_fd_sc_ls__nand4bb_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 14 14
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 11 11
+
+ Instances: 2 2 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 1 SMN4 (6 pins)
+ ------ ------
+ Total Inst: 9 9
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 6 6 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN4
+ ------- ------- --------- ---------
+ Total Inst: 9 9 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A_N B_N C D VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nand4bb/sky130_fd_sc_ls__nand4bb_1.pex.spice b/cells/nand4bb/sky130_fd_sc_ls__nand4bb_1.pex.spice
index 693d344..dfc2024 100644
--- a/cells/nand4bb/sky130_fd_sc_ls__nand4bb_1.pex.spice
+++ b/cells/nand4bb/sky130_fd_sc_ls__nand4bb_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nand4bb_1.pex.spice
-* Created: Fri Aug 28 13:35:54 2020
+* Created: Wed Sep 2 11:13:28 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nand4bb/sky130_fd_sc_ls__nand4bb_1.pxi.spice b/cells/nand4bb/sky130_fd_sc_ls__nand4bb_1.pxi.spice
index 3cf2edb..6394627 100644
--- a/cells/nand4bb/sky130_fd_sc_ls__nand4bb_1.pxi.spice
+++ b/cells/nand4bb/sky130_fd_sc_ls__nand4bb_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nand4bb_1.pxi.spice
-* Created: Fri Aug 28 13:35:54 2020
+* Created: Wed Sep 2 11:13:28 2020
*
x_PM_SKY130_FD_SC_LS__NAND4BB_1%A_N N_A_N_c_70_n N_A_N_c_71_n N_A_N_c_76_n
+ N_A_N_M1009_g N_A_N_M1002_g A_N N_A_N_c_73_n N_A_N_c_74_n
diff --git a/cells/nand4bb/sky130_fd_sc_ls__nand4bb_1.spice b/cells/nand4bb/sky130_fd_sc_ls__nand4bb_1.spice
index ab02a54..e2b6322 100644
--- a/cells/nand4bb/sky130_fd_sc_ls__nand4bb_1.spice
+++ b/cells/nand4bb/sky130_fd_sc_ls__nand4bb_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nand4bb_1.spice
-* Created: Fri Aug 28 13:35:54 2020
+* Created: Wed Sep 2 11:13:28 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nand4bb/sky130_fd_sc_ls__nand4bb_2.lvs.report b/cells/nand4bb/sky130_fd_sc_ls__nand4bb_2.lvs.report
new file mode 100644
index 0000000..0037841
--- /dev/null
+++ b/cells/nand4bb/sky130_fd_sc_ls__nand4bb_2.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__nand4bb_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__nand4bb_2.sp ('sky130_fd_sc_ls__nand4bb_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/nand4bb/sky130_fd_sc_ls__nand4bb_2.spice ('sky130_fd_sc_ls__nand4bb_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:13:32 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__nand4bb_2 sky130_fd_sc_ls__nand4bb_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__nand4bb_2
+SOURCE CELL NAME: sky130_fd_sc_ls__nand4bb_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 14 14
+
+ Instances: 10 10 MN (4 pins)
+ 10 10 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 21 20
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 11 11
+
+ Instances: 2 2 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 1 SMN4 (6 pins)
+ ------ ------
+ Total Inst: 9 9
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 6 6 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN4
+ ------- ------- --------- ---------
+ Total Inst: 9 9 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 16 layout mos transistors were reduced to 8.
+ 8 mos transistors were deleted by parallel reduction.
+ 16 source mos transistors were reduced to 8.
+ 8 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A_N B_N C D VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nand4bb/sky130_fd_sc_ls__nand4bb_2.pex.spice b/cells/nand4bb/sky130_fd_sc_ls__nand4bb_2.pex.spice
index a7eeac6..1b12aa1 100644
--- a/cells/nand4bb/sky130_fd_sc_ls__nand4bb_2.pex.spice
+++ b/cells/nand4bb/sky130_fd_sc_ls__nand4bb_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nand4bb_2.pex.spice
-* Created: Fri Aug 28 13:36:11 2020
+* Created: Wed Sep 2 11:13:36 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nand4bb/sky130_fd_sc_ls__nand4bb_2.pxi.spice b/cells/nand4bb/sky130_fd_sc_ls__nand4bb_2.pxi.spice
index 9aa57e2..5ef825e 100644
--- a/cells/nand4bb/sky130_fd_sc_ls__nand4bb_2.pxi.spice
+++ b/cells/nand4bb/sky130_fd_sc_ls__nand4bb_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nand4bb_2.pxi.spice
-* Created: Fri Aug 28 13:36:11 2020
+* Created: Wed Sep 2 11:13:36 2020
*
x_PM_SKY130_FD_SC_LS__NAND4BB_2%A_N N_A_N_c_111_n N_A_N_M1011_g N_A_N_M1018_g
+ A_N N_A_N_c_113_n PM_SKY130_FD_SC_LS__NAND4BB_2%A_N
diff --git a/cells/nand4bb/sky130_fd_sc_ls__nand4bb_2.spice b/cells/nand4bb/sky130_fd_sc_ls__nand4bb_2.spice
index 619dfe4..9c5c873 100644
--- a/cells/nand4bb/sky130_fd_sc_ls__nand4bb_2.spice
+++ b/cells/nand4bb/sky130_fd_sc_ls__nand4bb_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nand4bb_2.spice
-* Created: Fri Aug 28 13:36:11 2020
+* Created: Wed Sep 2 11:13:36 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nand4bb/sky130_fd_sc_ls__nand4bb_4.lvs.report b/cells/nand4bb/sky130_fd_sc_ls__nand4bb_4.lvs.report
new file mode 100644
index 0000000..255b589
--- /dev/null
+++ b/cells/nand4bb/sky130_fd_sc_ls__nand4bb_4.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__nand4bb_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__nand4bb_4.sp ('sky130_fd_sc_ls__nand4bb_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/nand4bb/sky130_fd_sc_ls__nand4bb_4.spice ('sky130_fd_sc_ls__nand4bb_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:13:40 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__nand4bb_4 sky130_fd_sc_ls__nand4bb_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__nand4bb_4
+SOURCE CELL NAME: sky130_fd_sc_ls__nand4bb_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 14 14
+
+ Instances: 18 18 MN (4 pins)
+ 20 20 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 39 38
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 11 11
+
+ Instances: 2 2 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 1 SMN4 (6 pins)
+ ------ ------
+ Total Inst: 9 9
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 6 6 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN4
+ ------- ------- --------- ---------
+ Total Inst: 9 9 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 36 layout mos transistors were reduced to 10.
+ 26 mos transistors were deleted by parallel reduction.
+ 36 source mos transistors were reduced to 10.
+ 26 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A_N B_N C D VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nand4bb/sky130_fd_sc_ls__nand4bb_4.pex.spice b/cells/nand4bb/sky130_fd_sc_ls__nand4bb_4.pex.spice
index a58caf4..cfbf898 100644
--- a/cells/nand4bb/sky130_fd_sc_ls__nand4bb_4.pex.spice
+++ b/cells/nand4bb/sky130_fd_sc_ls__nand4bb_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nand4bb_4.pex.spice
-* Created: Fri Aug 28 13:36:31 2020
+* Created: Wed Sep 2 11:13:43 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nand4bb/sky130_fd_sc_ls__nand4bb_4.pxi.spice b/cells/nand4bb/sky130_fd_sc_ls__nand4bb_4.pxi.spice
index b198dfe..9f590ff 100644
--- a/cells/nand4bb/sky130_fd_sc_ls__nand4bb_4.pxi.spice
+++ b/cells/nand4bb/sky130_fd_sc_ls__nand4bb_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nand4bb_4.pxi.spice
-* Created: Fri Aug 28 13:36:31 2020
+* Created: Wed Sep 2 11:13:43 2020
*
x_PM_SKY130_FD_SC_LS__NAND4BB_4%A_N N_A_N_M1018_g N_A_N_c_178_n N_A_N_c_182_n
+ N_A_N_M1024_g N_A_N_c_183_n N_A_N_M1026_g N_A_N_c_184_n A_N N_A_N_c_180_n
diff --git a/cells/nand4bb/sky130_fd_sc_ls__nand4bb_4.spice b/cells/nand4bb/sky130_fd_sc_ls__nand4bb_4.spice
index 4d054c8..ee6cbc9 100644
--- a/cells/nand4bb/sky130_fd_sc_ls__nand4bb_4.spice
+++ b/cells/nand4bb/sky130_fd_sc_ls__nand4bb_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nand4bb_4.spice
-* Created: Fri Aug 28 13:36:31 2020
+* Created: Wed Sep 2 11:13:43 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nor2/sky130_fd_sc_ls__nor2_1.lvs.report b/cells/nor2/sky130_fd_sc_ls__nor2_1.lvs.report
new file mode 100644
index 0000000..b7e08f2
--- /dev/null
+++ b/cells/nor2/sky130_fd_sc_ls__nor2_1.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__nor2_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__nor2_1.sp ('sky130_fd_sc_ls__nor2_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/nor2/sky130_fd_sc_ls__nor2_1.spice ('sky130_fd_sc_ls__nor2_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:13:47 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__nor2_1 sky130_fd_sc_ls__nor2_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__nor2_1
+SOURCE CELL NAME: sky130_fd_sc_ls__nor2_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 5 4
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 7 7
+
+ Instances: 2 2 MN (4 pins)
+ 1 1 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 7 7 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 1 1 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A B VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nor2/sky130_fd_sc_ls__nor2_1.pex.spice b/cells/nor2/sky130_fd_sc_ls__nor2_1.pex.spice
index e2bbe97..bb63bf2 100644
--- a/cells/nor2/sky130_fd_sc_ls__nor2_1.pex.spice
+++ b/cells/nor2/sky130_fd_sc_ls__nor2_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nor2_1.pex.spice
-* Created: Fri Aug 28 13:36:41 2020
+* Created: Wed Sep 2 11:13:51 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nor2/sky130_fd_sc_ls__nor2_1.pxi.spice b/cells/nor2/sky130_fd_sc_ls__nor2_1.pxi.spice
index db5dfca..2e03e02 100644
--- a/cells/nor2/sky130_fd_sc_ls__nor2_1.pxi.spice
+++ b/cells/nor2/sky130_fd_sc_ls__nor2_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nor2_1.pxi.spice
-* Created: Fri Aug 28 13:36:41 2020
+* Created: Wed Sep 2 11:13:51 2020
*
x_PM_SKY130_FD_SC_LS__NOR2_1%A N_A_c_27_n N_A_M1001_g N_A_M1003_g A N_A_c_29_n
+ PM_SKY130_FD_SC_LS__NOR2_1%A
diff --git a/cells/nor2/sky130_fd_sc_ls__nor2_1.spice b/cells/nor2/sky130_fd_sc_ls__nor2_1.spice
index 14cccc1..9bef67b 100644
--- a/cells/nor2/sky130_fd_sc_ls__nor2_1.spice
+++ b/cells/nor2/sky130_fd_sc_ls__nor2_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nor2_1.spice
-* Created: Fri Aug 28 13:36:41 2020
+* Created: Wed Sep 2 11:13:51 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nor2/sky130_fd_sc_ls__nor2_2.lvs.report b/cells/nor2/sky130_fd_sc_ls__nor2_2.lvs.report
new file mode 100644
index 0000000..4278a78
--- /dev/null
+++ b/cells/nor2/sky130_fd_sc_ls__nor2_2.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__nor2_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__nor2_2.sp ('sky130_fd_sc_ls__nor2_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/nor2/sky130_fd_sc_ls__nor2_2.spice ('sky130_fd_sc_ls__nor2_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:13:55 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__nor2_2 sky130_fd_sc_ls__nor2_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__nor2_2
+SOURCE CELL NAME: sky130_fd_sc_ls__nor2_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 2 2 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 7 6
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 7 7
+
+ Instances: 2 2 MN (4 pins)
+ 1 1 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 7 7 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 1 1 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B A Y VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nor2/sky130_fd_sc_ls__nor2_2.pex.spice b/cells/nor2/sky130_fd_sc_ls__nor2_2.pex.spice
index e8e4474..1763012 100644
--- a/cells/nor2/sky130_fd_sc_ls__nor2_2.pex.spice
+++ b/cells/nor2/sky130_fd_sc_ls__nor2_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nor2_2.pex.spice
-* Created: Fri Aug 28 13:36:52 2020
+* Created: Wed Sep 2 11:13:58 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nor2/sky130_fd_sc_ls__nor2_2.pxi.spice b/cells/nor2/sky130_fd_sc_ls__nor2_2.pxi.spice
index 6966d63..e579b4e 100644
--- a/cells/nor2/sky130_fd_sc_ls__nor2_2.pxi.spice
+++ b/cells/nor2/sky130_fd_sc_ls__nor2_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nor2_2.pxi.spice
-* Created: Fri Aug 28 13:36:52 2020
+* Created: Wed Sep 2 11:13:58 2020
*
x_PM_SKY130_FD_SC_LS__NOR2_2%B N_B_M1003_g N_B_M1001_g N_B_c_40_n N_B_c_45_n
+ N_B_M1004_g N_B_c_41_n N_B_c_42_n N_B_c_47_n B PM_SKY130_FD_SC_LS__NOR2_2%B
diff --git a/cells/nor2/sky130_fd_sc_ls__nor2_2.spice b/cells/nor2/sky130_fd_sc_ls__nor2_2.spice
index 85c9cd8..8e71fbe 100644
--- a/cells/nor2/sky130_fd_sc_ls__nor2_2.spice
+++ b/cells/nor2/sky130_fd_sc_ls__nor2_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nor2_2.spice
-* Created: Fri Aug 28 13:36:52 2020
+* Created: Wed Sep 2 11:13:58 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nor2/sky130_fd_sc_ls__nor2_4.lvs.report b/cells/nor2/sky130_fd_sc_ls__nor2_4.lvs.report
new file mode 100644
index 0000000..2a50628
--- /dev/null
+++ b/cells/nor2/sky130_fd_sc_ls__nor2_4.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__nor2_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__nor2_4.sp ('sky130_fd_sc_ls__nor2_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/nor2/sky130_fd_sc_ls__nor2_4.spice ('sky130_fd_sc_ls__nor2_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:14:02 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__nor2_4 sky130_fd_sc_ls__nor2_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__nor2_4
+SOURCE CELL NAME: sky130_fd_sc_ls__nor2_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 4 4 MN (4 pins)
+ 8 8 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 7 7
+
+ Instances: 2 2 MN (4 pins)
+ 1 1 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 7 7 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 1 1 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 12 layout mos transistors were reduced to 4.
+ 8 mos transistors were deleted by parallel reduction.
+ 12 source mos transistors were reduced to 4.
+ 8 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A B VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nor2/sky130_fd_sc_ls__nor2_4.pex.spice b/cells/nor2/sky130_fd_sc_ls__nor2_4.pex.spice
index 86709ec..9938ccf 100644
--- a/cells/nor2/sky130_fd_sc_ls__nor2_4.pex.spice
+++ b/cells/nor2/sky130_fd_sc_ls__nor2_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nor2_4.pex.spice
-* Created: Fri Aug 28 13:37:01 2020
+* Created: Wed Sep 2 11:14:05 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nor2/sky130_fd_sc_ls__nor2_4.pxi.spice b/cells/nor2/sky130_fd_sc_ls__nor2_4.pxi.spice
index fceed38..62000c6 100644
--- a/cells/nor2/sky130_fd_sc_ls__nor2_4.pxi.spice
+++ b/cells/nor2/sky130_fd_sc_ls__nor2_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nor2_4.pxi.spice
-* Created: Fri Aug 28 13:37:01 2020
+* Created: Wed Sep 2 11:14:05 2020
*
x_PM_SKY130_FD_SC_LS__NOR2_4%A N_A_c_54_n N_A_M1000_g N_A_c_50_n N_A_M1001_g
+ N_A_c_55_n N_A_M1007_g N_A_c_56_n N_A_M1008_g N_A_c_51_n N_A_M1003_g
diff --git a/cells/nor2/sky130_fd_sc_ls__nor2_4.spice b/cells/nor2/sky130_fd_sc_ls__nor2_4.spice
index 8df3e1b..6f1aec9 100644
--- a/cells/nor2/sky130_fd_sc_ls__nor2_4.spice
+++ b/cells/nor2/sky130_fd_sc_ls__nor2_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nor2_4.spice
-* Created: Fri Aug 28 13:37:01 2020
+* Created: Wed Sep 2 11:14:05 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nor2/sky130_fd_sc_ls__nor2_8.lvs.report b/cells/nor2/sky130_fd_sc_ls__nor2_8.lvs.report
new file mode 100644
index 0000000..b8c79f5
--- /dev/null
+++ b/cells/nor2/sky130_fd_sc_ls__nor2_8.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__nor2_8.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__nor2_8.sp ('sky130_fd_sc_ls__nor2_8')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/nor2/sky130_fd_sc_ls__nor2_8.spice ('sky130_fd_sc_ls__nor2_8')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:14:09 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__nor2_8 sky130_fd_sc_ls__nor2_8
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__nor2_8
+SOURCE CELL NAME: sky130_fd_sc_ls__nor2_8
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 8 8 MN (4 pins)
+ 16 16 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 25 24
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 7 7
+
+ Instances: 2 2 MN (4 pins)
+ 1 1 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 7 7 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 1 1 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 24 layout mos transistors were reduced to 4.
+ 20 mos transistors were deleted by parallel reduction.
+ 24 source mos transistors were reduced to 4.
+ 20 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A B VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nor2/sky130_fd_sc_ls__nor2_8.pex.spice b/cells/nor2/sky130_fd_sc_ls__nor2_8.pex.spice
index a0a8955..021da57 100644
--- a/cells/nor2/sky130_fd_sc_ls__nor2_8.pex.spice
+++ b/cells/nor2/sky130_fd_sc_ls__nor2_8.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nor2_8.pex.spice
-* Created: Fri Aug 28 13:37:18 2020
+* Created: Wed Sep 2 11:14:13 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nor2/sky130_fd_sc_ls__nor2_8.pxi.spice b/cells/nor2/sky130_fd_sc_ls__nor2_8.pxi.spice
index 8e305e0..156dfb4 100644
--- a/cells/nor2/sky130_fd_sc_ls__nor2_8.pxi.spice
+++ b/cells/nor2/sky130_fd_sc_ls__nor2_8.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nor2_8.pxi.spice
-* Created: Fri Aug 28 13:37:18 2020
+* Created: Wed Sep 2 11:14:13 2020
*
x_PM_SKY130_FD_SC_LS__NOR2_8%A N_A_c_142_n N_A_M1000_g N_A_c_130_n N_A_c_131_n
+ N_A_c_145_n N_A_M1005_g N_A_c_132_n N_A_c_147_n N_A_M1013_g N_A_c_133_n
diff --git a/cells/nor2/sky130_fd_sc_ls__nor2_8.spice b/cells/nor2/sky130_fd_sc_ls__nor2_8.spice
index 6ed47e1..e8ac25d 100644
--- a/cells/nor2/sky130_fd_sc_ls__nor2_8.spice
+++ b/cells/nor2/sky130_fd_sc_ls__nor2_8.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nor2_8.spice
-* Created: Fri Aug 28 13:37:18 2020
+* Created: Wed Sep 2 11:14:13 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nor2b/sky130_fd_sc_ls__nor2b_1.lvs.report b/cells/nor2b/sky130_fd_sc_ls__nor2b_1.lvs.report
new file mode 100644
index 0000000..7bdec0b
--- /dev/null
+++ b/cells/nor2b/sky130_fd_sc_ls__nor2b_1.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__nor2b_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__nor2b_1.sp ('sky130_fd_sc_ls__nor2b_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/nor2b/sky130_fd_sc_ls__nor2b_1.spice ('sky130_fd_sc_ls__nor2b_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:14:17 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__nor2b_1 sky130_fd_sc_ls__nor2b_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__nor2b_1
+SOURCE CELL NAME: sky130_fd_sc_ls__nor2b_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 9 9
+
+ Instances: 3 3 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 7 6
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 3 3 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 3 3 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B_N A VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nor2b/sky130_fd_sc_ls__nor2b_1.pex.spice b/cells/nor2b/sky130_fd_sc_ls__nor2b_1.pex.spice
index 7b1c9b1..76e490d 100644
--- a/cells/nor2b/sky130_fd_sc_ls__nor2b_1.pex.spice
+++ b/cells/nor2b/sky130_fd_sc_ls__nor2b_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nor2b_1.pex.spice
-* Created: Fri Aug 28 13:37:39 2020
+* Created: Wed Sep 2 11:14:20 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nor2b/sky130_fd_sc_ls__nor2b_1.pxi.spice b/cells/nor2b/sky130_fd_sc_ls__nor2b_1.pxi.spice
index 60355ad..43addf6 100644
--- a/cells/nor2b/sky130_fd_sc_ls__nor2b_1.pxi.spice
+++ b/cells/nor2b/sky130_fd_sc_ls__nor2b_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nor2b_1.pxi.spice
-* Created: Fri Aug 28 13:37:39 2020
+* Created: Wed Sep 2 11:14:20 2020
*
x_PM_SKY130_FD_SC_LS__NOR2B_1%B_N N_B_N_c_40_n N_B_N_M1003_g N_B_N_c_41_n
+ N_B_N_M1004_g N_B_N_c_42_n B_N PM_SKY130_FD_SC_LS__NOR2B_1%B_N
diff --git a/cells/nor2b/sky130_fd_sc_ls__nor2b_1.spice b/cells/nor2b/sky130_fd_sc_ls__nor2b_1.spice
index f8844ff..eccf724 100644
--- a/cells/nor2b/sky130_fd_sc_ls__nor2b_1.spice
+++ b/cells/nor2b/sky130_fd_sc_ls__nor2b_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nor2b_1.spice
-* Created: Fri Aug 28 13:37:39 2020
+* Created: Wed Sep 2 11:14:20 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nor2b/sky130_fd_sc_ls__nor2b_2.lvs.report b/cells/nor2b/sky130_fd_sc_ls__nor2b_2.lvs.report
new file mode 100644
index 0000000..1b9e55f
--- /dev/null
+++ b/cells/nor2b/sky130_fd_sc_ls__nor2b_2.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__nor2b_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__nor2b_2.sp ('sky130_fd_sc_ls__nor2b_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/nor2b/sky130_fd_sc_ls__nor2b_2.spice ('sky130_fd_sc_ls__nor2b_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:14:24 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__nor2b_2 sky130_fd_sc_ls__nor2b_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__nor2b_2
+SOURCE CELL NAME: sky130_fd_sc_ls__nor2b_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 9 9
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 3 3 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 3 3 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 8 layout mos transistors were reduced to 4.
+ 4 mos transistors were deleted by parallel reduction.
+ 8 source mos transistors were reduced to 4.
+ 4 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B_N A VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nor2b/sky130_fd_sc_ls__nor2b_2.pex.spice b/cells/nor2b/sky130_fd_sc_ls__nor2b_2.pex.spice
index 02c6368..66ab202 100644
--- a/cells/nor2b/sky130_fd_sc_ls__nor2b_2.pex.spice
+++ b/cells/nor2b/sky130_fd_sc_ls__nor2b_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nor2b_2.pex.spice
-* Created: Fri Aug 28 13:37:50 2020
+* Created: Wed Sep 2 11:14:27 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nor2b/sky130_fd_sc_ls__nor2b_2.pxi.spice b/cells/nor2b/sky130_fd_sc_ls__nor2b_2.pxi.spice
index 3aeba2e..67f94a3 100644
--- a/cells/nor2b/sky130_fd_sc_ls__nor2b_2.pxi.spice
+++ b/cells/nor2b/sky130_fd_sc_ls__nor2b_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nor2b_2.pxi.spice
-* Created: Fri Aug 28 13:37:50 2020
+* Created: Wed Sep 2 11:14:27 2020
*
x_PM_SKY130_FD_SC_LS__NOR2B_2%B_N N_B_N_c_63_n N_B_N_M1008_g N_B_N_M1002_g B_N
+ N_B_N_c_62_n PM_SKY130_FD_SC_LS__NOR2B_2%B_N
diff --git a/cells/nor2b/sky130_fd_sc_ls__nor2b_2.spice b/cells/nor2b/sky130_fd_sc_ls__nor2b_2.spice
index ad9dca4..b38bc95 100644
--- a/cells/nor2b/sky130_fd_sc_ls__nor2b_2.spice
+++ b/cells/nor2b/sky130_fd_sc_ls__nor2b_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nor2b_2.spice
-* Created: Fri Aug 28 13:37:50 2020
+* Created: Wed Sep 2 11:14:27 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nor2b/sky130_fd_sc_ls__nor2b_4.lvs.report b/cells/nor2b/sky130_fd_sc_ls__nor2b_4.lvs.report
new file mode 100644
index 0000000..7979075
--- /dev/null
+++ b/cells/nor2b/sky130_fd_sc_ls__nor2b_4.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__nor2b_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__nor2b_4.sp ('sky130_fd_sc_ls__nor2b_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/nor2b/sky130_fd_sc_ls__nor2b_4.spice ('sky130_fd_sc_ls__nor2b_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:14:31 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__nor2b_4 sky130_fd_sc_ls__nor2b_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__nor2b_4
+SOURCE CELL NAME: sky130_fd_sc_ls__nor2b_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 9 9
+
+ Instances: 5 5 MN (4 pins)
+ 10 10 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 16 15
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 3 3 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 3 3 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 14 layout mos transistors were reduced to 5.
+ 9 mos transistors were deleted by parallel reduction.
+ 14 source mos transistors were reduced to 5.
+ 9 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A B_N VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nor2b/sky130_fd_sc_ls__nor2b_4.pex.spice b/cells/nor2b/sky130_fd_sc_ls__nor2b_4.pex.spice
index d466991..e9f7366 100644
--- a/cells/nor2b/sky130_fd_sc_ls__nor2b_4.pex.spice
+++ b/cells/nor2b/sky130_fd_sc_ls__nor2b_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nor2b_4.pex.spice
-* Created: Fri Aug 28 13:38:00 2020
+* Created: Wed Sep 2 11:14:34 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nor2b/sky130_fd_sc_ls__nor2b_4.pxi.spice b/cells/nor2b/sky130_fd_sc_ls__nor2b_4.pxi.spice
index b8af007..2c05ce4 100644
--- a/cells/nor2b/sky130_fd_sc_ls__nor2b_4.pxi.spice
+++ b/cells/nor2b/sky130_fd_sc_ls__nor2b_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nor2b_4.pxi.spice
-* Created: Fri Aug 28 13:38:00 2020
+* Created: Wed Sep 2 11:14:34 2020
*
x_PM_SKY130_FD_SC_LS__NOR2B_4%A N_A_c_80_n N_A_c_91_n N_A_M1006_g N_A_c_81_n
+ N_A_c_93_n N_A_M1007_g N_A_c_82_n N_A_c_95_n N_A_M1011_g N_A_c_83_n
diff --git a/cells/nor2b/sky130_fd_sc_ls__nor2b_4.spice b/cells/nor2b/sky130_fd_sc_ls__nor2b_4.spice
index adf161e..3299d56 100644
--- a/cells/nor2b/sky130_fd_sc_ls__nor2b_4.spice
+++ b/cells/nor2b/sky130_fd_sc_ls__nor2b_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nor2b_4.spice
-* Created: Fri Aug 28 13:38:00 2020
+* Created: Wed Sep 2 11:14:34 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nor3/sky130_fd_sc_ls__nor3_1.lvs.report b/cells/nor3/sky130_fd_sc_ls__nor3_1.lvs.report
new file mode 100644
index 0000000..5f1a657
--- /dev/null
+++ b/cells/nor3/sky130_fd_sc_ls__nor3_1.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__nor3_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__nor3_1.sp ('sky130_fd_sc_ls__nor3_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/nor3/sky130_fd_sc_ls__nor3_1.spice ('sky130_fd_sc_ls__nor3_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:14:38 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__nor3_1 sky130_fd_sc_ls__nor3_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__nor3_1
+SOURCE CELL NAME: sky130_fd_sc_ls__nor3_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 10 10
+
+ Instances: 3 3 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 7 6
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 8 8
+
+ Instances: 3 3 MN (4 pins)
+ 1 1 SMP3 (5 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 3 3 0 0 MN(NSHORT)
+ 1 1 0 0 SMP3
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A B C VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nor3/sky130_fd_sc_ls__nor3_1.pex.spice b/cells/nor3/sky130_fd_sc_ls__nor3_1.pex.spice
index 136e59e..f78f31c 100644
--- a/cells/nor3/sky130_fd_sc_ls__nor3_1.pex.spice
+++ b/cells/nor3/sky130_fd_sc_ls__nor3_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nor3_1.pex.spice
-* Created: Fri Aug 28 13:38:10 2020
+* Created: Wed Sep 2 11:14:42 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nor3/sky130_fd_sc_ls__nor3_1.pxi.spice b/cells/nor3/sky130_fd_sc_ls__nor3_1.pxi.spice
index 9805d3f..4b03823 100644
--- a/cells/nor3/sky130_fd_sc_ls__nor3_1.pxi.spice
+++ b/cells/nor3/sky130_fd_sc_ls__nor3_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nor3_1.pxi.spice
-* Created: Fri Aug 28 13:38:10 2020
+* Created: Wed Sep 2 11:14:42 2020
*
x_PM_SKY130_FD_SC_LS__NOR3_1%A N_A_c_38_n N_A_M1004_g N_A_c_39_n N_A_M1003_g A A
+ PM_SKY130_FD_SC_LS__NOR3_1%A
diff --git a/cells/nor3/sky130_fd_sc_ls__nor3_1.spice b/cells/nor3/sky130_fd_sc_ls__nor3_1.spice
index 7367784..52663d5 100644
--- a/cells/nor3/sky130_fd_sc_ls__nor3_1.spice
+++ b/cells/nor3/sky130_fd_sc_ls__nor3_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nor3_1.spice
-* Created: Fri Aug 28 13:38:10 2020
+* Created: Wed Sep 2 11:14:42 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nor3/sky130_fd_sc_ls__nor3_2.lvs.report b/cells/nor3/sky130_fd_sc_ls__nor3_2.lvs.report
new file mode 100644
index 0000000..7ed42ab
--- /dev/null
+++ b/cells/nor3/sky130_fd_sc_ls__nor3_2.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__nor3_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__nor3_2.sp ('sky130_fd_sc_ls__nor3_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/nor3/sky130_fd_sc_ls__nor3_2.spice ('sky130_fd_sc_ls__nor3_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:14:46 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__nor3_2 sky130_fd_sc_ls__nor3_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__nor3_2
+SOURCE CELL NAME: sky130_fd_sc_ls__nor3_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 10 10
+
+ Instances: 3 3 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 10 9
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 8 8
+
+ Instances: 3 3 MN (4 pins)
+ 1 1 SMP3 (5 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 3 3 0 0 MN(NSHORT)
+ 1 1 0 0 SMP3
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 6 layout mos transistors were reduced to 3.
+ 3 mos transistors were deleted by parallel reduction.
+ 6 source mos transistors were reduced to 3.
+ 3 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB C B A Y VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nor3/sky130_fd_sc_ls__nor3_2.pex.spice b/cells/nor3/sky130_fd_sc_ls__nor3_2.pex.spice
index a924e36..1d418ed 100644
--- a/cells/nor3/sky130_fd_sc_ls__nor3_2.pex.spice
+++ b/cells/nor3/sky130_fd_sc_ls__nor3_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nor3_2.pex.spice
-* Created: Fri Aug 28 13:38:28 2020
+* Created: Wed Sep 2 11:14:49 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nor3/sky130_fd_sc_ls__nor3_2.pxi.spice b/cells/nor3/sky130_fd_sc_ls__nor3_2.pxi.spice
index 76d43d8..0a05ee0 100644
--- a/cells/nor3/sky130_fd_sc_ls__nor3_2.pxi.spice
+++ b/cells/nor3/sky130_fd_sc_ls__nor3_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nor3_2.pxi.spice
-* Created: Fri Aug 28 13:38:28 2020
+* Created: Wed Sep 2 11:14:49 2020
*
x_PM_SKY130_FD_SC_LS__NOR3_2%C N_C_c_57_n N_C_M1006_g N_C_c_60_n N_C_M1003_g
+ N_C_c_61_n N_C_M1004_g C N_C_c_59_n PM_SKY130_FD_SC_LS__NOR3_2%C
diff --git a/cells/nor3/sky130_fd_sc_ls__nor3_2.spice b/cells/nor3/sky130_fd_sc_ls__nor3_2.spice
index 3705c46..cf7c552 100644
--- a/cells/nor3/sky130_fd_sc_ls__nor3_2.spice
+++ b/cells/nor3/sky130_fd_sc_ls__nor3_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nor3_2.spice
-* Created: Fri Aug 28 13:38:28 2020
+* Created: Wed Sep 2 11:14:49 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nor3/sky130_fd_sc_ls__nor3_4.lvs.report b/cells/nor3/sky130_fd_sc_ls__nor3_4.lvs.report
new file mode 100644
index 0000000..fc39c40
--- /dev/null
+++ b/cells/nor3/sky130_fd_sc_ls__nor3_4.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__nor3_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__nor3_4.sp ('sky130_fd_sc_ls__nor3_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/nor3/sky130_fd_sc_ls__nor3_4.spice ('sky130_fd_sc_ls__nor3_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:14:53 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__nor3_4 sky130_fd_sc_ls__nor3_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__nor3_4
+SOURCE CELL NAME: sky130_fd_sc_ls__nor3_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 10 10
+
+ Instances: 6 6 MN (4 pins)
+ 12 12 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 19 18
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 8 8
+
+ Instances: 3 3 MN (4 pins)
+ 1 1 SMP3 (5 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 3 3 0 0 MN(NSHORT)
+ 1 1 0 0 SMP3
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 18 layout mos transistors were reduced to 6.
+ 12 mos transistors were deleted by parallel reduction.
+ 18 source mos transistors were reduced to 6.
+ 12 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A B C VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nor3/sky130_fd_sc_ls__nor3_4.pex.spice b/cells/nor3/sky130_fd_sc_ls__nor3_4.pex.spice
index 36ef66f..e16edc6 100644
--- a/cells/nor3/sky130_fd_sc_ls__nor3_4.pex.spice
+++ b/cells/nor3/sky130_fd_sc_ls__nor3_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nor3_4.pex.spice
-* Created: Fri Aug 28 13:38:48 2020
+* Created: Wed Sep 2 11:14:56 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nor3/sky130_fd_sc_ls__nor3_4.pxi.spice b/cells/nor3/sky130_fd_sc_ls__nor3_4.pxi.spice
index 3203e9f..104792c 100644
--- a/cells/nor3/sky130_fd_sc_ls__nor3_4.pxi.spice
+++ b/cells/nor3/sky130_fd_sc_ls__nor3_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nor3_4.pxi.spice
-* Created: Fri Aug 28 13:38:48 2020
+* Created: Wed Sep 2 11:14:56 2020
*
x_PM_SKY130_FD_SC_LS__NOR3_4%A N_A_M1002_g N_A_c_115_n N_A_M1000_g N_A_M1014_g
+ N_A_c_116_n N_A_M1004_g N_A_c_117_n N_A_M1010_g N_A_c_118_n N_A_M1011_g
diff --git a/cells/nor3/sky130_fd_sc_ls__nor3_4.spice b/cells/nor3/sky130_fd_sc_ls__nor3_4.spice
index ccae5a7..2033cad 100644
--- a/cells/nor3/sky130_fd_sc_ls__nor3_4.spice
+++ b/cells/nor3/sky130_fd_sc_ls__nor3_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nor3_4.spice
-* Created: Fri Aug 28 13:38:48 2020
+* Created: Wed Sep 2 11:14:56 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nor3b/sky130_fd_sc_ls__nor3b_1.lvs.report b/cells/nor3b/sky130_fd_sc_ls__nor3b_1.lvs.report
new file mode 100644
index 0000000..769cdfc
--- /dev/null
+++ b/cells/nor3b/sky130_fd_sc_ls__nor3b_1.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__nor3b_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__nor3b_1.sp ('sky130_fd_sc_ls__nor3b_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/nor3b/sky130_fd_sc_ls__nor3b_1.spice ('sky130_fd_sc_ls__nor3b_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:15:00 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__nor3b_1 sky130_fd_sc_ls__nor3b_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__nor3b_1
+SOURCE CELL NAME: sky130_fd_sc_ls__nor3b_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 11 11
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 9 9
+
+ Instances: 4 4 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMP3 (5 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 4 4 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP3
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB C_N A B VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nor3b/sky130_fd_sc_ls__nor3b_1.pex.spice b/cells/nor3b/sky130_fd_sc_ls__nor3b_1.pex.spice
index 14e1557..eb5cec4 100644
--- a/cells/nor3b/sky130_fd_sc_ls__nor3b_1.pex.spice
+++ b/cells/nor3b/sky130_fd_sc_ls__nor3b_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nor3b_1.pex.spice
-* Created: Fri Aug 28 13:38:58 2020
+* Created: Wed Sep 2 11:15:03 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nor3b/sky130_fd_sc_ls__nor3b_1.pxi.spice b/cells/nor3b/sky130_fd_sc_ls__nor3b_1.pxi.spice
index 222fef7..950e03e 100644
--- a/cells/nor3b/sky130_fd_sc_ls__nor3b_1.pxi.spice
+++ b/cells/nor3b/sky130_fd_sc_ls__nor3b_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nor3b_1.pxi.spice
-* Created: Fri Aug 28 13:38:58 2020
+* Created: Wed Sep 2 11:15:03 2020
*
x_PM_SKY130_FD_SC_LS__NOR3B_1%C_N N_C_N_c_48_n N_C_N_M1003_g N_C_N_c_49_n
+ N_C_N_M1004_g C_N PM_SKY130_FD_SC_LS__NOR3B_1%C_N
diff --git a/cells/nor3b/sky130_fd_sc_ls__nor3b_1.spice b/cells/nor3b/sky130_fd_sc_ls__nor3b_1.spice
index 5c98f0a..27ab8c9 100644
--- a/cells/nor3b/sky130_fd_sc_ls__nor3b_1.spice
+++ b/cells/nor3b/sky130_fd_sc_ls__nor3b_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nor3b_1.spice
-* Created: Fri Aug 28 13:38:58 2020
+* Created: Wed Sep 2 11:15:03 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nor3b/sky130_fd_sc_ls__nor3b_2.lvs.report b/cells/nor3b/sky130_fd_sc_ls__nor3b_2.lvs.report
new file mode 100644
index 0000000..10ecac3
--- /dev/null
+++ b/cells/nor3b/sky130_fd_sc_ls__nor3b_2.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__nor3b_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__nor3b_2.sp ('sky130_fd_sc_ls__nor3b_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/nor3b/sky130_fd_sc_ls__nor3b_2.spice ('sky130_fd_sc_ls__nor3b_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:15:07 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__nor3b_2 sky130_fd_sc_ls__nor3b_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__nor3b_2
+SOURCE CELL NAME: sky130_fd_sc_ls__nor3b_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 11 11
+
+ Instances: 7 7 MN (4 pins)
+ 7 7 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 15 14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 9 9
+
+ Instances: 4 4 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMP3 (5 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 4 4 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP3
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 12 layout mos transistors were reduced to 6.
+ 6 mos transistors were deleted by parallel reduction.
+ 12 source mos transistors were reduced to 6.
+ 6 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB C_N B A VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nor3b/sky130_fd_sc_ls__nor3b_2.pex.spice b/cells/nor3b/sky130_fd_sc_ls__nor3b_2.pex.spice
index a4ff2e7..60ae836 100644
--- a/cells/nor3b/sky130_fd_sc_ls__nor3b_2.pex.spice
+++ b/cells/nor3b/sky130_fd_sc_ls__nor3b_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nor3b_2.pex.spice
-* Created: Fri Aug 28 13:39:08 2020
+* Created: Wed Sep 2 11:15:10 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nor3b/sky130_fd_sc_ls__nor3b_2.pxi.spice b/cells/nor3b/sky130_fd_sc_ls__nor3b_2.pxi.spice
index 699e92b..9b0d543 100644
--- a/cells/nor3b/sky130_fd_sc_ls__nor3b_2.pxi.spice
+++ b/cells/nor3b/sky130_fd_sc_ls__nor3b_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nor3b_2.pxi.spice
-* Created: Fri Aug 28 13:39:08 2020
+* Created: Wed Sep 2 11:15:10 2020
*
x_PM_SKY130_FD_SC_LS__NOR3B_2%C_N N_C_N_M1007_g N_C_N_c_81_n N_C_N_M1011_g C_N
+ PM_SKY130_FD_SC_LS__NOR3B_2%C_N
diff --git a/cells/nor3b/sky130_fd_sc_ls__nor3b_2.spice b/cells/nor3b/sky130_fd_sc_ls__nor3b_2.spice
index 05b42bf..e527aca 100644
--- a/cells/nor3b/sky130_fd_sc_ls__nor3b_2.spice
+++ b/cells/nor3b/sky130_fd_sc_ls__nor3b_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nor3b_2.spice
-* Created: Fri Aug 28 13:39:08 2020
+* Created: Wed Sep 2 11:15:10 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nor3b/sky130_fd_sc_ls__nor3b_4.lvs.report b/cells/nor3b/sky130_fd_sc_ls__nor3b_4.lvs.report
new file mode 100644
index 0000000..f736836
--- /dev/null
+++ b/cells/nor3b/sky130_fd_sc_ls__nor3b_4.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__nor3b_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__nor3b_4.sp ('sky130_fd_sc_ls__nor3b_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/nor3b/sky130_fd_sc_ls__nor3b_4.spice ('sky130_fd_sc_ls__nor3b_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:15:13 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__nor3b_4 sky130_fd_sc_ls__nor3b_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__nor3b_4
+SOURCE CELL NAME: sky130_fd_sc_ls__nor3b_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 11 11
+
+ Instances: 13 13 MN (4 pins)
+ 14 14 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 28 27
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 9 9
+
+ Instances: 4 4 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMP3 (5 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 4 4 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP3
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 26 layout mos transistors were reduced to 7.
+ 19 mos transistors were deleted by parallel reduction.
+ 26 source mos transistors were reduced to 7.
+ 19 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B A C_N Y VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nor3b/sky130_fd_sc_ls__nor3b_4.pex.spice b/cells/nor3b/sky130_fd_sc_ls__nor3b_4.pex.spice
index a9556b3..25a2a2d 100644
--- a/cells/nor3b/sky130_fd_sc_ls__nor3b_4.pex.spice
+++ b/cells/nor3b/sky130_fd_sc_ls__nor3b_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nor3b_4.pex.spice
-* Created: Fri Aug 28 13:39:18 2020
+* Created: Wed Sep 2 11:15:16 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nor3b/sky130_fd_sc_ls__nor3b_4.pxi.spice b/cells/nor3b/sky130_fd_sc_ls__nor3b_4.pxi.spice
index 5340f4d..34d13a4 100644
--- a/cells/nor3b/sky130_fd_sc_ls__nor3b_4.pxi.spice
+++ b/cells/nor3b/sky130_fd_sc_ls__nor3b_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nor3b_4.pxi.spice
-* Created: Fri Aug 28 13:39:18 2020
+* Created: Wed Sep 2 11:15:16 2020
*
x_PM_SKY130_FD_SC_LS__NOR3B_4%B N_B_M1004_g N_B_c_118_n N_B_M1010_g N_B_M1008_g
+ N_B_c_119_n N_B_M1014_g N_B_c_120_n N_B_M1016_g N_B_M1022_g N_B_c_121_n
diff --git a/cells/nor3b/sky130_fd_sc_ls__nor3b_4.spice b/cells/nor3b/sky130_fd_sc_ls__nor3b_4.spice
index b05fe2d..183e3e5 100644
--- a/cells/nor3b/sky130_fd_sc_ls__nor3b_4.spice
+++ b/cells/nor3b/sky130_fd_sc_ls__nor3b_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nor3b_4.spice
-* Created: Fri Aug 28 13:39:18 2020
+* Created: Wed Sep 2 11:15:16 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nor4/sky130_fd_sc_ls__nor4_1.lvs.report b/cells/nor4/sky130_fd_sc_ls__nor4_1.lvs.report
new file mode 100644
index 0000000..c095747
--- /dev/null
+++ b/cells/nor4/sky130_fd_sc_ls__nor4_1.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__nor4_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__nor4_1.sp ('sky130_fd_sc_ls__nor4_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/nor4/sky130_fd_sc_ls__nor4_1.spice ('sky130_fd_sc_ls__nor4_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:15:20 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__nor4_1 sky130_fd_sc_ls__nor4_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__nor4_1
+SOURCE CELL NAME: sky130_fd_sc_ls__nor4_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 12 12
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 9 9
+
+ Instances: 4 4 MN (4 pins)
+ 1 1 SMP4 (6 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 4 4 0 0 MN(NSHORT)
+ 1 1 0 0 SMP4
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A B C D VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nor4/sky130_fd_sc_ls__nor4_1.pex.spice b/cells/nor4/sky130_fd_sc_ls__nor4_1.pex.spice
index 2ec1bde..2fe9ff0 100644
--- a/cells/nor4/sky130_fd_sc_ls__nor4_1.pex.spice
+++ b/cells/nor4/sky130_fd_sc_ls__nor4_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nor4_1.pex.spice
-* Created: Fri Aug 28 13:39:35 2020
+* Created: Wed Sep 2 11:15:23 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nor4/sky130_fd_sc_ls__nor4_1.pxi.spice b/cells/nor4/sky130_fd_sc_ls__nor4_1.pxi.spice
index da3120a..c9fc802 100644
--- a/cells/nor4/sky130_fd_sc_ls__nor4_1.pxi.spice
+++ b/cells/nor4/sky130_fd_sc_ls__nor4_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nor4_1.pxi.spice
-* Created: Fri Aug 28 13:39:35 2020
+* Created: Wed Sep 2 11:15:23 2020
*
x_PM_SKY130_FD_SC_LS__NOR4_1%A N_A_c_48_n N_A_M1007_g N_A_M1000_g N_A_c_45_n
+ N_A_c_46_n A N_A_c_47_n PM_SKY130_FD_SC_LS__NOR4_1%A
diff --git a/cells/nor4/sky130_fd_sc_ls__nor4_1.spice b/cells/nor4/sky130_fd_sc_ls__nor4_1.spice
index fd16cc5..6945856 100644
--- a/cells/nor4/sky130_fd_sc_ls__nor4_1.spice
+++ b/cells/nor4/sky130_fd_sc_ls__nor4_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nor4_1.spice
-* Created: Fri Aug 28 13:39:35 2020
+* Created: Wed Sep 2 11:15:23 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nor4/sky130_fd_sc_ls__nor4_2.lvs.report b/cells/nor4/sky130_fd_sc_ls__nor4_2.lvs.report
new file mode 100644
index 0000000..62dbe1a
--- /dev/null
+++ b/cells/nor4/sky130_fd_sc_ls__nor4_2.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__nor4_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__nor4_2.sp ('sky130_fd_sc_ls__nor4_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/nor4/sky130_fd_sc_ls__nor4_2.spice ('sky130_fd_sc_ls__nor4_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:15:26 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__nor4_2 sky130_fd_sc_ls__nor4_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__nor4_2
+SOURCE CELL NAME: sky130_fd_sc_ls__nor4_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 12 12
+
+ Instances: 4 4 MN (4 pins)
+ 8 8 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 9 9
+
+ Instances: 4 4 MN (4 pins)
+ 1 1 SMP4 (6 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 4 4 0 0 MN(NSHORT)
+ 1 1 0 0 SMP4
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 8 layout mos transistors were reduced to 4.
+ 4 mos transistors were deleted by parallel reduction.
+ 8 source mos transistors were reduced to 4.
+ 4 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB C D B A Y VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nor4/sky130_fd_sc_ls__nor4_2.pex.spice b/cells/nor4/sky130_fd_sc_ls__nor4_2.pex.spice
index 1339868..29d816d 100644
--- a/cells/nor4/sky130_fd_sc_ls__nor4_2.pex.spice
+++ b/cells/nor4/sky130_fd_sc_ls__nor4_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nor4_2.pex.spice
-* Created: Fri Aug 28 13:39:56 2020
+* Created: Wed Sep 2 11:15:29 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nor4/sky130_fd_sc_ls__nor4_2.pxi.spice b/cells/nor4/sky130_fd_sc_ls__nor4_2.pxi.spice
index a2fbe86..80df684 100644
--- a/cells/nor4/sky130_fd_sc_ls__nor4_2.pxi.spice
+++ b/cells/nor4/sky130_fd_sc_ls__nor4_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nor4_2.pxi.spice
-* Created: Fri Aug 28 13:39:56 2020
+* Created: Wed Sep 2 11:15:29 2020
*
x_PM_SKY130_FD_SC_LS__NOR4_2%C N_C_c_78_n N_C_c_87_n N_C_M1001_g N_C_c_79_n
+ N_C_M1006_g N_C_M1004_g N_C_c_81_n N_C_c_82_n C C N_C_c_83_n C N_C_c_85_n
diff --git a/cells/nor4/sky130_fd_sc_ls__nor4_2.spice b/cells/nor4/sky130_fd_sc_ls__nor4_2.spice
index 28b49f6..ea33cc9 100644
--- a/cells/nor4/sky130_fd_sc_ls__nor4_2.spice
+++ b/cells/nor4/sky130_fd_sc_ls__nor4_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nor4_2.spice
-* Created: Fri Aug 28 13:39:56 2020
+* Created: Wed Sep 2 11:15:29 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nor4/sky130_fd_sc_ls__nor4_4.lvs.report b/cells/nor4/sky130_fd_sc_ls__nor4_4.lvs.report
new file mode 100644
index 0000000..aaaf16c
--- /dev/null
+++ b/cells/nor4/sky130_fd_sc_ls__nor4_4.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__nor4_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__nor4_4.sp ('sky130_fd_sc_ls__nor4_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/nor4/sky130_fd_sc_ls__nor4_4.spice ('sky130_fd_sc_ls__nor4_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:15:33 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__nor4_4 sky130_fd_sc_ls__nor4_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__nor4_4
+SOURCE CELL NAME: sky130_fd_sc_ls__nor4_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 12 12
+
+ Instances: 8 8 MN (4 pins)
+ 16 16 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 25 24
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 9 9
+
+ Instances: 4 4 MN (4 pins)
+ 1 1 SMP4 (6 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 4 4 0 0 MN(NSHORT)
+ 1 1 0 0 SMP4
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 24 layout mos transistors were reduced to 8.
+ 16 mos transistors were deleted by parallel reduction.
+ 24 source mos transistors were reduced to 8.
+ 16 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D C B A Y VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nor4/sky130_fd_sc_ls__nor4_4.pex.spice b/cells/nor4/sky130_fd_sc_ls__nor4_4.pex.spice
index 26950ea..8529757 100644
--- a/cells/nor4/sky130_fd_sc_ls__nor4_4.pex.spice
+++ b/cells/nor4/sky130_fd_sc_ls__nor4_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nor4_4.pex.spice
-* Created: Fri Aug 28 13:40:06 2020
+* Created: Wed Sep 2 11:15:36 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nor4/sky130_fd_sc_ls__nor4_4.pxi.spice b/cells/nor4/sky130_fd_sc_ls__nor4_4.pxi.spice
index 9d80f74..dd24eaf 100644
--- a/cells/nor4/sky130_fd_sc_ls__nor4_4.pxi.spice
+++ b/cells/nor4/sky130_fd_sc_ls__nor4_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nor4_4.pxi.spice
-* Created: Fri Aug 28 13:40:06 2020
+* Created: Wed Sep 2 11:15:36 2020
*
x_PM_SKY130_FD_SC_LS__NOR4_4%D N_D_M1002_g N_D_c_105_n N_D_M1000_g N_D_c_106_n
+ N_D_M1012_g N_D_c_107_n N_D_M1013_g N_D_M1020_g N_D_c_108_n N_D_M1018_g D D D
diff --git a/cells/nor4/sky130_fd_sc_ls__nor4_4.spice b/cells/nor4/sky130_fd_sc_ls__nor4_4.spice
index de73335..304b890 100644
--- a/cells/nor4/sky130_fd_sc_ls__nor4_4.spice
+++ b/cells/nor4/sky130_fd_sc_ls__nor4_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nor4_4.spice
-* Created: Fri Aug 28 13:40:06 2020
+* Created: Wed Sep 2 11:15:36 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nor4b/sky130_fd_sc_ls__nor4b_1.lvs.report b/cells/nor4b/sky130_fd_sc_ls__nor4b_1.lvs.report
new file mode 100644
index 0000000..3bec64b
--- /dev/null
+++ b/cells/nor4b/sky130_fd_sc_ls__nor4b_1.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__nor4b_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__nor4b_1.sp ('sky130_fd_sc_ls__nor4b_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/nor4b/sky130_fd_sc_ls__nor4b_1.spice ('sky130_fd_sc_ls__nor4b_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:15:39 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__nor4b_1 sky130_fd_sc_ls__nor4b_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__nor4b_1
+SOURCE CELL NAME: sky130_fd_sc_ls__nor4b_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 5 5 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMP4 (6 pins)
+ ------ ------
+ Total Inst: 7 7
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 5 5 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP4
+ ------- ------- --------- ---------
+ Total Inst: 7 7 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D_N A B C VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nor4b/sky130_fd_sc_ls__nor4b_1.pex.spice b/cells/nor4b/sky130_fd_sc_ls__nor4b_1.pex.spice
index f38abbf..2274363 100644
--- a/cells/nor4b/sky130_fd_sc_ls__nor4b_1.pex.spice
+++ b/cells/nor4b/sky130_fd_sc_ls__nor4b_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nor4b_1.pex.spice
-* Created: Fri Aug 28 13:40:17 2020
+* Created: Wed Sep 2 11:15:43 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nor4b/sky130_fd_sc_ls__nor4b_1.pxi.spice b/cells/nor4b/sky130_fd_sc_ls__nor4b_1.pxi.spice
index a48d65f..050a702 100644
--- a/cells/nor4b/sky130_fd_sc_ls__nor4b_1.pxi.spice
+++ b/cells/nor4b/sky130_fd_sc_ls__nor4b_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nor4b_1.pxi.spice
-* Created: Fri Aug 28 13:40:17 2020
+* Created: Wed Sep 2 11:15:43 2020
*
x_PM_SKY130_FD_SC_LS__NOR4B_1%D_N N_D_N_c_58_n N_D_N_c_63_n N_D_N_M1008_g
+ N_D_N_M1007_g D_N N_D_N_c_61_n PM_SKY130_FD_SC_LS__NOR4B_1%D_N
diff --git a/cells/nor4b/sky130_fd_sc_ls__nor4b_1.spice b/cells/nor4b/sky130_fd_sc_ls__nor4b_1.spice
index a5795f9..2b2865b 100644
--- a/cells/nor4b/sky130_fd_sc_ls__nor4b_1.spice
+++ b/cells/nor4b/sky130_fd_sc_ls__nor4b_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nor4b_1.spice
-* Created: Fri Aug 28 13:40:17 2020
+* Created: Wed Sep 2 11:15:43 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nor4b/sky130_fd_sc_ls__nor4b_2.lvs.report b/cells/nor4b/sky130_fd_sc_ls__nor4b_2.lvs.report
new file mode 100644
index 0000000..cf901cb
--- /dev/null
+++ b/cells/nor4b/sky130_fd_sc_ls__nor4b_2.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__nor4b_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__nor4b_2.sp ('sky130_fd_sc_ls__nor4b_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/nor4b/sky130_fd_sc_ls__nor4b_2.spice ('sky130_fd_sc_ls__nor4b_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:15:46 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__nor4b_2 sky130_fd_sc_ls__nor4b_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__nor4b_2
+SOURCE CELL NAME: sky130_fd_sc_ls__nor4b_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 9 9 MN (4 pins)
+ 9 9 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 19 18
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 5 5 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMP4 (6 pins)
+ ------ ------
+ Total Inst: 7 7
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 5 5 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP4
+ ------- ------- --------- ---------
+ Total Inst: 7 7 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 16 layout mos transistors were reduced to 8.
+ 8 mos transistors were deleted by parallel reduction.
+ 16 source mos transistors were reduced to 8.
+ 8 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D_N C B A VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nor4b/sky130_fd_sc_ls__nor4b_2.pex.spice b/cells/nor4b/sky130_fd_sc_ls__nor4b_2.pex.spice
index d9a1620..07a5380 100644
--- a/cells/nor4b/sky130_fd_sc_ls__nor4b_2.pex.spice
+++ b/cells/nor4b/sky130_fd_sc_ls__nor4b_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nor4b_2.pex.spice
-* Created: Fri Aug 28 13:40:26 2020
+* Created: Wed Sep 2 11:15:49 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nor4b/sky130_fd_sc_ls__nor4b_2.pxi.spice b/cells/nor4b/sky130_fd_sc_ls__nor4b_2.pxi.spice
index fdd2432..4de23af 100644
--- a/cells/nor4b/sky130_fd_sc_ls__nor4b_2.pxi.spice
+++ b/cells/nor4b/sky130_fd_sc_ls__nor4b_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nor4b_2.pxi.spice
-* Created: Fri Aug 28 13:40:26 2020
+* Created: Wed Sep 2 11:15:49 2020
*
x_PM_SKY130_FD_SC_LS__NOR4B_2%D_N N_D_N_c_95_n N_D_N_M1013_g N_D_N_M1017_g D_N
+ PM_SKY130_FD_SC_LS__NOR4B_2%D_N
diff --git a/cells/nor4b/sky130_fd_sc_ls__nor4b_2.spice b/cells/nor4b/sky130_fd_sc_ls__nor4b_2.spice
index b4c08c7..7bc57f1 100644
--- a/cells/nor4b/sky130_fd_sc_ls__nor4b_2.spice
+++ b/cells/nor4b/sky130_fd_sc_ls__nor4b_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nor4b_2.spice
-* Created: Fri Aug 28 13:40:26 2020
+* Created: Wed Sep 2 11:15:49 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nor4b/sky130_fd_sc_ls__nor4b_4.lvs.report b/cells/nor4b/sky130_fd_sc_ls__nor4b_4.lvs.report
new file mode 100644
index 0000000..28c030a
--- /dev/null
+++ b/cells/nor4b/sky130_fd_sc_ls__nor4b_4.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__nor4b_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__nor4b_4.sp ('sky130_fd_sc_ls__nor4b_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/nor4b/sky130_fd_sc_ls__nor4b_4.spice ('sky130_fd_sc_ls__nor4b_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:15:53 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__nor4b_4 sky130_fd_sc_ls__nor4b_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__nor4b_4
+SOURCE CELL NAME: sky130_fd_sc_ls__nor4b_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 17 17 MN (4 pins)
+ 18 18 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 36 35
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 5 5 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMP4 (6 pins)
+ ------ ------
+ Total Inst: 7 7
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 5 5 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP4
+ ------- ------- --------- ---------
+ Total Inst: 7 7 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 34 layout mos transistors were reduced to 9.
+ 25 mos transistors were deleted by parallel reduction.
+ 34 source mos transistors were reduced to 9.
+ 25 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D_N C B A VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nor4b/sky130_fd_sc_ls__nor4b_4.pex.spice b/cells/nor4b/sky130_fd_sc_ls__nor4b_4.pex.spice
index 3150c75..44a97d3 100644
--- a/cells/nor4b/sky130_fd_sc_ls__nor4b_4.pex.spice
+++ b/cells/nor4b/sky130_fd_sc_ls__nor4b_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nor4b_4.pex.spice
-* Created: Fri Aug 28 13:40:44 2020
+* Created: Wed Sep 2 11:15:56 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nor4b/sky130_fd_sc_ls__nor4b_4.pxi.spice b/cells/nor4b/sky130_fd_sc_ls__nor4b_4.pxi.spice
index 7ad9aa2..c5872a2 100644
--- a/cells/nor4b/sky130_fd_sc_ls__nor4b_4.pxi.spice
+++ b/cells/nor4b/sky130_fd_sc_ls__nor4b_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nor4b_4.pxi.spice
-* Created: Fri Aug 28 13:40:44 2020
+* Created: Wed Sep 2 11:15:56 2020
*
x_PM_SKY130_FD_SC_LS__NOR4B_4%D_N N_D_N_c_153_n N_D_N_M1021_g N_D_N_c_154_n
+ N_D_N_M1023_g N_D_N_c_150_n N_D_N_M1014_g D_N D_N N_D_N_c_151_n N_D_N_c_152_n
diff --git a/cells/nor4b/sky130_fd_sc_ls__nor4b_4.spice b/cells/nor4b/sky130_fd_sc_ls__nor4b_4.spice
index 6de731d..421eb87 100644
--- a/cells/nor4b/sky130_fd_sc_ls__nor4b_4.spice
+++ b/cells/nor4b/sky130_fd_sc_ls__nor4b_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nor4b_4.spice
-* Created: Fri Aug 28 13:40:44 2020
+* Created: Wed Sep 2 11:15:56 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nor4bb/sky130_fd_sc_ls__nor4bb_1.lvs.report b/cells/nor4bb/sky130_fd_sc_ls__nor4bb_1.lvs.report
new file mode 100644
index 0000000..14c23b8
--- /dev/null
+++ b/cells/nor4bb/sky130_fd_sc_ls__nor4bb_1.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__nor4bb_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__nor4bb_1.sp ('sky130_fd_sc_ls__nor4bb_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/nor4bb/sky130_fd_sc_ls__nor4bb_1.spice ('sky130_fd_sc_ls__nor4bb_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:16:00 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__nor4bb_1 sky130_fd_sc_ls__nor4bb_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__nor4bb_1
+SOURCE CELL NAME: sky130_fd_sc_ls__nor4bb_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 14 14
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 11 11
+
+ Instances: 6 6 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 1 SMP4 (6 pins)
+ ------ ------
+ Total Inst: 9 9
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 6 6 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP4
+ ------- ------- --------- ---------
+ Total Inst: 9 9 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB C_N A B D_N VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nor4bb/sky130_fd_sc_ls__nor4bb_1.pex.spice b/cells/nor4bb/sky130_fd_sc_ls__nor4bb_1.pex.spice
index 0e09558..66cc9b7 100644
--- a/cells/nor4bb/sky130_fd_sc_ls__nor4bb_1.pex.spice
+++ b/cells/nor4bb/sky130_fd_sc_ls__nor4bb_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nor4bb_1.pex.spice
-* Created: Fri Aug 28 13:41:04 2020
+* Created: Wed Sep 2 11:16:04 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nor4bb/sky130_fd_sc_ls__nor4bb_1.pxi.spice b/cells/nor4bb/sky130_fd_sc_ls__nor4bb_1.pxi.spice
index d705952..f2961de 100644
--- a/cells/nor4bb/sky130_fd_sc_ls__nor4bb_1.pxi.spice
+++ b/cells/nor4bb/sky130_fd_sc_ls__nor4bb_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nor4bb_1.pxi.spice
-* Created: Fri Aug 28 13:41:04 2020
+* Created: Wed Sep 2 11:16:04 2020
*
x_PM_SKY130_FD_SC_LS__NOR4BB_1%C_N N_C_N_c_75_n N_C_N_M1007_g N_C_N_c_72_n
+ N_C_N_M1003_g C_N N_C_N_c_74_n PM_SKY130_FD_SC_LS__NOR4BB_1%C_N
diff --git a/cells/nor4bb/sky130_fd_sc_ls__nor4bb_1.spice b/cells/nor4bb/sky130_fd_sc_ls__nor4bb_1.spice
index 00dcff9..b2283cf 100644
--- a/cells/nor4bb/sky130_fd_sc_ls__nor4bb_1.spice
+++ b/cells/nor4bb/sky130_fd_sc_ls__nor4bb_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nor4bb_1.spice
-* Created: Fri Aug 28 13:41:04 2020
+* Created: Wed Sep 2 11:16:04 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nor4bb/sky130_fd_sc_ls__nor4bb_2.lvs.report b/cells/nor4bb/sky130_fd_sc_ls__nor4bb_2.lvs.report
new file mode 100644
index 0000000..6379954
--- /dev/null
+++ b/cells/nor4bb/sky130_fd_sc_ls__nor4bb_2.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__nor4bb_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__nor4bb_2.sp ('sky130_fd_sc_ls__nor4bb_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/nor4bb/sky130_fd_sc_ls__nor4bb_2.spice ('sky130_fd_sc_ls__nor4bb_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:16:08 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__nor4bb_2 sky130_fd_sc_ls__nor4bb_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__nor4bb_2
+SOURCE CELL NAME: sky130_fd_sc_ls__nor4bb_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 14 14
+
+ Instances: 10 10 MN (4 pins)
+ 10 10 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 21 20
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 11 11
+
+ Instances: 6 6 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 1 SMP4 (6 pins)
+ ------ ------
+ Total Inst: 9 9
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 6 6 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP4
+ ------- ------- --------- ---------
+ Total Inst: 9 9 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 16 layout mos transistors were reduced to 8.
+ 8 mos transistors were deleted by parallel reduction.
+ 16 source mos transistors were reduced to 8.
+ 8 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB C_N D_N B A VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nor4bb/sky130_fd_sc_ls__nor4bb_2.pex.spice b/cells/nor4bb/sky130_fd_sc_ls__nor4bb_2.pex.spice
index bab2393..13788e0 100644
--- a/cells/nor4bb/sky130_fd_sc_ls__nor4bb_2.pex.spice
+++ b/cells/nor4bb/sky130_fd_sc_ls__nor4bb_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nor4bb_2.pex.spice
-* Created: Fri Aug 28 13:41:15 2020
+* Created: Wed Sep 2 11:16:12 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nor4bb/sky130_fd_sc_ls__nor4bb_2.pxi.spice b/cells/nor4bb/sky130_fd_sc_ls__nor4bb_2.pxi.spice
index ecffcd9..81762a8 100644
--- a/cells/nor4bb/sky130_fd_sc_ls__nor4bb_2.pxi.spice
+++ b/cells/nor4bb/sky130_fd_sc_ls__nor4bb_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nor4bb_2.pxi.spice
-* Created: Fri Aug 28 13:41:15 2020
+* Created: Wed Sep 2 11:16:12 2020
*
x_PM_SKY130_FD_SC_LS__NOR4BB_2%C_N N_C_N_c_110_n N_C_N_M1014_g N_C_N_M1016_g C_N
+ C_N N_C_N_c_109_n PM_SKY130_FD_SC_LS__NOR4BB_2%C_N
diff --git a/cells/nor4bb/sky130_fd_sc_ls__nor4bb_2.spice b/cells/nor4bb/sky130_fd_sc_ls__nor4bb_2.spice
index 10586e6..0946cfb 100644
--- a/cells/nor4bb/sky130_fd_sc_ls__nor4bb_2.spice
+++ b/cells/nor4bb/sky130_fd_sc_ls__nor4bb_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nor4bb_2.spice
-* Created: Fri Aug 28 13:41:15 2020
+* Created: Wed Sep 2 11:16:12 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nor4bb/sky130_fd_sc_ls__nor4bb_4.lvs.report b/cells/nor4bb/sky130_fd_sc_ls__nor4bb_4.lvs.report
new file mode 100644
index 0000000..6f71921
--- /dev/null
+++ b/cells/nor4bb/sky130_fd_sc_ls__nor4bb_4.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__nor4bb_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__nor4bb_4.sp ('sky130_fd_sc_ls__nor4bb_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/nor4bb/sky130_fd_sc_ls__nor4bb_4.spice ('sky130_fd_sc_ls__nor4bb_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:16:16 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__nor4bb_4 sky130_fd_sc_ls__nor4bb_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__nor4bb_4
+SOURCE CELL NAME: sky130_fd_sc_ls__nor4bb_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 14 14
+
+ Instances: 18 18 MN (4 pins)
+ 20 20 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 39 38
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 11 11
+
+ Instances: 6 6 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 1 SMP4 (6 pins)
+ ------ ------
+ Total Inst: 9 9
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 6 6 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP4
+ ------- ------- --------- ---------
+ Total Inst: 9 9 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 36 layout mos transistors were reduced to 10.
+ 26 mos transistors were deleted by parallel reduction.
+ 36 source mos transistors were reduced to 10.
+ 26 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B A C_N D_N VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nor4bb/sky130_fd_sc_ls__nor4bb_4.pex.spice b/cells/nor4bb/sky130_fd_sc_ls__nor4bb_4.pex.spice
index daa4d71..f73c0af 100644
--- a/cells/nor4bb/sky130_fd_sc_ls__nor4bb_4.pex.spice
+++ b/cells/nor4bb/sky130_fd_sc_ls__nor4bb_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nor4bb_4.pex.spice
-* Created: Fri Aug 28 13:41:25 2020
+* Created: Wed Sep 2 11:16:19 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nor4bb/sky130_fd_sc_ls__nor4bb_4.pxi.spice b/cells/nor4bb/sky130_fd_sc_ls__nor4bb_4.pxi.spice
index 17b82bf..d113c1f 100644
--- a/cells/nor4bb/sky130_fd_sc_ls__nor4bb_4.pxi.spice
+++ b/cells/nor4bb/sky130_fd_sc_ls__nor4bb_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nor4bb_4.pxi.spice
-* Created: Fri Aug 28 13:41:25 2020
+* Created: Wed Sep 2 11:16:19 2020
*
x_PM_SKY130_FD_SC_LS__NOR4BB_4%B N_B_c_185_n N_B_M1006_g N_B_M1012_g N_B_M1024_g
+ N_B_c_195_n N_B_M1014_g N_B_c_196_n N_B_M1022_g N_B_M1035_g N_B_c_197_n
diff --git a/cells/nor4bb/sky130_fd_sc_ls__nor4bb_4.spice b/cells/nor4bb/sky130_fd_sc_ls__nor4bb_4.spice
index 0320a0b..520397e 100644
--- a/cells/nor4bb/sky130_fd_sc_ls__nor4bb_4.spice
+++ b/cells/nor4bb/sky130_fd_sc_ls__nor4bb_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__nor4bb_4.spice
-* Created: Fri Aug 28 13:41:25 2020
+* Created: Wed Sep 2 11:16:19 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o2111a/sky130_fd_sc_ls__o2111a_1.lvs.report b/cells/o2111a/sky130_fd_sc_ls__o2111a_1.lvs.report
new file mode 100644
index 0000000..9c0fd88
--- /dev/null
+++ b/cells/o2111a/sky130_fd_sc_ls__o2111a_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__o2111a_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__o2111a_1.sp ('sky130_fd_sc_ls__o2111a_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/o2111a/sky130_fd_sc_ls__o2111a_1.spice ('sky130_fd_sc_ls__o2111a_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:16:23 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__o2111a_1 sky130_fd_sc_ls__o2111a_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__o2111a_1
+SOURCE CELL NAME: sky130_fd_sc_ls__o2111a_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 15 15
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 11 11
+
+ Instances: 1 1 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1_1_1 (7 pins)
+ ------ ------
+ Total Inst: 7 7
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 4 4 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1_1_1
+ ------- ------- --------- ---------
+ Total Inst: 7 7 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D1 C1 B1 A2 A1 X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o2111a/sky130_fd_sc_ls__o2111a_1.pex.spice b/cells/o2111a/sky130_fd_sc_ls__o2111a_1.pex.spice
index 6b00904..c4cba5d 100644
--- a/cells/o2111a/sky130_fd_sc_ls__o2111a_1.pex.spice
+++ b/cells/o2111a/sky130_fd_sc_ls__o2111a_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o2111a_1.pex.spice
-* Created: Fri Aug 28 13:41:35 2020
+* Created: Wed Sep 2 11:16:27 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o2111a/sky130_fd_sc_ls__o2111a_1.pxi.spice b/cells/o2111a/sky130_fd_sc_ls__o2111a_1.pxi.spice
index 53f9514..25ba671 100644
--- a/cells/o2111a/sky130_fd_sc_ls__o2111a_1.pxi.spice
+++ b/cells/o2111a/sky130_fd_sc_ls__o2111a_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o2111a_1.pxi.spice
-* Created: Fri Aug 28 13:41:35 2020
+* Created: Wed Sep 2 11:16:27 2020
*
x_PM_SKY130_FD_SC_LS__O2111A_1%A_82_48# N_A_82_48#_M1009_s N_A_82_48#_M1003_d
+ N_A_82_48#_M1008_d N_A_82_48#_c_69_n N_A_82_48#_M1004_g N_A_82_48#_c_70_n
diff --git a/cells/o2111a/sky130_fd_sc_ls__o2111a_1.spice b/cells/o2111a/sky130_fd_sc_ls__o2111a_1.spice
index a630358..b6cbb33 100644
--- a/cells/o2111a/sky130_fd_sc_ls__o2111a_1.spice
+++ b/cells/o2111a/sky130_fd_sc_ls__o2111a_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o2111a_1.spice
-* Created: Fri Aug 28 13:41:35 2020
+* Created: Wed Sep 2 11:16:27 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o2111a/sky130_fd_sc_ls__o2111a_2.lvs.report b/cells/o2111a/sky130_fd_sc_ls__o2111a_2.lvs.report
new file mode 100644
index 0000000..0e4df3b
--- /dev/null
+++ b/cells/o2111a/sky130_fd_sc_ls__o2111a_2.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__o2111a_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__o2111a_2.sp ('sky130_fd_sc_ls__o2111a_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/o2111a/sky130_fd_sc_ls__o2111a_2.spice ('sky130_fd_sc_ls__o2111a_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:16:31 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__o2111a_2 sky130_fd_sc_ls__o2111a_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__o2111a_2
+SOURCE CELL NAME: sky130_fd_sc_ls__o2111a_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 15 15
+
+ Instances: 7 7 MN (4 pins)
+ 7 7 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 15 14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 11 11
+
+ Instances: 1 1 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1_1_1 (7 pins)
+ ------ ------
+ Total Inst: 7 7
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 4 4 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1_1_1
+ ------- ------- --------- ---------
+ Total Inst: 7 7 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1 A2 B1 C1 D1 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o2111a/sky130_fd_sc_ls__o2111a_2.pex.spice b/cells/o2111a/sky130_fd_sc_ls__o2111a_2.pex.spice
index e9730ef..efc360b 100644
--- a/cells/o2111a/sky130_fd_sc_ls__o2111a_2.pex.spice
+++ b/cells/o2111a/sky130_fd_sc_ls__o2111a_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o2111a_2.pex.spice
-* Created: Fri Aug 28 13:41:52 2020
+* Created: Wed Sep 2 11:16:34 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o2111a/sky130_fd_sc_ls__o2111a_2.pxi.spice b/cells/o2111a/sky130_fd_sc_ls__o2111a_2.pxi.spice
index 29c71ec..ad92e8b 100644
--- a/cells/o2111a/sky130_fd_sc_ls__o2111a_2.pxi.spice
+++ b/cells/o2111a/sky130_fd_sc_ls__o2111a_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o2111a_2.pxi.spice
-* Created: Fri Aug 28 13:41:52 2020
+* Created: Wed Sep 2 11:16:34 2020
*
x_PM_SKY130_FD_SC_LS__O2111A_2%A1 N_A1_c_73_n N_A1_c_77_n N_A1_M1002_g
+ N_A1_M1008_g A1 A1 N_A1_c_75_n PM_SKY130_FD_SC_LS__O2111A_2%A1
diff --git a/cells/o2111a/sky130_fd_sc_ls__o2111a_2.spice b/cells/o2111a/sky130_fd_sc_ls__o2111a_2.spice
index 47576a1..f91e58a 100644
--- a/cells/o2111a/sky130_fd_sc_ls__o2111a_2.spice
+++ b/cells/o2111a/sky130_fd_sc_ls__o2111a_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o2111a_2.spice
-* Created: Fri Aug 28 13:41:52 2020
+* Created: Wed Sep 2 11:16:34 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o2111a/sky130_fd_sc_ls__o2111a_4.lvs.report b/cells/o2111a/sky130_fd_sc_ls__o2111a_4.lvs.report
new file mode 100644
index 0000000..d8fca4d
--- /dev/null
+++ b/cells/o2111a/sky130_fd_sc_ls__o2111a_4.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__o2111a_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__o2111a_4.sp ('sky130_fd_sc_ls__o2111a_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/o2111a/sky130_fd_sc_ls__o2111a_4.spice ('sky130_fd_sc_ls__o2111a_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:16:38 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__o2111a_4 sky130_fd_sc_ls__o2111a_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__o2111a_4
+SOURCE CELL NAME: sky130_fd_sc_ls__o2111a_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 15 15
+
+ Instances: 14 14 MN (4 pins)
+ 14 14 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 29 28
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 11 11
+
+ Instances: 1 1 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1_1_1 (7 pins)
+ ------ ------
+ Total Inst: 7 7
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 4 4 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1_1_1
+ ------- ------- --------- ---------
+ Total Inst: 7 7 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 28 layout mos transistors were reduced to 12.
+ 16 mos transistors were deleted by parallel reduction.
+ 28 source mos transistors were reduced to 12.
+ 16 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D1 C1 B1 A2 A1 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o2111a/sky130_fd_sc_ls__o2111a_4.pex.spice b/cells/o2111a/sky130_fd_sc_ls__o2111a_4.pex.spice
index 378064d..5dcc020 100644
--- a/cells/o2111a/sky130_fd_sc_ls__o2111a_4.pex.spice
+++ b/cells/o2111a/sky130_fd_sc_ls__o2111a_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o2111a_4.pex.spice
-* Created: Fri Aug 28 13:42:12 2020
+* Created: Wed Sep 2 11:16:42 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o2111a/sky130_fd_sc_ls__o2111a_4.pxi.spice b/cells/o2111a/sky130_fd_sc_ls__o2111a_4.pxi.spice
index 839a354..7c41f7f 100644
--- a/cells/o2111a/sky130_fd_sc_ls__o2111a_4.pxi.spice
+++ b/cells/o2111a/sky130_fd_sc_ls__o2111a_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o2111a_4.pxi.spice
-* Created: Fri Aug 28 13:42:12 2020
+* Created: Wed Sep 2 11:16:42 2020
*
x_PM_SKY130_FD_SC_LS__O2111A_4%D1 N_D1_M1017_g N_D1_c_150_n N_D1_M1021_g
+ N_D1_c_151_n N_D1_M1018_g N_D1_c_157_n N_D1_M1023_g N_D1_c_153_n D1
diff --git a/cells/o2111a/sky130_fd_sc_ls__o2111a_4.spice b/cells/o2111a/sky130_fd_sc_ls__o2111a_4.spice
index f8fb31f..1c39b23 100644
--- a/cells/o2111a/sky130_fd_sc_ls__o2111a_4.spice
+++ b/cells/o2111a/sky130_fd_sc_ls__o2111a_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o2111a_4.spice
-* Created: Fri Aug 28 13:42:12 2020
+* Created: Wed Sep 2 11:16:42 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o2111ai/sky130_fd_sc_ls__o2111ai_1.lvs.report b/cells/o2111ai/sky130_fd_sc_ls__o2111ai_1.lvs.report
new file mode 100644
index 0000000..ac1156f
--- /dev/null
+++ b/cells/o2111ai/sky130_fd_sc_ls__o2111ai_1.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__o2111ai_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__o2111ai_1.sp ('sky130_fd_sc_ls__o2111ai_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/o2111ai/sky130_fd_sc_ls__o2111ai_1.spice ('sky130_fd_sc_ls__o2111ai_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:16:46 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__o2111ai_1 sky130_fd_sc_ls__o2111ai_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__o2111ai_1
+SOURCE CELL NAME: sky130_fd_sc_ls__o2111ai_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 14 14
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 10 10
+
+ Instances: 3 3 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1_1_1 (7 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 3 3 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1_1_1
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D1 C1 B1 A2 A1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o2111ai/sky130_fd_sc_ls__o2111ai_1.pex.spice b/cells/o2111ai/sky130_fd_sc_ls__o2111ai_1.pex.spice
index 670982e..6054db3 100644
--- a/cells/o2111ai/sky130_fd_sc_ls__o2111ai_1.pex.spice
+++ b/cells/o2111ai/sky130_fd_sc_ls__o2111ai_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o2111ai_1.pex.spice
-* Created: Fri Aug 28 13:42:23 2020
+* Created: Wed Sep 2 11:16:49 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o2111ai/sky130_fd_sc_ls__o2111ai_1.pxi.spice b/cells/o2111ai/sky130_fd_sc_ls__o2111ai_1.pxi.spice
index c5b5fe2..7f70930 100644
--- a/cells/o2111ai/sky130_fd_sc_ls__o2111ai_1.pxi.spice
+++ b/cells/o2111ai/sky130_fd_sc_ls__o2111ai_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o2111ai_1.pxi.spice
-* Created: Fri Aug 28 13:42:23 2020
+* Created: Wed Sep 2 11:16:49 2020
*
x_PM_SKY130_FD_SC_LS__O2111AI_1%D1 N_D1_c_49_n N_D1_M1003_g N_D1_c_50_n
+ N_D1_M1006_g D1 PM_SKY130_FD_SC_LS__O2111AI_1%D1
diff --git a/cells/o2111ai/sky130_fd_sc_ls__o2111ai_1.spice b/cells/o2111ai/sky130_fd_sc_ls__o2111ai_1.spice
index bde7315..c75be5f 100644
--- a/cells/o2111ai/sky130_fd_sc_ls__o2111ai_1.spice
+++ b/cells/o2111ai/sky130_fd_sc_ls__o2111ai_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o2111ai_1.spice
-* Created: Fri Aug 28 13:42:23 2020
+* Created: Wed Sep 2 11:16:49 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o2111ai/sky130_fd_sc_ls__o2111ai_2.lvs.report b/cells/o2111ai/sky130_fd_sc_ls__o2111ai_2.lvs.report
new file mode 100644
index 0000000..3019de9
--- /dev/null
+++ b/cells/o2111ai/sky130_fd_sc_ls__o2111ai_2.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__o2111ai_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__o2111ai_2.sp ('sky130_fd_sc_ls__o2111ai_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/o2111ai/sky130_fd_sc_ls__o2111ai_2.spice ('sky130_fd_sc_ls__o2111ai_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:16:53 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__o2111ai_2 sky130_fd_sc_ls__o2111ai_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__o2111ai_2
+SOURCE CELL NAME: sky130_fd_sc_ls__o2111ai_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 14 14
+
+ Instances: 10 10 MN (4 pins)
+ 10 10 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 21 20
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 10 10
+
+ Instances: 3 3 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1_1_1 (7 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 3 3 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1_1_1
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 20 layout mos transistors were reduced to 10.
+ 10 mos transistors were deleted by parallel reduction.
+ 20 source mos transistors were reduced to 10.
+ 10 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D1 C1 B1 A2 A1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o2111ai/sky130_fd_sc_ls__o2111ai_2.pex.spice b/cells/o2111ai/sky130_fd_sc_ls__o2111ai_2.pex.spice
index db5aada..75a5449 100644
--- a/cells/o2111ai/sky130_fd_sc_ls__o2111ai_2.pex.spice
+++ b/cells/o2111ai/sky130_fd_sc_ls__o2111ai_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o2111ai_2.pex.spice
-* Created: Fri Aug 28 13:42:33 2020
+* Created: Wed Sep 2 11:16:56 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o2111ai/sky130_fd_sc_ls__o2111ai_2.pxi.spice b/cells/o2111ai/sky130_fd_sc_ls__o2111ai_2.pxi.spice
index 5030f05..3496254 100644
--- a/cells/o2111ai/sky130_fd_sc_ls__o2111ai_2.pxi.spice
+++ b/cells/o2111ai/sky130_fd_sc_ls__o2111ai_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o2111ai_2.pxi.spice
-* Created: Fri Aug 28 13:42:33 2020
+* Created: Wed Sep 2 11:16:56 2020
*
x_PM_SKY130_FD_SC_LS__O2111AI_2%D1 N_D1_c_105_n N_D1_M1015_g N_D1_c_100_n
+ N_D1_M1013_g N_D1_c_101_n N_D1_M1014_g N_D1_c_106_n N_D1_M1016_g N_D1_c_102_n
diff --git a/cells/o2111ai/sky130_fd_sc_ls__o2111ai_2.spice b/cells/o2111ai/sky130_fd_sc_ls__o2111ai_2.spice
index f15a810..f4eac43 100644
--- a/cells/o2111ai/sky130_fd_sc_ls__o2111ai_2.spice
+++ b/cells/o2111ai/sky130_fd_sc_ls__o2111ai_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o2111ai_2.spice
-* Created: Fri Aug 28 13:42:33 2020
+* Created: Wed Sep 2 11:16:56 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o2111ai/sky130_fd_sc_ls__o2111ai_4.lvs.report b/cells/o2111ai/sky130_fd_sc_ls__o2111ai_4.lvs.report
new file mode 100644
index 0000000..139268f
--- /dev/null
+++ b/cells/o2111ai/sky130_fd_sc_ls__o2111ai_4.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__o2111ai_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__o2111ai_4.sp ('sky130_fd_sc_ls__o2111ai_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/o2111ai/sky130_fd_sc_ls__o2111ai_4.spice ('sky130_fd_sc_ls__o2111ai_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:17:00 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__o2111ai_4 sky130_fd_sc_ls__o2111ai_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__o2111ai_4
+SOURCE CELL NAME: sky130_fd_sc_ls__o2111ai_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 14 14
+
+ Instances: 20 20 MN (4 pins)
+ 14 14 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 35 34
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 10 10
+
+ Instances: 3 3 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1_1_1 (7 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 3 3 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1_1_1
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 34 layout mos transistors were reduced to 10.
+ 24 mos transistors were deleted by parallel reduction.
+ 34 source mos transistors were reduced to 10.
+ 24 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D1 C1 B1 A1 A2 Y VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o2111ai/sky130_fd_sc_ls__o2111ai_4.pex.spice b/cells/o2111ai/sky130_fd_sc_ls__o2111ai_4.pex.spice
index 341d7d3..df5f7e1 100644
--- a/cells/o2111ai/sky130_fd_sc_ls__o2111ai_4.pex.spice
+++ b/cells/o2111ai/sky130_fd_sc_ls__o2111ai_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o2111ai_4.pex.spice
-* Created: Fri Aug 28 13:42:43 2020
+* Created: Wed Sep 2 11:17:04 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o2111ai/sky130_fd_sc_ls__o2111ai_4.pxi.spice b/cells/o2111ai/sky130_fd_sc_ls__o2111ai_4.pxi.spice
index 1449567..4fa66bc 100644
--- a/cells/o2111ai/sky130_fd_sc_ls__o2111ai_4.pxi.spice
+++ b/cells/o2111ai/sky130_fd_sc_ls__o2111ai_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o2111ai_4.pxi.spice
-* Created: Fri Aug 28 13:42:43 2020
+* Created: Wed Sep 2 11:17:04 2020
*
x_PM_SKY130_FD_SC_LS__O2111AI_4%D1 N_D1_c_140_n N_D1_M1008_g N_D1_c_141_n
+ N_D1_M1010_g N_D1_c_146_n N_D1_M1028_g N_D1_c_142_n N_D1_M1024_g N_D1_c_147_n
diff --git a/cells/o2111ai/sky130_fd_sc_ls__o2111ai_4.spice b/cells/o2111ai/sky130_fd_sc_ls__o2111ai_4.spice
index 966b890..a99181b 100644
--- a/cells/o2111ai/sky130_fd_sc_ls__o2111ai_4.spice
+++ b/cells/o2111ai/sky130_fd_sc_ls__o2111ai_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o2111ai_4.spice
-* Created: Fri Aug 28 13:42:43 2020
+* Created: Wed Sep 2 11:17:04 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o211a/sky130_fd_sc_ls__o211a_1.lvs.report b/cells/o211a/sky130_fd_sc_ls__o211a_1.lvs.report
new file mode 100644
index 0000000..7e2281b
--- /dev/null
+++ b/cells/o211a/sky130_fd_sc_ls__o211a_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__o211a_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__o211a_1.sp ('sky130_fd_sc_ls__o211a_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/o211a/sky130_fd_sc_ls__o211a_1.spice ('sky130_fd_sc_ls__o211a_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:17:08 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__o211a_1 sky130_fd_sc_ls__o211a_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__o211a_1
+SOURCE CELL NAME: sky130_fd_sc_ls__o211a_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 1 1 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1_1 (6 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 3 3 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1_1
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1 A2 B1 C1 X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o211a/sky130_fd_sc_ls__o211a_1.pex.spice b/cells/o211a/sky130_fd_sc_ls__o211a_1.pex.spice
index 2c71ff4..6c5c9a8 100644
--- a/cells/o211a/sky130_fd_sc_ls__o211a_1.pex.spice
+++ b/cells/o211a/sky130_fd_sc_ls__o211a_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o211a_1.pex.spice
-* Created: Fri Aug 28 13:43:01 2020
+* Created: Wed Sep 2 11:17:12 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o211a/sky130_fd_sc_ls__o211a_1.pxi.spice b/cells/o211a/sky130_fd_sc_ls__o211a_1.pxi.spice
index 5e305f4..c4c482a 100644
--- a/cells/o211a/sky130_fd_sc_ls__o211a_1.pxi.spice
+++ b/cells/o211a/sky130_fd_sc_ls__o211a_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o211a_1.pxi.spice
-* Created: Fri Aug 28 13:43:01 2020
+* Created: Wed Sep 2 11:17:12 2020
*
x_PM_SKY130_FD_SC_LS__O211A_1%A_83_264# N_A_83_264#_M1002_d N_A_83_264#_M1007_d
+ N_A_83_264#_M1009_d N_A_83_264#_M1008_g N_A_83_264#_c_70_n N_A_83_264#_M1005_g
diff --git a/cells/o211a/sky130_fd_sc_ls__o211a_1.spice b/cells/o211a/sky130_fd_sc_ls__o211a_1.spice
index 66795dc..f764450 100644
--- a/cells/o211a/sky130_fd_sc_ls__o211a_1.spice
+++ b/cells/o211a/sky130_fd_sc_ls__o211a_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o211a_1.spice
-* Created: Fri Aug 28 13:43:01 2020
+* Created: Wed Sep 2 11:17:12 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o211a/sky130_fd_sc_ls__o211a_2.lvs.report b/cells/o211a/sky130_fd_sc_ls__o211a_2.lvs.report
new file mode 100644
index 0000000..8bf81de
--- /dev/null
+++ b/cells/o211a/sky130_fd_sc_ls__o211a_2.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__o211a_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__o211a_2.sp ('sky130_fd_sc_ls__o211a_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/o211a/sky130_fd_sc_ls__o211a_2.spice ('sky130_fd_sc_ls__o211a_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:17:16 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__o211a_2 sky130_fd_sc_ls__o211a_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__o211a_2
+SOURCE CELL NAME: sky130_fd_sc_ls__o211a_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 1 1 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1_1 (6 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 3 3 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1_1
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB C1 B1 A2 A1 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o211a/sky130_fd_sc_ls__o211a_2.pex.spice b/cells/o211a/sky130_fd_sc_ls__o211a_2.pex.spice
index 9a3d9a8..5428bce 100644
--- a/cells/o211a/sky130_fd_sc_ls__o211a_2.pex.spice
+++ b/cells/o211a/sky130_fd_sc_ls__o211a_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o211a_2.pex.spice
-* Created: Fri Aug 28 13:43:21 2020
+* Created: Wed Sep 2 11:17:19 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o211a/sky130_fd_sc_ls__o211a_2.pxi.spice b/cells/o211a/sky130_fd_sc_ls__o211a_2.pxi.spice
index 6a13fe9..8a658d0 100644
--- a/cells/o211a/sky130_fd_sc_ls__o211a_2.pxi.spice
+++ b/cells/o211a/sky130_fd_sc_ls__o211a_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o211a_2.pxi.spice
-* Created: Fri Aug 28 13:43:21 2020
+* Created: Wed Sep 2 11:17:19 2020
*
x_PM_SKY130_FD_SC_LS__O211A_2%C1 N_C1_c_63_n N_C1_M1004_g N_C1_c_64_n
+ N_C1_M1009_g C1 PM_SKY130_FD_SC_LS__O211A_2%C1
diff --git a/cells/o211a/sky130_fd_sc_ls__o211a_2.spice b/cells/o211a/sky130_fd_sc_ls__o211a_2.spice
index 8ce7926..04c4da5 100644
--- a/cells/o211a/sky130_fd_sc_ls__o211a_2.spice
+++ b/cells/o211a/sky130_fd_sc_ls__o211a_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o211a_2.spice
-* Created: Fri Aug 28 13:43:21 2020
+* Created: Wed Sep 2 11:17:19 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o211a/sky130_fd_sc_ls__o211a_4.lvs.report b/cells/o211a/sky130_fd_sc_ls__o211a_4.lvs.report
new file mode 100644
index 0000000..cc11817
--- /dev/null
+++ b/cells/o211a/sky130_fd_sc_ls__o211a_4.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__o211a_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__o211a_4.sp ('sky130_fd_sc_ls__o211a_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/o211a/sky130_fd_sc_ls__o211a_4.spice ('sky130_fd_sc_ls__o211a_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:17:22 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__o211a_4 sky130_fd_sc_ls__o211a_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__o211a_4
+SOURCE CELL NAME: sky130_fd_sc_ls__o211a_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 12 12 MN (4 pins)
+ 12 12 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 25 24
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 1 1 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1_1 (6 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 3 3 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1_1
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 24 layout mos transistors were reduced to 10.
+ 14 mos transistors were deleted by parallel reduction.
+ 24 source mos transistors were reduced to 10.
+ 14 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB C1 B1 A2 A1 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o211a/sky130_fd_sc_ls__o211a_4.pex.spice b/cells/o211a/sky130_fd_sc_ls__o211a_4.pex.spice
index 0007419..895089e 100644
--- a/cells/o211a/sky130_fd_sc_ls__o211a_4.pex.spice
+++ b/cells/o211a/sky130_fd_sc_ls__o211a_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o211a_4.pex.spice
-* Created: Fri Aug 28 13:43:32 2020
+* Created: Wed Sep 2 11:17:26 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o211a/sky130_fd_sc_ls__o211a_4.pxi.spice b/cells/o211a/sky130_fd_sc_ls__o211a_4.pxi.spice
index f9cf099..d5aa476 100644
--- a/cells/o211a/sky130_fd_sc_ls__o211a_4.pxi.spice
+++ b/cells/o211a/sky130_fd_sc_ls__o211a_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o211a_4.pxi.spice
-* Created: Fri Aug 28 13:43:32 2020
+* Created: Wed Sep 2 11:17:26 2020
*
x_PM_SKY130_FD_SC_LS__O211A_4%A_91_48# N_A_91_48#_M1013_s N_A_91_48#_M1003_d
+ N_A_91_48#_M1009_d N_A_91_48#_M1001_d N_A_91_48#_M1007_g N_A_91_48#_c_140_n
diff --git a/cells/o211a/sky130_fd_sc_ls__o211a_4.spice b/cells/o211a/sky130_fd_sc_ls__o211a_4.spice
index 03fe107..b707e8d 100644
--- a/cells/o211a/sky130_fd_sc_ls__o211a_4.spice
+++ b/cells/o211a/sky130_fd_sc_ls__o211a_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o211a_4.spice
-* Created: Fri Aug 28 13:43:32 2020
+* Created: Wed Sep 2 11:17:26 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o211ai/sky130_fd_sc_ls__o211ai_1.lvs.report b/cells/o211ai/sky130_fd_sc_ls__o211ai_1.lvs.report
new file mode 100644
index 0000000..721f36d
--- /dev/null
+++ b/cells/o211ai/sky130_fd_sc_ls__o211ai_1.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__o211ai_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__o211ai_1.sp ('sky130_fd_sc_ls__o211ai_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/o211ai/sky130_fd_sc_ls__o211ai_1.spice ('sky130_fd_sc_ls__o211ai_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:17:29 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__o211ai_1 sky130_fd_sc_ls__o211ai_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__o211ai_1
+SOURCE CELL NAME: sky130_fd_sc_ls__o211ai_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 12 12
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 9 9
+
+ Instances: 2 2 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1_1 (6 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1_1
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1 A2 B1 C1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o211ai/sky130_fd_sc_ls__o211ai_1.pex.spice b/cells/o211ai/sky130_fd_sc_ls__o211ai_1.pex.spice
index cb0b0bb..386784d 100644
--- a/cells/o211ai/sky130_fd_sc_ls__o211ai_1.pex.spice
+++ b/cells/o211ai/sky130_fd_sc_ls__o211ai_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o211ai_1.pex.spice
-* Created: Fri Aug 28 13:43:42 2020
+* Created: Wed Sep 2 11:17:32 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o211ai/sky130_fd_sc_ls__o211ai_1.pxi.spice b/cells/o211ai/sky130_fd_sc_ls__o211ai_1.pxi.spice
index 1493e66..f8ad8d9 100644
--- a/cells/o211ai/sky130_fd_sc_ls__o211ai_1.pxi.spice
+++ b/cells/o211ai/sky130_fd_sc_ls__o211ai_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o211ai_1.pxi.spice
-* Created: Fri Aug 28 13:43:42 2020
+* Created: Wed Sep 2 11:17:32 2020
*
x_PM_SKY130_FD_SC_LS__O211AI_1%A1 N_A1_c_46_n N_A1_M1005_g N_A1_M1006_g A1
+ N_A1_c_48_n PM_SKY130_FD_SC_LS__O211AI_1%A1
diff --git a/cells/o211ai/sky130_fd_sc_ls__o211ai_1.spice b/cells/o211ai/sky130_fd_sc_ls__o211ai_1.spice
index c830b95..17d5767 100644
--- a/cells/o211ai/sky130_fd_sc_ls__o211ai_1.spice
+++ b/cells/o211ai/sky130_fd_sc_ls__o211ai_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o211ai_1.spice
-* Created: Fri Aug 28 13:43:42 2020
+* Created: Wed Sep 2 11:17:32 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o211ai/sky130_fd_sc_ls__o211ai_2.lvs.report b/cells/o211ai/sky130_fd_sc_ls__o211ai_2.lvs.report
new file mode 100644
index 0000000..785eb4f
--- /dev/null
+++ b/cells/o211ai/sky130_fd_sc_ls__o211ai_2.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__o211ai_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__o211ai_2.sp ('sky130_fd_sc_ls__o211ai_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/o211ai/sky130_fd_sc_ls__o211ai_2.spice ('sky130_fd_sc_ls__o211ai_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:17:36 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__o211ai_2 sky130_fd_sc_ls__o211ai_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__o211ai_2
+SOURCE CELL NAME: sky130_fd_sc_ls__o211ai_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 12 12
+
+ Instances: 8 8 MN (4 pins)
+ 8 8 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 17 16
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 9 9
+
+ Instances: 2 2 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1_1 (6 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1_1
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 16 layout mos transistors were reduced to 8.
+ 8 mos transistors were deleted by parallel reduction.
+ 16 source mos transistors were reduced to 8.
+ 8 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB C1 B1 A2 A1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o211ai/sky130_fd_sc_ls__o211ai_2.pex.spice b/cells/o211ai/sky130_fd_sc_ls__o211ai_2.pex.spice
index 328c4d8..de1eaba 100644
--- a/cells/o211ai/sky130_fd_sc_ls__o211ai_2.pex.spice
+++ b/cells/o211ai/sky130_fd_sc_ls__o211ai_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o211ai_2.pex.spice
-* Created: Fri Aug 28 13:43:52 2020
+* Created: Wed Sep 2 11:17:39 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o211ai/sky130_fd_sc_ls__o211ai_2.pxi.spice b/cells/o211ai/sky130_fd_sc_ls__o211ai_2.pxi.spice
index 09d751c..d6dafb2 100644
--- a/cells/o211ai/sky130_fd_sc_ls__o211ai_2.pxi.spice
+++ b/cells/o211ai/sky130_fd_sc_ls__o211ai_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o211ai_2.pxi.spice
-* Created: Fri Aug 28 13:43:52 2020
+* Created: Wed Sep 2 11:17:39 2020
*
x_PM_SKY130_FD_SC_LS__O211AI_2%C1 N_C1_M1002_g N_C1_c_88_n N_C1_M1014_g
+ N_C1_M1003_g N_C1_c_89_n N_C1_M1015_g C1 N_C1_c_86_n N_C1_c_87_n
diff --git a/cells/o211ai/sky130_fd_sc_ls__o211ai_2.spice b/cells/o211ai/sky130_fd_sc_ls__o211ai_2.spice
index 7f9f16c..766c165 100644
--- a/cells/o211ai/sky130_fd_sc_ls__o211ai_2.spice
+++ b/cells/o211ai/sky130_fd_sc_ls__o211ai_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o211ai_2.spice
-* Created: Fri Aug 28 13:43:52 2020
+* Created: Wed Sep 2 11:17:39 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o211ai/sky130_fd_sc_ls__o211ai_4.lvs.report b/cells/o211ai/sky130_fd_sc_ls__o211ai_4.lvs.report
new file mode 100644
index 0000000..5557f07
--- /dev/null
+++ b/cells/o211ai/sky130_fd_sc_ls__o211ai_4.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__o211ai_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__o211ai_4.sp ('sky130_fd_sc_ls__o211ai_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/o211ai/sky130_fd_sc_ls__o211ai_4.spice ('sky130_fd_sc_ls__o211ai_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:17:43 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__o211ai_4 sky130_fd_sc_ls__o211ai_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__o211ai_4
+SOURCE CELL NAME: sky130_fd_sc_ls__o211ai_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 12 12
+
+ Instances: 16 16 MN (4 pins)
+ 12 12 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 29 28
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 9 9
+
+ Instances: 2 2 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1_1 (6 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1_1
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 28 layout mos transistors were reduced to 8.
+ 20 mos transistors were deleted by parallel reduction.
+ 28 source mos transistors were reduced to 8.
+ 20 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1 A2 B1 C1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o211ai/sky130_fd_sc_ls__o211ai_4.pex.spice b/cells/o211ai/sky130_fd_sc_ls__o211ai_4.pex.spice
index 237bc97..44f2d07 100644
--- a/cells/o211ai/sky130_fd_sc_ls__o211ai_4.pex.spice
+++ b/cells/o211ai/sky130_fd_sc_ls__o211ai_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o211ai_4.pex.spice
-* Created: Fri Aug 28 13:44:09 2020
+* Created: Wed Sep 2 11:17:46 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o211ai/sky130_fd_sc_ls__o211ai_4.pxi.spice b/cells/o211ai/sky130_fd_sc_ls__o211ai_4.pxi.spice
index 05d5e91..127b735 100644
--- a/cells/o211ai/sky130_fd_sc_ls__o211ai_4.pxi.spice
+++ b/cells/o211ai/sky130_fd_sc_ls__o211ai_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o211ai_4.pxi.spice
-* Created: Fri Aug 28 13:44:09 2020
+* Created: Wed Sep 2 11:17:46 2020
*
x_PM_SKY130_FD_SC_LS__O211AI_4%A1 N_A1_M1010_g N_A1_c_133_n N_A1_M1007_g
+ N_A1_c_134_n N_A1_M1009_g N_A1_M1017_g N_A1_c_135_n N_A1_M1013_g N_A1_M1022_g
diff --git a/cells/o211ai/sky130_fd_sc_ls__o211ai_4.spice b/cells/o211ai/sky130_fd_sc_ls__o211ai_4.spice
index 174c324..0bd3c80 100644
--- a/cells/o211ai/sky130_fd_sc_ls__o211ai_4.spice
+++ b/cells/o211ai/sky130_fd_sc_ls__o211ai_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o211ai_4.spice
-* Created: Fri Aug 28 13:44:09 2020
+* Created: Wed Sep 2 11:17:46 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o21a/sky130_fd_sc_ls__o21a_1.lvs.report b/cells/o21a/sky130_fd_sc_ls__o21a_1.lvs.report
new file mode 100644
index 0000000..d454562
--- /dev/null
+++ b/cells/o21a/sky130_fd_sc_ls__o21a_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__o21a_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__o21a_1.sp ('sky130_fd_sc_ls__o21a_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/o21a/sky130_fd_sc_ls__o21a_1.spice ('sky130_fd_sc_ls__o21a_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:17:49 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__o21a_1 sky130_fd_sc_ls__o21a_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__o21a_1
+SOURCE CELL NAME: sky130_fd_sc_ls__o21a_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 11 11
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 9 9
+
+ Instances: 1 1 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1 (5 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1 A2 A1 X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o21a/sky130_fd_sc_ls__o21a_1.pex.spice b/cells/o21a/sky130_fd_sc_ls__o21a_1.pex.spice
index 77ee27c..198640d 100644
--- a/cells/o21a/sky130_fd_sc_ls__o21a_1.pex.spice
+++ b/cells/o21a/sky130_fd_sc_ls__o21a_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o21a_1.pex.spice
-* Created: Fri Aug 28 13:44:30 2020
+* Created: Wed Sep 2 11:17:52 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o21a/sky130_fd_sc_ls__o21a_1.pxi.spice b/cells/o21a/sky130_fd_sc_ls__o21a_1.pxi.spice
index bfa64af..f66ced4 100644
--- a/cells/o21a/sky130_fd_sc_ls__o21a_1.pxi.spice
+++ b/cells/o21a/sky130_fd_sc_ls__o21a_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o21a_1.pxi.spice
-* Created: Fri Aug 28 13:44:30 2020
+* Created: Wed Sep 2 11:17:52 2020
*
x_PM_SKY130_FD_SC_LS__O21A_1%A_83_244# N_A_83_244#_M1002_s N_A_83_244#_M1003_d
+ N_A_83_244#_c_50_n N_A_83_244#_M1006_g N_A_83_244#_c_51_n N_A_83_244#_M1005_g
diff --git a/cells/o21a/sky130_fd_sc_ls__o21a_1.spice b/cells/o21a/sky130_fd_sc_ls__o21a_1.spice
index b72ad2d..58f21b7 100644
--- a/cells/o21a/sky130_fd_sc_ls__o21a_1.spice
+++ b/cells/o21a/sky130_fd_sc_ls__o21a_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o21a_1.spice
-* Created: Fri Aug 28 13:44:30 2020
+* Created: Wed Sep 2 11:17:52 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o21a/sky130_fd_sc_ls__o21a_2.lvs.report b/cells/o21a/sky130_fd_sc_ls__o21a_2.lvs.report
new file mode 100644
index 0000000..199ab71
--- /dev/null
+++ b/cells/o21a/sky130_fd_sc_ls__o21a_2.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__o21a_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__o21a_2.sp ('sky130_fd_sc_ls__o21a_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/o21a/sky130_fd_sc_ls__o21a_2.spice ('sky130_fd_sc_ls__o21a_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:17:56 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__o21a_2 sky130_fd_sc_ls__o21a_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__o21a_2
+SOURCE CELL NAME: sky130_fd_sc_ls__o21a_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 11 11
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 9 9
+
+ Instances: 1 1 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1 (5 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1 A2 B1 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o21a/sky130_fd_sc_ls__o21a_2.pex.spice b/cells/o21a/sky130_fd_sc_ls__o21a_2.pex.spice
index 63aaecf..8fb754b 100644
--- a/cells/o21a/sky130_fd_sc_ls__o21a_2.pex.spice
+++ b/cells/o21a/sky130_fd_sc_ls__o21a_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o21a_2.pex.spice
-* Created: Fri Aug 28 13:44:41 2020
+* Created: Wed Sep 2 11:17:59 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o21a/sky130_fd_sc_ls__o21a_2.pxi.spice b/cells/o21a/sky130_fd_sc_ls__o21a_2.pxi.spice
index 8cf0f38..6d6ee18 100644
--- a/cells/o21a/sky130_fd_sc_ls__o21a_2.pxi.spice
+++ b/cells/o21a/sky130_fd_sc_ls__o21a_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o21a_2.pxi.spice
-* Created: Fri Aug 28 13:44:41 2020
+* Created: Wed Sep 2 11:17:59 2020
*
x_PM_SKY130_FD_SC_LS__O21A_2%A1 N_A1_c_59_n N_A1_M1006_g N_A1_c_60_n
+ N_A1_M1001_g N_A1_c_61_n A1 A1 PM_SKY130_FD_SC_LS__O21A_2%A1
diff --git a/cells/o21a/sky130_fd_sc_ls__o21a_2.spice b/cells/o21a/sky130_fd_sc_ls__o21a_2.spice
index 33a4ae7..d00d6bd 100644
--- a/cells/o21a/sky130_fd_sc_ls__o21a_2.spice
+++ b/cells/o21a/sky130_fd_sc_ls__o21a_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o21a_2.spice
-* Created: Fri Aug 28 13:44:41 2020
+* Created: Wed Sep 2 11:17:59 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o21a/sky130_fd_sc_ls__o21a_4.lvs.report b/cells/o21a/sky130_fd_sc_ls__o21a_4.lvs.report
new file mode 100644
index 0000000..7062cf0
--- /dev/null
+++ b/cells/o21a/sky130_fd_sc_ls__o21a_4.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__o21a_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__o21a_4.sp ('sky130_fd_sc_ls__o21a_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/o21a/sky130_fd_sc_ls__o21a_4.spice ('sky130_fd_sc_ls__o21a_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:18:02 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__o21a_4 sky130_fd_sc_ls__o21a_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__o21a_4
+SOURCE CELL NAME: sky130_fd_sc_ls__o21a_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 11 11
+
+ Instances: 10 10 MN (4 pins)
+ 10 10 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 21 20
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 9 9
+
+ Instances: 1 1 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1 (5 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 20 layout mos transistors were reduced to 8.
+ 12 mos transistors were deleted by parallel reduction.
+ 20 source mos transistors were reduced to 8.
+ 12 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A2 A1 B1 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o21a/sky130_fd_sc_ls__o21a_4.pex.spice b/cells/o21a/sky130_fd_sc_ls__o21a_4.pex.spice
index 5a8901e..e6ec05b 100644
--- a/cells/o21a/sky130_fd_sc_ls__o21a_4.pex.spice
+++ b/cells/o21a/sky130_fd_sc_ls__o21a_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o21a_4.pex.spice
-* Created: Fri Aug 28 13:44:51 2020
+* Created: Wed Sep 2 11:18:06 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o21a/sky130_fd_sc_ls__o21a_4.pxi.spice b/cells/o21a/sky130_fd_sc_ls__o21a_4.pxi.spice
index 6131cbd..2f874aa 100644
--- a/cells/o21a/sky130_fd_sc_ls__o21a_4.pxi.spice
+++ b/cells/o21a/sky130_fd_sc_ls__o21a_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o21a_4.pxi.spice
-* Created: Fri Aug 28 13:44:51 2020
+* Created: Wed Sep 2 11:18:06 2020
*
x_PM_SKY130_FD_SC_LS__O21A_4%A2 N_A2_M1003_g N_A2_c_104_n N_A2_M1000_g
+ N_A2_M1004_g N_A2_c_105_n N_A2_M1015_g A2 N_A2_c_102_n N_A2_c_103_n
diff --git a/cells/o21a/sky130_fd_sc_ls__o21a_4.spice b/cells/o21a/sky130_fd_sc_ls__o21a_4.spice
index 59ffec5..4549578 100644
--- a/cells/o21a/sky130_fd_sc_ls__o21a_4.spice
+++ b/cells/o21a/sky130_fd_sc_ls__o21a_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o21a_4.spice
-* Created: Fri Aug 28 13:44:51 2020
+* Created: Wed Sep 2 11:18:06 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o21ai/sky130_fd_sc_ls__o21ai_1.lvs.report b/cells/o21ai/sky130_fd_sc_ls__o21ai_1.lvs.report
new file mode 100644
index 0000000..71a5386
--- /dev/null
+++ b/cells/o21ai/sky130_fd_sc_ls__o21ai_1.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__o21ai_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__o21ai_1.sp ('sky130_fd_sc_ls__o21ai_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/o21ai/sky130_fd_sc_ls__o21ai_1.spice ('sky130_fd_sc_ls__o21ai_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:18:09 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__o21ai_1 sky130_fd_sc_ls__o21ai_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__o21ai_1
+SOURCE CELL NAME: sky130_fd_sc_ls__o21ai_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 10 10
+
+ Instances: 3 3 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 7 6
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 8 8
+
+ Instances: 1 1 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1 (5 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1 A2 B1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o21ai/sky130_fd_sc_ls__o21ai_1.pex.spice b/cells/o21ai/sky130_fd_sc_ls__o21ai_1.pex.spice
index c087310..837c551 100644
--- a/cells/o21ai/sky130_fd_sc_ls__o21ai_1.pex.spice
+++ b/cells/o21ai/sky130_fd_sc_ls__o21ai_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o21ai_1.pex.spice
-* Created: Fri Aug 28 13:45:01 2020
+* Created: Wed Sep 2 11:18:12 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o21ai/sky130_fd_sc_ls__o21ai_1.pxi.spice b/cells/o21ai/sky130_fd_sc_ls__o21ai_1.pxi.spice
index 07ea121..10845eb 100644
--- a/cells/o21ai/sky130_fd_sc_ls__o21ai_1.pxi.spice
+++ b/cells/o21ai/sky130_fd_sc_ls__o21ai_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o21ai_1.pxi.spice
-* Created: Fri Aug 28 13:45:01 2020
+* Created: Wed Sep 2 11:18:12 2020
*
x_PM_SKY130_FD_SC_LS__O21AI_1%A1 N_A1_c_36_n N_A1_M1003_g N_A1_c_37_n
+ N_A1_M1000_g A1 N_A1_c_38_n PM_SKY130_FD_SC_LS__O21AI_1%A1
diff --git a/cells/o21ai/sky130_fd_sc_ls__o21ai_1.spice b/cells/o21ai/sky130_fd_sc_ls__o21ai_1.spice
index d66c947..a9bcebd 100644
--- a/cells/o21ai/sky130_fd_sc_ls__o21ai_1.spice
+++ b/cells/o21ai/sky130_fd_sc_ls__o21ai_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o21ai_1.spice
-* Created: Fri Aug 28 13:45:01 2020
+* Created: Wed Sep 2 11:18:12 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o21ai/sky130_fd_sc_ls__o21ai_2.lvs.report b/cells/o21ai/sky130_fd_sc_ls__o21ai_2.lvs.report
new file mode 100644
index 0000000..5b6d035
--- /dev/null
+++ b/cells/o21ai/sky130_fd_sc_ls__o21ai_2.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__o21ai_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__o21ai_2.sp ('sky130_fd_sc_ls__o21ai_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/o21ai/sky130_fd_sc_ls__o21ai_2.spice ('sky130_fd_sc_ls__o21ai_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:18:16 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__o21ai_2 sky130_fd_sc_ls__o21ai_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__o21ai_2
+SOURCE CELL NAME: sky130_fd_sc_ls__o21ai_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 10 10
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 8 8
+
+ Instances: 1 1 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1 (5 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 12 layout mos transistors were reduced to 6.
+ 6 mos transistors were deleted by parallel reduction.
+ 12 source mos transistors were reduced to 6.
+ 6 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1 A2 B1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o21ai/sky130_fd_sc_ls__o21ai_2.pex.spice b/cells/o21ai/sky130_fd_sc_ls__o21ai_2.pex.spice
index a8a4aee..7b63a3a 100644
--- a/cells/o21ai/sky130_fd_sc_ls__o21ai_2.pex.spice
+++ b/cells/o21ai/sky130_fd_sc_ls__o21ai_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o21ai_2.pex.spice
-* Created: Fri Aug 28 13:45:18 2020
+* Created: Wed Sep 2 11:18:19 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o21ai/sky130_fd_sc_ls__o21ai_2.pxi.spice b/cells/o21ai/sky130_fd_sc_ls__o21ai_2.pxi.spice
index 9df263b..d013750 100644
--- a/cells/o21ai/sky130_fd_sc_ls__o21ai_2.pxi.spice
+++ b/cells/o21ai/sky130_fd_sc_ls__o21ai_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o21ai_2.pxi.spice
-* Created: Fri Aug 28 13:45:18 2020
+* Created: Wed Sep 2 11:18:19 2020
*
x_PM_SKY130_FD_SC_LS__O21AI_2%A1 N_A1_M1008_g N_A1_c_63_n N_A1_M1000_g
+ N_A1_M1010_g N_A1_c_65_n N_A1_M1006_g N_A1_c_66_n N_A1_c_74_p N_A1_c_96_p A1
diff --git a/cells/o21ai/sky130_fd_sc_ls__o21ai_2.spice b/cells/o21ai/sky130_fd_sc_ls__o21ai_2.spice
index 17b2618..fb39232 100644
--- a/cells/o21ai/sky130_fd_sc_ls__o21ai_2.spice
+++ b/cells/o21ai/sky130_fd_sc_ls__o21ai_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o21ai_2.spice
-* Created: Fri Aug 28 13:45:18 2020
+* Created: Wed Sep 2 11:18:19 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o21ai/sky130_fd_sc_ls__o21ai_4.lvs.report b/cells/o21ai/sky130_fd_sc_ls__o21ai_4.lvs.report
new file mode 100644
index 0000000..9652490
--- /dev/null
+++ b/cells/o21ai/sky130_fd_sc_ls__o21ai_4.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__o21ai_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__o21ai_4.sp ('sky130_fd_sc_ls__o21ai_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/o21ai/sky130_fd_sc_ls__o21ai_4.spice ('sky130_fd_sc_ls__o21ai_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:18:22 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__o21ai_4 sky130_fd_sc_ls__o21ai_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__o21ai_4
+SOURCE CELL NAME: sky130_fd_sc_ls__o21ai_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 10 10
+
+ Instances: 12 12 MN (4 pins)
+ 10 10 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 23 22
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 8 8
+
+ Instances: 1 1 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1 (5 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 22 layout mos transistors were reduced to 6.
+ 16 mos transistors were deleted by parallel reduction.
+ 22 source mos transistors were reduced to 6.
+ 16 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1 B1 A2 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o21ai/sky130_fd_sc_ls__o21ai_4.pex.spice b/cells/o21ai/sky130_fd_sc_ls__o21ai_4.pex.spice
index cb21fbf..ad45844 100644
--- a/cells/o21ai/sky130_fd_sc_ls__o21ai_4.pex.spice
+++ b/cells/o21ai/sky130_fd_sc_ls__o21ai_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o21ai_4.pex.spice
-* Created: Fri Aug 28 13:45:39 2020
+* Created: Wed Sep 2 11:18:25 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o21ai/sky130_fd_sc_ls__o21ai_4.pxi.spice b/cells/o21ai/sky130_fd_sc_ls__o21ai_4.pxi.spice
index 7cf48af..5df3967 100644
--- a/cells/o21ai/sky130_fd_sc_ls__o21ai_4.pxi.spice
+++ b/cells/o21ai/sky130_fd_sc_ls__o21ai_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o21ai_4.pxi.spice
-* Created: Fri Aug 28 13:45:39 2020
+* Created: Wed Sep 2 11:18:25 2020
*
x_PM_SKY130_FD_SC_LS__O21AI_4%A1 N_A1_M1008_g N_A1_c_98_n N_A1_M1001_g
+ N_A1_M1016_g N_A1_c_99_n N_A1_M1012_g N_A1_M1017_g N_A1_c_100_n N_A1_M1013_g
diff --git a/cells/o21ai/sky130_fd_sc_ls__o21ai_4.spice b/cells/o21ai/sky130_fd_sc_ls__o21ai_4.spice
index b9f14d2..716aeac 100644
--- a/cells/o21ai/sky130_fd_sc_ls__o21ai_4.spice
+++ b/cells/o21ai/sky130_fd_sc_ls__o21ai_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o21ai_4.spice
-* Created: Fri Aug 28 13:45:39 2020
+* Created: Wed Sep 2 11:18:25 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o21ba/sky130_fd_sc_ls__o21ba_1.lvs.report b/cells/o21ba/sky130_fd_sc_ls__o21ba_1.lvs.report
new file mode 100644
index 0000000..4b4a69e
--- /dev/null
+++ b/cells/o21ba/sky130_fd_sc_ls__o21ba_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__o21ba_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__o21ba_1.sp ('sky130_fd_sc_ls__o21ba_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/o21ba/sky130_fd_sc_ls__o21ba_1.spice ('sky130_fd_sc_ls__o21ba_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:18:29 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__o21ba_1 sky130_fd_sc_ls__o21ba_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__o21ba_1
+SOURCE CELL NAME: sky130_fd_sc_ls__o21ba_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 12 12
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 10 10
+
+ Instances: 2 2 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1 (5 pins)
+ ------ ------
+ Total Inst: 7 7
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 3 3 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1
+ ------- ------- --------- ---------
+ Total Inst: 7 7 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1 A2 B1_N VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o21ba/sky130_fd_sc_ls__o21ba_1.pex.spice b/cells/o21ba/sky130_fd_sc_ls__o21ba_1.pex.spice
index 72660f0..06867c4 100644
--- a/cells/o21ba/sky130_fd_sc_ls__o21ba_1.pex.spice
+++ b/cells/o21ba/sky130_fd_sc_ls__o21ba_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o21ba_1.pex.spice
-* Created: Fri Aug 28 13:45:49 2020
+* Created: Wed Sep 2 11:18:32 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o21ba/sky130_fd_sc_ls__o21ba_1.pxi.spice b/cells/o21ba/sky130_fd_sc_ls__o21ba_1.pxi.spice
index ae7945e..1c4da31 100644
--- a/cells/o21ba/sky130_fd_sc_ls__o21ba_1.pxi.spice
+++ b/cells/o21ba/sky130_fd_sc_ls__o21ba_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o21ba_1.pxi.spice
-* Created: Fri Aug 28 13:45:49 2020
+* Created: Wed Sep 2 11:18:32 2020
*
x_PM_SKY130_FD_SC_LS__O21BA_1%A1 N_A1_c_73_n N_A1_M1007_g N_A1_c_78_n
+ N_A1_M1006_g A1 A1 N_A1_c_75_n N_A1_c_76_n PM_SKY130_FD_SC_LS__O21BA_1%A1
diff --git a/cells/o21ba/sky130_fd_sc_ls__o21ba_1.spice b/cells/o21ba/sky130_fd_sc_ls__o21ba_1.spice
index 9054a87..e8d9248 100644
--- a/cells/o21ba/sky130_fd_sc_ls__o21ba_1.spice
+++ b/cells/o21ba/sky130_fd_sc_ls__o21ba_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o21ba_1.spice
-* Created: Fri Aug 28 13:45:49 2020
+* Created: Wed Sep 2 11:18:32 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o21ba/sky130_fd_sc_ls__o21ba_2.lvs.report b/cells/o21ba/sky130_fd_sc_ls__o21ba_2.lvs.report
new file mode 100644
index 0000000..6cf82dc
--- /dev/null
+++ b/cells/o21ba/sky130_fd_sc_ls__o21ba_2.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__o21ba_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__o21ba_2.sp ('sky130_fd_sc_ls__o21ba_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/o21ba/sky130_fd_sc_ls__o21ba_2.spice ('sky130_fd_sc_ls__o21ba_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:18:36 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__o21ba_2 sky130_fd_sc_ls__o21ba_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__o21ba_2
+SOURCE CELL NAME: sky130_fd_sc_ls__o21ba_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 12 12
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 10 10
+
+ Instances: 2 2 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1 (5 pins)
+ ------ ------
+ Total Inst: 7 7
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 3 3 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1
+ ------- ------- --------- ---------
+ Total Inst: 7 7 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1_N A2 A1 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o21ba/sky130_fd_sc_ls__o21ba_2.pex.spice b/cells/o21ba/sky130_fd_sc_ls__o21ba_2.pex.spice
index cb3d671..6ab9e75 100644
--- a/cells/o21ba/sky130_fd_sc_ls__o21ba_2.pex.spice
+++ b/cells/o21ba/sky130_fd_sc_ls__o21ba_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o21ba_2.pex.spice
-* Created: Fri Aug 28 13:46:00 2020
+* Created: Wed Sep 2 11:18:39 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o21ba/sky130_fd_sc_ls__o21ba_2.pxi.spice b/cells/o21ba/sky130_fd_sc_ls__o21ba_2.pxi.spice
index 1bf9eaf..18d1689 100644
--- a/cells/o21ba/sky130_fd_sc_ls__o21ba_2.pxi.spice
+++ b/cells/o21ba/sky130_fd_sc_ls__o21ba_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o21ba_2.pxi.spice
-* Created: Fri Aug 28 13:46:00 2020
+* Created: Wed Sep 2 11:18:39 2020
*
x_PM_SKY130_FD_SC_LS__O21BA_2%B1_N N_B1_N_M1002_g N_B1_N_c_70_n N_B1_N_M1003_g
+ B1_N N_B1_N_c_71_n PM_SKY130_FD_SC_LS__O21BA_2%B1_N
diff --git a/cells/o21ba/sky130_fd_sc_ls__o21ba_2.spice b/cells/o21ba/sky130_fd_sc_ls__o21ba_2.spice
index fcd7691..a13c7d4 100644
--- a/cells/o21ba/sky130_fd_sc_ls__o21ba_2.spice
+++ b/cells/o21ba/sky130_fd_sc_ls__o21ba_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o21ba_2.spice
-* Created: Fri Aug 28 13:46:00 2020
+* Created: Wed Sep 2 11:18:39 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o21ba/sky130_fd_sc_ls__o21ba_4.lvs.report b/cells/o21ba/sky130_fd_sc_ls__o21ba_4.lvs.report
new file mode 100644
index 0000000..bb5f87c
--- /dev/null
+++ b/cells/o21ba/sky130_fd_sc_ls__o21ba_4.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__o21ba_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__o21ba_4.sp ('sky130_fd_sc_ls__o21ba_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/o21ba/sky130_fd_sc_ls__o21ba_4.spice ('sky130_fd_sc_ls__o21ba_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:18:42 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__o21ba_4 sky130_fd_sc_ls__o21ba_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__o21ba_4
+SOURCE CELL NAME: sky130_fd_sc_ls__o21ba_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 12 12
+
+ Instances: 11 11 MN (4 pins)
+ 11 11 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 23 22
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 10 10
+
+ Instances: 2 2 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1 (5 pins)
+ ------ ------
+ Total Inst: 7 7
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 3 3 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1
+ ------- ------- --------- ---------
+ Total Inst: 7 7 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 20 layout mos transistors were reduced to 8.
+ 12 mos transistors were deleted by parallel reduction.
+ 20 source mos transistors were reduced to 8.
+ 12 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1_N A2 A1 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o21ba/sky130_fd_sc_ls__o21ba_4.pex.spice b/cells/o21ba/sky130_fd_sc_ls__o21ba_4.pex.spice
index 93c1d76..51ed706 100644
--- a/cells/o21ba/sky130_fd_sc_ls__o21ba_4.pex.spice
+++ b/cells/o21ba/sky130_fd_sc_ls__o21ba_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o21ba_4.pex.spice
-* Created: Fri Aug 28 13:46:09 2020
+* Created: Wed Sep 2 11:18:46 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o21ba/sky130_fd_sc_ls__o21ba_4.pxi.spice b/cells/o21ba/sky130_fd_sc_ls__o21ba_4.pxi.spice
index 802ed75..21cf318 100644
--- a/cells/o21ba/sky130_fd_sc_ls__o21ba_4.pxi.spice
+++ b/cells/o21ba/sky130_fd_sc_ls__o21ba_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o21ba_4.pxi.spice
-* Created: Fri Aug 28 13:46:09 2020
+* Created: Wed Sep 2 11:18:46 2020
*
x_PM_SKY130_FD_SC_LS__O21BA_4%B1_N N_B1_N_c_115_n N_B1_N_M1015_g N_B1_N_c_116_n
+ N_B1_N_M1018_g B1_N PM_SKY130_FD_SC_LS__O21BA_4%B1_N
diff --git a/cells/o21ba/sky130_fd_sc_ls__o21ba_4.spice b/cells/o21ba/sky130_fd_sc_ls__o21ba_4.spice
index 3846335..12b266b 100644
--- a/cells/o21ba/sky130_fd_sc_ls__o21ba_4.spice
+++ b/cells/o21ba/sky130_fd_sc_ls__o21ba_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o21ba_4.spice
-* Created: Fri Aug 28 13:46:09 2020
+* Created: Wed Sep 2 11:18:46 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o21bai/sky130_fd_sc_ls__o21bai_1.lvs.report b/cells/o21bai/sky130_fd_sc_ls__o21bai_1.lvs.report
new file mode 100644
index 0000000..8d323d8
--- /dev/null
+++ b/cells/o21bai/sky130_fd_sc_ls__o21bai_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__o21bai_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__o21bai_1.sp ('sky130_fd_sc_ls__o21bai_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/o21bai/sky130_fd_sc_ls__o21bai_1.spice ('sky130_fd_sc_ls__o21bai_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:18:49 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__o21bai_1 sky130_fd_sc_ls__o21bai_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__o21bai_1
+SOURCE CELL NAME: sky130_fd_sc_ls__o21bai_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 11 11
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 9 9
+
+ Instances: 1 1 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1 (5 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1_N A2 A1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o21bai/sky130_fd_sc_ls__o21bai_1.pex.spice b/cells/o21bai/sky130_fd_sc_ls__o21bai_1.pex.spice
index 95a21a8..d2ed6c1 100644
--- a/cells/o21bai/sky130_fd_sc_ls__o21bai_1.pex.spice
+++ b/cells/o21bai/sky130_fd_sc_ls__o21bai_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o21bai_1.pex.spice
-* Created: Fri Aug 28 13:46:27 2020
+* Created: Wed Sep 2 11:18:52 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o21bai/sky130_fd_sc_ls__o21bai_1.pxi.spice b/cells/o21bai/sky130_fd_sc_ls__o21bai_1.pxi.spice
index de17a6f..da1aa40 100644
--- a/cells/o21bai/sky130_fd_sc_ls__o21bai_1.pxi.spice
+++ b/cells/o21bai/sky130_fd_sc_ls__o21bai_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o21bai_1.pxi.spice
-* Created: Fri Aug 28 13:46:27 2020
+* Created: Wed Sep 2 11:18:52 2020
*
x_PM_SKY130_FD_SC_LS__O21BAI_1%B1_N N_B1_N_M1002_g N_B1_N_c_60_n N_B1_N_M1000_g
+ B1_N N_B1_N_c_61_n PM_SKY130_FD_SC_LS__O21BAI_1%B1_N
diff --git a/cells/o21bai/sky130_fd_sc_ls__o21bai_1.spice b/cells/o21bai/sky130_fd_sc_ls__o21bai_1.spice
index 795fa85..df5aee1 100644
--- a/cells/o21bai/sky130_fd_sc_ls__o21bai_1.spice
+++ b/cells/o21bai/sky130_fd_sc_ls__o21bai_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o21bai_1.spice
-* Created: Fri Aug 28 13:46:27 2020
+* Created: Wed Sep 2 11:18:52 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o21bai/sky130_fd_sc_ls__o21bai_2.lvs.report b/cells/o21bai/sky130_fd_sc_ls__o21bai_2.lvs.report
new file mode 100644
index 0000000..2e7ca71
--- /dev/null
+++ b/cells/o21bai/sky130_fd_sc_ls__o21bai_2.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__o21bai_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__o21bai_2.sp ('sky130_fd_sc_ls__o21bai_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/o21bai/sky130_fd_sc_ls__o21bai_2.spice ('sky130_fd_sc_ls__o21bai_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:18:56 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__o21bai_2 sky130_fd_sc_ls__o21bai_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__o21bai_2
+SOURCE CELL NAME: sky130_fd_sc_ls__o21bai_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 11 11
+
+ Instances: 7 7 MN (4 pins)
+ 7 7 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 15 14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 9 9
+
+ Instances: 1 1 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1 (5 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 12 layout mos transistors were reduced to 6.
+ 6 mos transistors were deleted by parallel reduction.
+ 12 source mos transistors were reduced to 6.
+ 6 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1_N A1 A2 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o21bai/sky130_fd_sc_ls__o21bai_2.pex.spice b/cells/o21bai/sky130_fd_sc_ls__o21bai_2.pex.spice
index 38108a2..b35dccb 100644
--- a/cells/o21bai/sky130_fd_sc_ls__o21bai_2.pex.spice
+++ b/cells/o21bai/sky130_fd_sc_ls__o21bai_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o21bai_2.pex.spice
-* Created: Fri Aug 28 13:46:47 2020
+* Created: Wed Sep 2 11:18:59 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o21bai/sky130_fd_sc_ls__o21bai_2.pxi.spice b/cells/o21bai/sky130_fd_sc_ls__o21bai_2.pxi.spice
index 0f1e480..9f42e11 100644
--- a/cells/o21bai/sky130_fd_sc_ls__o21bai_2.pxi.spice
+++ b/cells/o21bai/sky130_fd_sc_ls__o21bai_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o21bai_2.pxi.spice
-* Created: Fri Aug 28 13:46:47 2020
+* Created: Wed Sep 2 11:18:59 2020
*
x_PM_SKY130_FD_SC_LS__O21BAI_2%B1_N N_B1_N_M1012_g N_B1_N_c_79_n N_B1_N_M1011_g
+ B1_N N_B1_N_c_80_n PM_SKY130_FD_SC_LS__O21BAI_2%B1_N
diff --git a/cells/o21bai/sky130_fd_sc_ls__o21bai_2.spice b/cells/o21bai/sky130_fd_sc_ls__o21bai_2.spice
index 8956a1f..320d6a7 100644
--- a/cells/o21bai/sky130_fd_sc_ls__o21bai_2.spice
+++ b/cells/o21bai/sky130_fd_sc_ls__o21bai_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o21bai_2.spice
-* Created: Fri Aug 28 13:46:47 2020
+* Created: Wed Sep 2 11:18:59 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o21bai/sky130_fd_sc_ls__o21bai_4.lvs.report b/cells/o21bai/sky130_fd_sc_ls__o21bai_4.lvs.report
new file mode 100644
index 0000000..a946278
--- /dev/null
+++ b/cells/o21bai/sky130_fd_sc_ls__o21bai_4.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__o21bai_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__o21bai_4.sp ('sky130_fd_sc_ls__o21bai_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/o21bai/sky130_fd_sc_ls__o21bai_4.spice ('sky130_fd_sc_ls__o21bai_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:19:02 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__o21bai_4 sky130_fd_sc_ls__o21bai_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__o21bai_4
+SOURCE CELL NAME: sky130_fd_sc_ls__o21bai_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 11 11
+
+ Instances: 13 13 MN (4 pins)
+ 12 12 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 26 25
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 9 9
+
+ Instances: 1 1 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1 (5 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 24 layout mos transistors were reduced to 7.
+ 17 mos transistors were deleted by parallel reduction.
+ 24 source mos transistors were reduced to 7.
+ 17 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1 A2 B1_N VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o21bai/sky130_fd_sc_ls__o21bai_4.pex.spice b/cells/o21bai/sky130_fd_sc_ls__o21bai_4.pex.spice
index 83a8c0b..2824036 100644
--- a/cells/o21bai/sky130_fd_sc_ls__o21bai_4.pex.spice
+++ b/cells/o21bai/sky130_fd_sc_ls__o21bai_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o21bai_4.pex.spice
-* Created: Fri Aug 28 13:46:57 2020
+* Created: Wed Sep 2 11:19:06 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o21bai/sky130_fd_sc_ls__o21bai_4.pxi.spice b/cells/o21bai/sky130_fd_sc_ls__o21bai_4.pxi.spice
index 219b5c7..ad2222e 100644
--- a/cells/o21bai/sky130_fd_sc_ls__o21bai_4.pxi.spice
+++ b/cells/o21bai/sky130_fd_sc_ls__o21bai_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o21bai_4.pxi.spice
-* Created: Fri Aug 28 13:46:57 2020
+* Created: Wed Sep 2 11:19:06 2020
*
x_PM_SKY130_FD_SC_LS__O21BAI_4%A1 N_A1_M1004_g N_A1_c_135_n N_A1_M1011_g
+ N_A1_c_136_n N_A1_M1012_g N_A1_M1013_g N_A1_M1014_g N_A1_c_137_n N_A1_M1016_g
diff --git a/cells/o21bai/sky130_fd_sc_ls__o21bai_4.spice b/cells/o21bai/sky130_fd_sc_ls__o21bai_4.spice
index c7c1a4c..f307329 100644
--- a/cells/o21bai/sky130_fd_sc_ls__o21bai_4.spice
+++ b/cells/o21bai/sky130_fd_sc_ls__o21bai_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o21bai_4.spice
-* Created: Fri Aug 28 13:46:57 2020
+* Created: Wed Sep 2 11:19:06 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o221a/sky130_fd_sc_ls__o221a_1.lvs.report b/cells/o221a/sky130_fd_sc_ls__o221a_1.lvs.report
new file mode 100644
index 0000000..ebef53a
--- /dev/null
+++ b/cells/o221a/sky130_fd_sc_ls__o221a_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__o221a_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__o221a_1.sp ('sky130_fd_sc_ls__o221a_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/o221a/sky130_fd_sc_ls__o221a_1.spice ('sky130_fd_sc_ls__o221a_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:19:09 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__o221a_1 sky130_fd_sc_ls__o221a_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__o221a_1
+SOURCE CELL NAME: sky130_fd_sc_ls__o221a_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 15 15
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 11 11
+
+ Instances: 1 1 MN (4 pins)
+ 2 2 MP (4 pins)
+ 2 2 SMP2 (4 pins)
+ 1 1 SPMN_2_2_1 (7 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMP2
+ 1 1 0 0 SPMN_2_2_1
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1 A2 B2 B1 C1 X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o221a/sky130_fd_sc_ls__o221a_1.pex.spice b/cells/o221a/sky130_fd_sc_ls__o221a_1.pex.spice
index 7a186df..356ad60 100644
--- a/cells/o221a/sky130_fd_sc_ls__o221a_1.pex.spice
+++ b/cells/o221a/sky130_fd_sc_ls__o221a_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o221a_1.pex.spice
-* Created: Fri Aug 28 13:47:08 2020
+* Created: Wed Sep 2 11:19:12 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o221a/sky130_fd_sc_ls__o221a_1.pxi.spice b/cells/o221a/sky130_fd_sc_ls__o221a_1.pxi.spice
index d62b066..8797514 100644
--- a/cells/o221a/sky130_fd_sc_ls__o221a_1.pxi.spice
+++ b/cells/o221a/sky130_fd_sc_ls__o221a_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o221a_1.pxi.spice
-* Created: Fri Aug 28 13:47:08 2020
+* Created: Wed Sep 2 11:19:12 2020
*
x_PM_SKY130_FD_SC_LS__O221A_1%A_83_264# N_A_83_264#_M1003_d N_A_83_264#_M1002_d
+ N_A_83_264#_M1009_d N_A_83_264#_c_73_n N_A_83_264#_M1006_g N_A_83_264#_M1001_g
diff --git a/cells/o221a/sky130_fd_sc_ls__o221a_1.spice b/cells/o221a/sky130_fd_sc_ls__o221a_1.spice
index e157642..3fdb100 100644
--- a/cells/o221a/sky130_fd_sc_ls__o221a_1.spice
+++ b/cells/o221a/sky130_fd_sc_ls__o221a_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o221a_1.spice
-* Created: Fri Aug 28 13:47:08 2020
+* Created: Wed Sep 2 11:19:12 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o221a/sky130_fd_sc_ls__o221a_2.lvs.report b/cells/o221a/sky130_fd_sc_ls__o221a_2.lvs.report
new file mode 100644
index 0000000..a9529e5
--- /dev/null
+++ b/cells/o221a/sky130_fd_sc_ls__o221a_2.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__o221a_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__o221a_2.sp ('sky130_fd_sc_ls__o221a_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/o221a/sky130_fd_sc_ls__o221a_2.spice ('sky130_fd_sc_ls__o221a_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:19:16 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__o221a_2 sky130_fd_sc_ls__o221a_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__o221a_2
+SOURCE CELL NAME: sky130_fd_sc_ls__o221a_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 15 15
+
+ Instances: 7 7 MN (4 pins)
+ 7 7 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 15 14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 11 11
+
+ Instances: 1 1 MN (4 pins)
+ 2 2 MP (4 pins)
+ 2 2 SMP2 (4 pins)
+ 1 1 SPMN_2_2_1 (7 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMP2
+ 1 1 0 0 SPMN_2_2_1
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB C1 B1 B2 A2 A1 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o221a/sky130_fd_sc_ls__o221a_2.pex.spice b/cells/o221a/sky130_fd_sc_ls__o221a_2.pex.spice
index 986a7ec..50a2dea 100644
--- a/cells/o221a/sky130_fd_sc_ls__o221a_2.pex.spice
+++ b/cells/o221a/sky130_fd_sc_ls__o221a_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o221a_2.pex.spice
-* Created: Fri Aug 28 13:47:18 2020
+* Created: Wed Sep 2 11:19:19 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o221a/sky130_fd_sc_ls__o221a_2.pxi.spice b/cells/o221a/sky130_fd_sc_ls__o221a_2.pxi.spice
index ed92963..025ebb9 100644
--- a/cells/o221a/sky130_fd_sc_ls__o221a_2.pxi.spice
+++ b/cells/o221a/sky130_fd_sc_ls__o221a_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o221a_2.pxi.spice
-* Created: Fri Aug 28 13:47:18 2020
+* Created: Wed Sep 2 11:19:19 2020
*
x_PM_SKY130_FD_SC_LS__O221A_2%C1 N_C1_c_84_n N_C1_M1010_g N_C1_c_81_n
+ N_C1_M1005_g C1 N_C1_c_83_n PM_SKY130_FD_SC_LS__O221A_2%C1
diff --git a/cells/o221a/sky130_fd_sc_ls__o221a_2.spice b/cells/o221a/sky130_fd_sc_ls__o221a_2.spice
index 6be68bd..39cb79b 100644
--- a/cells/o221a/sky130_fd_sc_ls__o221a_2.spice
+++ b/cells/o221a/sky130_fd_sc_ls__o221a_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o221a_2.spice
-* Created: Fri Aug 28 13:47:18 2020
+* Created: Wed Sep 2 11:19:19 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o221a/sky130_fd_sc_ls__o221a_4.lvs.report b/cells/o221a/sky130_fd_sc_ls__o221a_4.lvs.report
new file mode 100644
index 0000000..7e0edfc
--- /dev/null
+++ b/cells/o221a/sky130_fd_sc_ls__o221a_4.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__o221a_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__o221a_4.sp ('sky130_fd_sc_ls__o221a_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/o221a/sky130_fd_sc_ls__o221a_4.spice ('sky130_fd_sc_ls__o221a_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:19:22 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__o221a_4 sky130_fd_sc_ls__o221a_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__o221a_4
+SOURCE CELL NAME: sky130_fd_sc_ls__o221a_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 15 15
+
+ Instances: 14 14 MN (4 pins)
+ 14 14 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 29 28
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 11 11
+
+ Instances: 1 1 MN (4 pins)
+ 2 2 MP (4 pins)
+ 2 2 SMP2 (4 pins)
+ 1 1 SPMN_2_2_1 (7 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMP2
+ 1 1 0 0 SPMN_2_2_1
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 28 layout mos transistors were reduced to 12.
+ 16 mos transistors were deleted by parallel reduction.
+ 28 source mos transistors were reduced to 12.
+ 16 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB C1 B2 B1 A2 A1 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o221a/sky130_fd_sc_ls__o221a_4.pex.spice b/cells/o221a/sky130_fd_sc_ls__o221a_4.pex.spice
index af95da7..0658877 100644
--- a/cells/o221a/sky130_fd_sc_ls__o221a_4.pex.spice
+++ b/cells/o221a/sky130_fd_sc_ls__o221a_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o221a_4.pex.spice
-* Created: Fri Aug 28 13:47:35 2020
+* Created: Wed Sep 2 11:19:25 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o221a/sky130_fd_sc_ls__o221a_4.pxi.spice b/cells/o221a/sky130_fd_sc_ls__o221a_4.pxi.spice
index a3a32e5..863fe34 100644
--- a/cells/o221a/sky130_fd_sc_ls__o221a_4.pxi.spice
+++ b/cells/o221a/sky130_fd_sc_ls__o221a_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o221a_4.pxi.spice
-* Created: Fri Aug 28 13:47:35 2020
+* Created: Wed Sep 2 11:19:25 2020
*
x_PM_SKY130_FD_SC_LS__O221A_4%C1 N_C1_M1014_g N_C1_c_146_n N_C1_M1023_g
+ N_C1_M1015_g N_C1_c_147_n N_C1_M1024_g C1 C1 N_C1_c_145_n
diff --git a/cells/o221a/sky130_fd_sc_ls__o221a_4.spice b/cells/o221a/sky130_fd_sc_ls__o221a_4.spice
index fba291e..1a7346d 100644
--- a/cells/o221a/sky130_fd_sc_ls__o221a_4.spice
+++ b/cells/o221a/sky130_fd_sc_ls__o221a_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o221a_4.spice
-* Created: Fri Aug 28 13:47:35 2020
+* Created: Wed Sep 2 11:19:25 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o221ai/sky130_fd_sc_ls__o221ai_1.lvs.report b/cells/o221ai/sky130_fd_sc_ls__o221ai_1.lvs.report
new file mode 100644
index 0000000..acbbce7
--- /dev/null
+++ b/cells/o221ai/sky130_fd_sc_ls__o221ai_1.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__o221ai_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__o221ai_1.sp ('sky130_fd_sc_ls__o221ai_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/o221ai/sky130_fd_sc_ls__o221ai_1.spice ('sky130_fd_sc_ls__o221ai_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:19:29 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__o221ai_1 sky130_fd_sc_ls__o221ai_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__o221ai_1
+SOURCE CELL NAME: sky130_fd_sc_ls__o221ai_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 14 14
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 10 10
+
+ Instances: 1 1 MP (4 pins)
+ 2 2 SMP2 (4 pins)
+ 1 1 SPMN_2_2_1 (7 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMP2
+ 1 1 0 0 SPMN_2_2_1
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB C1 B1 B2 A2 A1 Y VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o221ai/sky130_fd_sc_ls__o221ai_1.pex.spice b/cells/o221ai/sky130_fd_sc_ls__o221ai_1.pex.spice
index f9d0b0c..c9d528b 100644
--- a/cells/o221ai/sky130_fd_sc_ls__o221ai_1.pex.spice
+++ b/cells/o221ai/sky130_fd_sc_ls__o221ai_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o221ai_1.pex.spice
-* Created: Fri Aug 28 13:47:55 2020
+* Created: Wed Sep 2 11:19:32 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o221ai/sky130_fd_sc_ls__o221ai_1.pxi.spice b/cells/o221ai/sky130_fd_sc_ls__o221ai_1.pxi.spice
index b650655..f4a63f0 100644
--- a/cells/o221ai/sky130_fd_sc_ls__o221ai_1.pxi.spice
+++ b/cells/o221ai/sky130_fd_sc_ls__o221ai_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o221ai_1.pxi.spice
-* Created: Fri Aug 28 13:47:55 2020
+* Created: Wed Sep 2 11:19:32 2020
*
x_PM_SKY130_FD_SC_LS__O221AI_1%C1 N_C1_M1008_g N_C1_c_61_n N_C1_M1000_g C1
+ N_C1_c_59_n N_C1_c_60_n PM_SKY130_FD_SC_LS__O221AI_1%C1
diff --git a/cells/o221ai/sky130_fd_sc_ls__o221ai_1.spice b/cells/o221ai/sky130_fd_sc_ls__o221ai_1.spice
index f47e984..f91de50 100644
--- a/cells/o221ai/sky130_fd_sc_ls__o221ai_1.spice
+++ b/cells/o221ai/sky130_fd_sc_ls__o221ai_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o221ai_1.spice
-* Created: Fri Aug 28 13:47:55 2020
+* Created: Wed Sep 2 11:19:32 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o221ai/sky130_fd_sc_ls__o221ai_2.lvs.report b/cells/o221ai/sky130_fd_sc_ls__o221ai_2.lvs.report
new file mode 100644
index 0000000..e7c96ac
--- /dev/null
+++ b/cells/o221ai/sky130_fd_sc_ls__o221ai_2.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__o221ai_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__o221ai_2.sp ('sky130_fd_sc_ls__o221ai_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/o221ai/sky130_fd_sc_ls__o221ai_2.spice ('sky130_fd_sc_ls__o221ai_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:19:36 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__o221ai_2 sky130_fd_sc_ls__o221ai_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__o221ai_2
+SOURCE CELL NAME: sky130_fd_sc_ls__o221ai_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 14 14
+
+ Instances: 10 10 MN (4 pins)
+ 10 10 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 21 20
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 10 10
+
+ Instances: 1 1 MP (4 pins)
+ 2 2 SMP2 (4 pins)
+ 1 1 SPMN_2_2_1 (7 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMP2
+ 1 1 0 0 SPMN_2_2_1
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 20 layout mos transistors were reduced to 10.
+ 10 mos transistors were deleted by parallel reduction.
+ 20 source mos transistors were reduced to 10.
+ 10 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB C1 B1 B2 A1 A2 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o221ai/sky130_fd_sc_ls__o221ai_2.pex.spice b/cells/o221ai/sky130_fd_sc_ls__o221ai_2.pex.spice
index 235d56c..49837de 100644
--- a/cells/o221ai/sky130_fd_sc_ls__o221ai_2.pex.spice
+++ b/cells/o221ai/sky130_fd_sc_ls__o221ai_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o221ai_2.pex.spice
-* Created: Fri Aug 28 13:48:06 2020
+* Created: Wed Sep 2 11:19:39 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o221ai/sky130_fd_sc_ls__o221ai_2.pxi.spice b/cells/o221ai/sky130_fd_sc_ls__o221ai_2.pxi.spice
index c5ea965..663edf9 100644
--- a/cells/o221ai/sky130_fd_sc_ls__o221ai_2.pxi.spice
+++ b/cells/o221ai/sky130_fd_sc_ls__o221ai_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o221ai_2.pxi.spice
-* Created: Fri Aug 28 13:48:06 2020
+* Created: Wed Sep 2 11:19:39 2020
*
x_PM_SKY130_FD_SC_LS__O221AI_2%C1 N_C1_M1015_g N_C1_c_96_n N_C1_M1013_g
+ N_C1_M1016_g N_C1_c_97_n N_C1_M1014_g C1 N_C1_c_94_n N_C1_c_95_n
diff --git a/cells/o221ai/sky130_fd_sc_ls__o221ai_2.spice b/cells/o221ai/sky130_fd_sc_ls__o221ai_2.spice
index 3eceff8..82ad9b0 100644
--- a/cells/o221ai/sky130_fd_sc_ls__o221ai_2.spice
+++ b/cells/o221ai/sky130_fd_sc_ls__o221ai_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o221ai_2.spice
-* Created: Fri Aug 28 13:48:06 2020
+* Created: Wed Sep 2 11:19:39 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o221ai/sky130_fd_sc_ls__o221ai_4.lvs.report b/cells/o221ai/sky130_fd_sc_ls__o221ai_4.lvs.report
new file mode 100644
index 0000000..e80efd5
--- /dev/null
+++ b/cells/o221ai/sky130_fd_sc_ls__o221ai_4.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__o221ai_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__o221ai_4.sp ('sky130_fd_sc_ls__o221ai_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/o221ai/sky130_fd_sc_ls__o221ai_4.spice ('sky130_fd_sc_ls__o221ai_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:19:42 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__o221ai_4 sky130_fd_sc_ls__o221ai_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__o221ai_4
+SOURCE CELL NAME: sky130_fd_sc_ls__o221ai_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 14 14
+
+ Instances: 20 20 MN (4 pins)
+ 20 20 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 41 40
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 10 10
+
+ Instances: 1 1 MP (4 pins)
+ 2 2 SMP2 (4 pins)
+ 1 1 SPMN_2_2_1 (7 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMP2
+ 1 1 0 0 SPMN_2_2_1
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 40 layout mos transistors were reduced to 10.
+ 30 mos transistors were deleted by parallel reduction.
+ 40 source mos transistors were reduced to 10.
+ 30 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB C1 B1 B2 A1 A2 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o221ai/sky130_fd_sc_ls__o221ai_4.pex.spice b/cells/o221ai/sky130_fd_sc_ls__o221ai_4.pex.spice
index 40867b2..fc1a8b3 100644
--- a/cells/o221ai/sky130_fd_sc_ls__o221ai_4.pex.spice
+++ b/cells/o221ai/sky130_fd_sc_ls__o221ai_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o221ai_4.pex.spice
-* Created: Fri Aug 28 13:48:16 2020
+* Created: Wed Sep 2 11:19:45 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o221ai/sky130_fd_sc_ls__o221ai_4.pxi.spice b/cells/o221ai/sky130_fd_sc_ls__o221ai_4.pxi.spice
index 7531a6b..d7a17e1 100644
--- a/cells/o221ai/sky130_fd_sc_ls__o221ai_4.pxi.spice
+++ b/cells/o221ai/sky130_fd_sc_ls__o221ai_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o221ai_4.pxi.spice
-* Created: Fri Aug 28 13:48:16 2020
+* Created: Wed Sep 2 11:19:45 2020
*
x_PM_SKY130_FD_SC_LS__O221AI_4%C1 N_C1_M1000_g N_C1_c_148_n N_C1_M1002_g
+ N_C1_M1021_g N_C1_c_149_n N_C1_M1023_g N_C1_M1038_g N_C1_c_150_n N_C1_M1024_g
diff --git a/cells/o221ai/sky130_fd_sc_ls__o221ai_4.spice b/cells/o221ai/sky130_fd_sc_ls__o221ai_4.spice
index 9e3fc95..8db295c 100644
--- a/cells/o221ai/sky130_fd_sc_ls__o221ai_4.spice
+++ b/cells/o221ai/sky130_fd_sc_ls__o221ai_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o221ai_4.spice
-* Created: Fri Aug 28 13:48:16 2020
+* Created: Wed Sep 2 11:19:45 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o22a/sky130_fd_sc_ls__o22a_1.lvs.report b/cells/o22a/sky130_fd_sc_ls__o22a_1.lvs.report
new file mode 100644
index 0000000..c10b781
--- /dev/null
+++ b/cells/o22a/sky130_fd_sc_ls__o22a_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__o22a_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__o22a_1.sp ('sky130_fd_sc_ls__o22a_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/o22a/sky130_fd_sc_ls__o22a_1.spice ('sky130_fd_sc_ls__o22a_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:19:49 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__o22a_1 sky130_fd_sc_ls__o22a_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__o22a_1
+SOURCE CELL NAME: sky130_fd_sc_ls__o22a_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 2 2 SMP2 (4 pins)
+ 1 1 SPMN_2_2 (6 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMP2
+ 1 1 0 0 SPMN_2_2
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1 B2 A2 A1 X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o22a/sky130_fd_sc_ls__o22a_1.pex.spice b/cells/o22a/sky130_fd_sc_ls__o22a_1.pex.spice
index 62abe2b..ec234cf 100644
--- a/cells/o22a/sky130_fd_sc_ls__o22a_1.pex.spice
+++ b/cells/o22a/sky130_fd_sc_ls__o22a_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o22a_1.pex.spice
-* Created: Fri Aug 28 13:48:27 2020
+* Created: Wed Sep 2 11:19:52 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o22a/sky130_fd_sc_ls__o22a_1.pxi.spice b/cells/o22a/sky130_fd_sc_ls__o22a_1.pxi.spice
index 42a15ea..0a47a9e 100644
--- a/cells/o22a/sky130_fd_sc_ls__o22a_1.pxi.spice
+++ b/cells/o22a/sky130_fd_sc_ls__o22a_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o22a_1.pxi.spice
-* Created: Fri Aug 28 13:48:27 2020
+* Created: Wed Sep 2 11:19:52 2020
*
x_PM_SKY130_FD_SC_LS__O22A_1%A_83_260# N_A_83_260#_M1003_d N_A_83_260#_M1008_d
+ N_A_83_260#_M1009_g N_A_83_260#_c_67_n N_A_83_260#_M1006_g N_A_83_260#_c_62_n
diff --git a/cells/o22a/sky130_fd_sc_ls__o22a_1.spice b/cells/o22a/sky130_fd_sc_ls__o22a_1.spice
index ea2ee53..39d1ad0 100644
--- a/cells/o22a/sky130_fd_sc_ls__o22a_1.spice
+++ b/cells/o22a/sky130_fd_sc_ls__o22a_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o22a_1.spice
-* Created: Fri Aug 28 13:48:27 2020
+* Created: Wed Sep 2 11:19:52 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o22a/sky130_fd_sc_ls__o22a_2.lvs.report b/cells/o22a/sky130_fd_sc_ls__o22a_2.lvs.report
new file mode 100644
index 0000000..e50afb3
--- /dev/null
+++ b/cells/o22a/sky130_fd_sc_ls__o22a_2.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__o22a_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__o22a_2.sp ('sky130_fd_sc_ls__o22a_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/o22a/sky130_fd_sc_ls__o22a_2.spice ('sky130_fd_sc_ls__o22a_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:19:56 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__o22a_2 sky130_fd_sc_ls__o22a_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__o22a_2
+SOURCE CELL NAME: sky130_fd_sc_ls__o22a_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 2 2 SMP2 (4 pins)
+ 1 1 SPMN_2_2 (6 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMP2
+ 1 1 0 0 SPMN_2_2
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1 B2 A2 A1 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o22a/sky130_fd_sc_ls__o22a_2.pex.spice b/cells/o22a/sky130_fd_sc_ls__o22a_2.pex.spice
index 8c76391..6670d82 100644
--- a/cells/o22a/sky130_fd_sc_ls__o22a_2.pex.spice
+++ b/cells/o22a/sky130_fd_sc_ls__o22a_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o22a_2.pex.spice
-* Created: Fri Aug 28 13:48:43 2020
+* Created: Wed Sep 2 11:19:59 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o22a/sky130_fd_sc_ls__o22a_2.pxi.spice b/cells/o22a/sky130_fd_sc_ls__o22a_2.pxi.spice
index 00f4658..14aea16 100644
--- a/cells/o22a/sky130_fd_sc_ls__o22a_2.pxi.spice
+++ b/cells/o22a/sky130_fd_sc_ls__o22a_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o22a_2.pxi.spice
-* Created: Fri Aug 28 13:48:43 2020
+* Created: Wed Sep 2 11:19:59 2020
*
x_PM_SKY130_FD_SC_LS__O22A_2%A_82_48# N_A_82_48#_M1002_d N_A_82_48#_M1004_d
+ N_A_82_48#_M1006_g N_A_82_48#_c_76_n N_A_82_48#_M1000_g N_A_82_48#_M1008_g
diff --git a/cells/o22a/sky130_fd_sc_ls__o22a_2.spice b/cells/o22a/sky130_fd_sc_ls__o22a_2.spice
index 530e617..cc89a11 100644
--- a/cells/o22a/sky130_fd_sc_ls__o22a_2.spice
+++ b/cells/o22a/sky130_fd_sc_ls__o22a_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o22a_2.spice
-* Created: Fri Aug 28 13:48:43 2020
+* Created: Wed Sep 2 11:19:59 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o22a/sky130_fd_sc_ls__o22a_4.lvs.report b/cells/o22a/sky130_fd_sc_ls__o22a_4.lvs.report
new file mode 100644
index 0000000..7299134
--- /dev/null
+++ b/cells/o22a/sky130_fd_sc_ls__o22a_4.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__o22a_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__o22a_4.sp ('sky130_fd_sc_ls__o22a_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/o22a/sky130_fd_sc_ls__o22a_4.spice ('sky130_fd_sc_ls__o22a_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:20:02 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__o22a_4 sky130_fd_sc_ls__o22a_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__o22a_4
+SOURCE CELL NAME: sky130_fd_sc_ls__o22a_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 12 12 MN (4 pins)
+ 12 12 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 25 24
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 2 2 SMP2 (4 pins)
+ 1 1 SPMN_2_2 (6 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMP2
+ 1 1 0 0 SPMN_2_2
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 24 layout mos transistors were reduced to 10.
+ 14 mos transistors were deleted by parallel reduction.
+ 24 source mos transistors were reduced to 10.
+ 14 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A2 A1 B2 B1 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o22a/sky130_fd_sc_ls__o22a_4.pex.spice b/cells/o22a/sky130_fd_sc_ls__o22a_4.pex.spice
index b79663a..2cafd5a 100644
--- a/cells/o22a/sky130_fd_sc_ls__o22a_4.pex.spice
+++ b/cells/o22a/sky130_fd_sc_ls__o22a_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o22a_4.pex.spice
-* Created: Fri Aug 28 13:49:04 2020
+* Created: Wed Sep 2 11:20:06 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o22a/sky130_fd_sc_ls__o22a_4.pxi.spice b/cells/o22a/sky130_fd_sc_ls__o22a_4.pxi.spice
index 8ef72ac..b22a0b7 100644
--- a/cells/o22a/sky130_fd_sc_ls__o22a_4.pxi.spice
+++ b/cells/o22a/sky130_fd_sc_ls__o22a_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o22a_4.pxi.spice
-* Created: Fri Aug 28 13:49:04 2020
+* Created: Wed Sep 2 11:20:06 2020
*
x_PM_SKY130_FD_SC_LS__O22A_4%A2 N_A2_c_119_n N_A2_M1017_g N_A2_M1012_g
+ N_A2_c_116_n N_A2_M1014_g N_A2_c_120_n N_A2_M1022_g A2 N_A2_c_117_n
diff --git a/cells/o22a/sky130_fd_sc_ls__o22a_4.spice b/cells/o22a/sky130_fd_sc_ls__o22a_4.spice
index c1de1e3..bb74e78 100644
--- a/cells/o22a/sky130_fd_sc_ls__o22a_4.spice
+++ b/cells/o22a/sky130_fd_sc_ls__o22a_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o22a_4.spice
-* Created: Fri Aug 28 13:49:04 2020
+* Created: Wed Sep 2 11:20:06 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o22ai/sky130_fd_sc_ls__o22ai_1.lvs.report b/cells/o22ai/sky130_fd_sc_ls__o22ai_1.lvs.report
new file mode 100644
index 0000000..fd67e52
--- /dev/null
+++ b/cells/o22ai/sky130_fd_sc_ls__o22ai_1.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__o22ai_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__o22ai_1.sp ('sky130_fd_sc_ls__o22ai_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/o22ai/sky130_fd_sc_ls__o22ai_1.spice ('sky130_fd_sc_ls__o22ai_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:20:09 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__o22ai_1 sky130_fd_sc_ls__o22ai_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__o22ai_1
+SOURCE CELL NAME: sky130_fd_sc_ls__o22ai_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 12 12
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 9 9
+
+ Instances: 2 2 SMP2 (4 pins)
+ 1 1 SPMN_2_2 (6 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 2 2 0 0 SMP2
+ 1 1 0 0 SPMN_2_2
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1 B2 A2 A1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o22ai/sky130_fd_sc_ls__o22ai_1.pex.spice b/cells/o22ai/sky130_fd_sc_ls__o22ai_1.pex.spice
index 911d29c..4eaf215 100644
--- a/cells/o22ai/sky130_fd_sc_ls__o22ai_1.pex.spice
+++ b/cells/o22ai/sky130_fd_sc_ls__o22ai_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o22ai_1.pex.spice
-* Created: Fri Aug 28 13:49:15 2020
+* Created: Wed Sep 2 11:20:12 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o22ai/sky130_fd_sc_ls__o22ai_1.pxi.spice b/cells/o22ai/sky130_fd_sc_ls__o22ai_1.pxi.spice
index a78d7f7..70bf10f 100644
--- a/cells/o22ai/sky130_fd_sc_ls__o22ai_1.pxi.spice
+++ b/cells/o22ai/sky130_fd_sc_ls__o22ai_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o22ai_1.pxi.spice
-* Created: Fri Aug 28 13:49:15 2020
+* Created: Wed Sep 2 11:20:12 2020
*
x_PM_SKY130_FD_SC_LS__O22AI_1%B1 N_B1_c_44_n N_B1_M1007_g N_B1_c_45_n
+ N_B1_M1000_g B1 PM_SKY130_FD_SC_LS__O22AI_1%B1
diff --git a/cells/o22ai/sky130_fd_sc_ls__o22ai_1.spice b/cells/o22ai/sky130_fd_sc_ls__o22ai_1.spice
index a596b35..fde0023 100644
--- a/cells/o22ai/sky130_fd_sc_ls__o22ai_1.spice
+++ b/cells/o22ai/sky130_fd_sc_ls__o22ai_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o22ai_1.spice
-* Created: Fri Aug 28 13:49:15 2020
+* Created: Wed Sep 2 11:20:12 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o22ai/sky130_fd_sc_ls__o22ai_2.lvs.report b/cells/o22ai/sky130_fd_sc_ls__o22ai_2.lvs.report
new file mode 100644
index 0000000..d10e0ad
--- /dev/null
+++ b/cells/o22ai/sky130_fd_sc_ls__o22ai_2.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__o22ai_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__o22ai_2.sp ('sky130_fd_sc_ls__o22ai_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/o22ai/sky130_fd_sc_ls__o22ai_2.spice ('sky130_fd_sc_ls__o22ai_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:20:16 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__o22ai_2 sky130_fd_sc_ls__o22ai_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__o22ai_2
+SOURCE CELL NAME: sky130_fd_sc_ls__o22ai_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 12 12
+
+ Instances: 8 8 MN (4 pins)
+ 8 8 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 17 16
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 9 9
+
+ Instances: 2 2 SMP2 (4 pins)
+ 1 1 SPMN_2_2 (6 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 2 2 0 0 SMP2
+ 1 1 0 0 SPMN_2_2
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 16 layout mos transistors were reduced to 8.
+ 8 mos transistors were deleted by parallel reduction.
+ 16 source mos transistors were reduced to 8.
+ 8 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1 B2 A2 A1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o22ai/sky130_fd_sc_ls__o22ai_2.pex.spice b/cells/o22ai/sky130_fd_sc_ls__o22ai_2.pex.spice
index d6ee366..f6887d5 100644
--- a/cells/o22ai/sky130_fd_sc_ls__o22ai_2.pex.spice
+++ b/cells/o22ai/sky130_fd_sc_ls__o22ai_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o22ai_2.pex.spice
-* Created: Fri Aug 28 13:49:25 2020
+* Created: Wed Sep 2 11:20:19 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o22ai/sky130_fd_sc_ls__o22ai_2.pxi.spice b/cells/o22ai/sky130_fd_sc_ls__o22ai_2.pxi.spice
index ab37634..911ac5f 100644
--- a/cells/o22ai/sky130_fd_sc_ls__o22ai_2.pxi.spice
+++ b/cells/o22ai/sky130_fd_sc_ls__o22ai_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o22ai_2.pxi.spice
-* Created: Fri Aug 28 13:49:25 2020
+* Created: Wed Sep 2 11:20:19 2020
*
x_PM_SKY130_FD_SC_LS__O22AI_2%B1 N_B1_M1005_g N_B1_c_83_n N_B1_M1007_g
+ N_B1_c_84_n N_B1_M1008_g N_B1_M1012_g B1 B1 B1 N_B1_c_82_n
diff --git a/cells/o22ai/sky130_fd_sc_ls__o22ai_2.spice b/cells/o22ai/sky130_fd_sc_ls__o22ai_2.spice
index 4353f88..edd6118 100644
--- a/cells/o22ai/sky130_fd_sc_ls__o22ai_2.spice
+++ b/cells/o22ai/sky130_fd_sc_ls__o22ai_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o22ai_2.spice
-* Created: Fri Aug 28 13:49:25 2020
+* Created: Wed Sep 2 11:20:19 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o22ai/sky130_fd_sc_ls__o22ai_4.lvs.report b/cells/o22ai/sky130_fd_sc_ls__o22ai_4.lvs.report
new file mode 100644
index 0000000..d844d6f
--- /dev/null
+++ b/cells/o22ai/sky130_fd_sc_ls__o22ai_4.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__o22ai_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__o22ai_4.sp ('sky130_fd_sc_ls__o22ai_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/o22ai/sky130_fd_sc_ls__o22ai_4.spice ('sky130_fd_sc_ls__o22ai_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:20:22 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__o22ai_4 sky130_fd_sc_ls__o22ai_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__o22ai_4
+SOURCE CELL NAME: sky130_fd_sc_ls__o22ai_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 12 12
+
+ Instances: 16 16 MN (4 pins)
+ 16 16 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 33 32
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 9 9
+
+ Instances: 2 2 SMP2 (4 pins)
+ 1 1 SPMN_2_2 (6 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 2 2 0 0 SMP2
+ 1 1 0 0 SPMN_2_2
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 32 layout mos transistors were reduced to 8.
+ 24 mos transistors were deleted by parallel reduction.
+ 32 source mos transistors were reduced to 8.
+ 24 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1 A2 B1 B2 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o22ai/sky130_fd_sc_ls__o22ai_4.pex.spice b/cells/o22ai/sky130_fd_sc_ls__o22ai_4.pex.spice
index aeb65ca..9294227 100644
--- a/cells/o22ai/sky130_fd_sc_ls__o22ai_4.pex.spice
+++ b/cells/o22ai/sky130_fd_sc_ls__o22ai_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o22ai_4.pex.spice
-* Created: Fri Aug 28 13:49:34 2020
+* Created: Wed Sep 2 11:20:26 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o22ai/sky130_fd_sc_ls__o22ai_4.pxi.spice b/cells/o22ai/sky130_fd_sc_ls__o22ai_4.pxi.spice
index b0ff058..011db75 100644
--- a/cells/o22ai/sky130_fd_sc_ls__o22ai_4.pxi.spice
+++ b/cells/o22ai/sky130_fd_sc_ls__o22ai_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o22ai_4.pxi.spice
-* Created: Fri Aug 28 13:49:34 2020
+* Created: Wed Sep 2 11:20:26 2020
*
x_PM_SKY130_FD_SC_LS__O22AI_4%A1 N_A1_M1008_g N_A1_c_125_n N_A1_M1011_g
+ N_A1_c_126_n N_A1_M1012_g N_A1_M1021_g N_A1_M1026_g N_A1_c_127_n N_A1_M1020_g
diff --git a/cells/o22ai/sky130_fd_sc_ls__o22ai_4.spice b/cells/o22ai/sky130_fd_sc_ls__o22ai_4.spice
index 6cda2e2..f14b504 100644
--- a/cells/o22ai/sky130_fd_sc_ls__o22ai_4.spice
+++ b/cells/o22ai/sky130_fd_sc_ls__o22ai_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o22ai_4.spice
-* Created: Fri Aug 28 13:49:34 2020
+* Created: Wed Sep 2 11:20:26 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o2bb2a/sky130_fd_sc_ls__o2bb2a_1.lvs.report b/cells/o2bb2a/sky130_fd_sc_ls__o2bb2a_1.lvs.report
new file mode 100644
index 0000000..48df3a1
--- /dev/null
+++ b/cells/o2bb2a/sky130_fd_sc_ls__o2bb2a_1.lvs.report
@@ -0,0 +1,470 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__o2bb2a_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__o2bb2a_1.sp ('sky130_fd_sc_ls__o2bb2a_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/o2bb2a/sky130_fd_sc_ls__o2bb2a_1.spice ('sky130_fd_sc_ls__o2bb2a_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:20:29 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__o2bb2a_1 sky130_fd_sc_ls__o2bb2a_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__o2bb2a_1
+SOURCE CELL NAME: sky130_fd_sc_ls__o2bb2a_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 14 14
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 11 11
+
+ Instances: 1 1 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1 (5 pins)
+ ------ ------
+ Total Inst: 8 8
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 4 4 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1
+ ------- ------- --------- ---------
+ Total Inst: 8 8 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1_N A2_N B2 B1 X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o2bb2a/sky130_fd_sc_ls__o2bb2a_1.pex.spice b/cells/o2bb2a/sky130_fd_sc_ls__o2bb2a_1.pex.spice
index 4facf61..af48c4d 100644
--- a/cells/o2bb2a/sky130_fd_sc_ls__o2bb2a_1.pex.spice
+++ b/cells/o2bb2a/sky130_fd_sc_ls__o2bb2a_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o2bb2a_1.pex.spice
-* Created: Fri Aug 28 13:49:51 2020
+* Created: Wed Sep 2 11:20:33 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o2bb2a/sky130_fd_sc_ls__o2bb2a_1.pxi.spice b/cells/o2bb2a/sky130_fd_sc_ls__o2bb2a_1.pxi.spice
index bca7294..77555f4 100644
--- a/cells/o2bb2a/sky130_fd_sc_ls__o2bb2a_1.pxi.spice
+++ b/cells/o2bb2a/sky130_fd_sc_ls__o2bb2a_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o2bb2a_1.pxi.spice
-* Created: Fri Aug 28 13:49:51 2020
+* Created: Wed Sep 2 11:20:33 2020
*
x_PM_SKY130_FD_SC_LS__O2BB2A_1%A_83_260# N_A_83_260#_M1005_s N_A_83_260#_M1008_d
+ N_A_83_260#_M1002_g N_A_83_260#_c_78_n N_A_83_260#_M1007_g N_A_83_260#_c_79_n
diff --git a/cells/o2bb2a/sky130_fd_sc_ls__o2bb2a_1.spice b/cells/o2bb2a/sky130_fd_sc_ls__o2bb2a_1.spice
index 7742025..897dfb7 100644
--- a/cells/o2bb2a/sky130_fd_sc_ls__o2bb2a_1.spice
+++ b/cells/o2bb2a/sky130_fd_sc_ls__o2bb2a_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o2bb2a_1.spice
-* Created: Fri Aug 28 13:49:51 2020
+* Created: Wed Sep 2 11:20:33 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o2bb2a/sky130_fd_sc_ls__o2bb2a_2.lvs.report b/cells/o2bb2a/sky130_fd_sc_ls__o2bb2a_2.lvs.report
new file mode 100644
index 0000000..9b0f199
--- /dev/null
+++ b/cells/o2bb2a/sky130_fd_sc_ls__o2bb2a_2.lvs.report
@@ -0,0 +1,475 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__o2bb2a_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__o2bb2a_2.sp ('sky130_fd_sc_ls__o2bb2a_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/o2bb2a/sky130_fd_sc_ls__o2bb2a_2.spice ('sky130_fd_sc_ls__o2bb2a_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:20:36 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__o2bb2a_2 sky130_fd_sc_ls__o2bb2a_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__o2bb2a_2
+SOURCE CELL NAME: sky130_fd_sc_ls__o2bb2a_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 14 14
+
+ Instances: 7 7 MN (4 pins)
+ 7 7 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 15 14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 11 11
+
+ Instances: 1 1 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1 (5 pins)
+ ------ ------
+ Total Inst: 8 8
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 4 4 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1
+ ------- ------- --------- ---------
+ Total Inst: 8 8 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1 B2 A2_N A1_N VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o2bb2a/sky130_fd_sc_ls__o2bb2a_2.pex.spice b/cells/o2bb2a/sky130_fd_sc_ls__o2bb2a_2.pex.spice
index 58392cb..d94c006 100644
--- a/cells/o2bb2a/sky130_fd_sc_ls__o2bb2a_2.pex.spice
+++ b/cells/o2bb2a/sky130_fd_sc_ls__o2bb2a_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o2bb2a_2.pex.spice
-* Created: Fri Aug 28 13:50:12 2020
+* Created: Wed Sep 2 11:20:39 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o2bb2a/sky130_fd_sc_ls__o2bb2a_2.pxi.spice b/cells/o2bb2a/sky130_fd_sc_ls__o2bb2a_2.pxi.spice
index 1a9ec63..676e28a 100644
--- a/cells/o2bb2a/sky130_fd_sc_ls__o2bb2a_2.pxi.spice
+++ b/cells/o2bb2a/sky130_fd_sc_ls__o2bb2a_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o2bb2a_2.pxi.spice
-* Created: Fri Aug 28 13:50:12 2020
+* Created: Wed Sep 2 11:20:39 2020
*
x_PM_SKY130_FD_SC_LS__O2BB2A_2%B1 N_B1_M1011_g N_B1_c_84_n N_B1_M1007_g B1
+ N_B1_c_85_n PM_SKY130_FD_SC_LS__O2BB2A_2%B1
diff --git a/cells/o2bb2a/sky130_fd_sc_ls__o2bb2a_2.spice b/cells/o2bb2a/sky130_fd_sc_ls__o2bb2a_2.spice
index 56947d5..7b8ee79 100644
--- a/cells/o2bb2a/sky130_fd_sc_ls__o2bb2a_2.spice
+++ b/cells/o2bb2a/sky130_fd_sc_ls__o2bb2a_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o2bb2a_2.spice
-* Created: Fri Aug 28 13:50:12 2020
+* Created: Wed Sep 2 11:20:39 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o2bb2a/sky130_fd_sc_ls__o2bb2a_4.lvs.report b/cells/o2bb2a/sky130_fd_sc_ls__o2bb2a_4.lvs.report
new file mode 100644
index 0000000..fba50f5
--- /dev/null
+++ b/cells/o2bb2a/sky130_fd_sc_ls__o2bb2a_4.lvs.report
@@ -0,0 +1,475 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__o2bb2a_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__o2bb2a_4.sp ('sky130_fd_sc_ls__o2bb2a_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/o2bb2a/sky130_fd_sc_ls__o2bb2a_4.spice ('sky130_fd_sc_ls__o2bb2a_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:20:43 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__o2bb2a_4 sky130_fd_sc_ls__o2bb2a_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__o2bb2a_4
+SOURCE CELL NAME: sky130_fd_sc_ls__o2bb2a_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 14 14
+
+ Instances: 12 12 MN (4 pins)
+ 12 12 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 25 24
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 11 11
+
+ Instances: 1 1 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1 (5 pins)
+ ------ ------
+ Total Inst: 8 8
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 4 4 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1
+ ------- ------- --------- ---------
+ Total Inst: 8 8 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 20 layout mos transistors were reduced to 8.
+ 12 mos transistors were deleted by parallel reduction.
+ 20 source mos transistors were reduced to 8.
+ 12 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1 B2 A2_N A1_N VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o2bb2a/sky130_fd_sc_ls__o2bb2a_4.pex.spice b/cells/o2bb2a/sky130_fd_sc_ls__o2bb2a_4.pex.spice
index 724df3f..0ae3e99 100644
--- a/cells/o2bb2a/sky130_fd_sc_ls__o2bb2a_4.pex.spice
+++ b/cells/o2bb2a/sky130_fd_sc_ls__o2bb2a_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o2bb2a_4.pex.spice
-* Created: Fri Aug 28 13:50:22 2020
+* Created: Wed Sep 2 11:20:46 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o2bb2a/sky130_fd_sc_ls__o2bb2a_4.pxi.spice b/cells/o2bb2a/sky130_fd_sc_ls__o2bb2a_4.pxi.spice
index b950101..d5404d1 100644
--- a/cells/o2bb2a/sky130_fd_sc_ls__o2bb2a_4.pxi.spice
+++ b/cells/o2bb2a/sky130_fd_sc_ls__o2bb2a_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o2bb2a_4.pxi.spice
-* Created: Fri Aug 28 13:50:22 2020
+* Created: Wed Sep 2 11:20:46 2020
*
x_PM_SKY130_FD_SC_LS__O2BB2A_4%B1 N_B1_M1021_g N_B1_c_128_n N_B1_c_134_n
+ N_B1_M1006_g N_B1_c_129_n N_B1_c_136_n N_B1_M1010_g N_B1_M1022_g B1 B1
diff --git a/cells/o2bb2a/sky130_fd_sc_ls__o2bb2a_4.spice b/cells/o2bb2a/sky130_fd_sc_ls__o2bb2a_4.spice
index d8bc3da..34d9121 100644
--- a/cells/o2bb2a/sky130_fd_sc_ls__o2bb2a_4.spice
+++ b/cells/o2bb2a/sky130_fd_sc_ls__o2bb2a_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o2bb2a_4.spice
-* Created: Fri Aug 28 13:50:22 2020
+* Created: Wed Sep 2 11:20:46 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o2bb2ai/sky130_fd_sc_ls__o2bb2ai_1.lvs.report b/cells/o2bb2ai/sky130_fd_sc_ls__o2bb2ai_1.lvs.report
new file mode 100644
index 0000000..3398ee8
--- /dev/null
+++ b/cells/o2bb2ai/sky130_fd_sc_ls__o2bb2ai_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__o2bb2ai_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__o2bb2ai_1.sp ('sky130_fd_sc_ls__o2bb2ai_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/o2bb2ai/sky130_fd_sc_ls__o2bb2ai_1.spice ('sky130_fd_sc_ls__o2bb2ai_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:20:50 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__o2bb2ai_1 sky130_fd_sc_ls__o2bb2ai_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__o2bb2ai_1
+SOURCE CELL NAME: sky130_fd_sc_ls__o2bb2ai_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 3 3 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1 (5 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 3 3 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1_N A2_N B2 B1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o2bb2ai/sky130_fd_sc_ls__o2bb2ai_1.pex.spice b/cells/o2bb2ai/sky130_fd_sc_ls__o2bb2ai_1.pex.spice
index 3f44e8a..a78cbc5 100644
--- a/cells/o2bb2ai/sky130_fd_sc_ls__o2bb2ai_1.pex.spice
+++ b/cells/o2bb2ai/sky130_fd_sc_ls__o2bb2ai_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o2bb2ai_1.pex.spice
-* Created: Fri Aug 28 13:50:33 2020
+* Created: Wed Sep 2 11:20:53 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o2bb2ai/sky130_fd_sc_ls__o2bb2ai_1.pxi.spice b/cells/o2bb2ai/sky130_fd_sc_ls__o2bb2ai_1.pxi.spice
index 7e16991..d197f73 100644
--- a/cells/o2bb2ai/sky130_fd_sc_ls__o2bb2ai_1.pxi.spice
+++ b/cells/o2bb2ai/sky130_fd_sc_ls__o2bb2ai_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o2bb2ai_1.pxi.spice
-* Created: Fri Aug 28 13:50:33 2020
+* Created: Wed Sep 2 11:20:53 2020
*
x_PM_SKY130_FD_SC_LS__O2BB2AI_1%A1_N N_A1_N_M1009_g N_A1_N_c_65_n N_A1_N_c_69_n
+ N_A1_N_M1008_g N_A1_N_c_70_n A1_N N_A1_N_c_67_n
diff --git a/cells/o2bb2ai/sky130_fd_sc_ls__o2bb2ai_1.spice b/cells/o2bb2ai/sky130_fd_sc_ls__o2bb2ai_1.spice
index 52a55d2..cbd5a7c 100644
--- a/cells/o2bb2ai/sky130_fd_sc_ls__o2bb2ai_1.spice
+++ b/cells/o2bb2ai/sky130_fd_sc_ls__o2bb2ai_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o2bb2ai_1.spice
-* Created: Fri Aug 28 13:50:33 2020
+* Created: Wed Sep 2 11:20:53 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o2bb2ai/sky130_fd_sc_ls__o2bb2ai_2.lvs.report b/cells/o2bb2ai/sky130_fd_sc_ls__o2bb2ai_2.lvs.report
new file mode 100644
index 0000000..d2fd5b6
--- /dev/null
+++ b/cells/o2bb2ai/sky130_fd_sc_ls__o2bb2ai_2.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__o2bb2ai_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__o2bb2ai_2.sp ('sky130_fd_sc_ls__o2bb2ai_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/o2bb2ai/sky130_fd_sc_ls__o2bb2ai_2.spice ('sky130_fd_sc_ls__o2bb2ai_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:20:56 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__o2bb2ai_2 sky130_fd_sc_ls__o2bb2ai_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__o2bb2ai_2
+SOURCE CELL NAME: sky130_fd_sc_ls__o2bb2ai_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 10 10 MN (4 pins)
+ 10 10 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 21 20
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 3 3 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1 (5 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 3 3 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 20 layout mos transistors were reduced to 10.
+ 10 mos transistors were deleted by parallel reduction.
+ 20 source mos transistors were reduced to 10.
+ 10 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1_N A2_N B1 B2 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o2bb2ai/sky130_fd_sc_ls__o2bb2ai_2.pex.spice b/cells/o2bb2ai/sky130_fd_sc_ls__o2bb2ai_2.pex.spice
index df7b004..9ac5e10 100644
--- a/cells/o2bb2ai/sky130_fd_sc_ls__o2bb2ai_2.pex.spice
+++ b/cells/o2bb2ai/sky130_fd_sc_ls__o2bb2ai_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o2bb2ai_2.pex.spice
-* Created: Fri Aug 28 13:50:42 2020
+* Created: Wed Sep 2 11:20:59 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o2bb2ai/sky130_fd_sc_ls__o2bb2ai_2.pxi.spice b/cells/o2bb2ai/sky130_fd_sc_ls__o2bb2ai_2.pxi.spice
index f2c52d9..84dae2b 100644
--- a/cells/o2bb2ai/sky130_fd_sc_ls__o2bb2ai_2.pxi.spice
+++ b/cells/o2bb2ai/sky130_fd_sc_ls__o2bb2ai_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o2bb2ai_2.pxi.spice
-* Created: Fri Aug 28 13:50:42 2020
+* Created: Wed Sep 2 11:20:59 2020
*
x_PM_SKY130_FD_SC_LS__O2BB2AI_2%A1_N N_A1_N_c_97_n N_A1_N_M1005_g N_A1_N_M1006_g
+ N_A1_N_c_99_n N_A1_N_M1014_g N_A1_N_c_100_n N_A1_N_M1008_g N_A1_N_c_101_n
diff --git a/cells/o2bb2ai/sky130_fd_sc_ls__o2bb2ai_2.spice b/cells/o2bb2ai/sky130_fd_sc_ls__o2bb2ai_2.spice
index dcf7d80..eea9f67 100644
--- a/cells/o2bb2ai/sky130_fd_sc_ls__o2bb2ai_2.spice
+++ b/cells/o2bb2ai/sky130_fd_sc_ls__o2bb2ai_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o2bb2ai_2.spice
-* Created: Fri Aug 28 13:50:42 2020
+* Created: Wed Sep 2 11:20:59 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o2bb2ai/sky130_fd_sc_ls__o2bb2ai_4.lvs.report b/cells/o2bb2ai/sky130_fd_sc_ls__o2bb2ai_4.lvs.report
new file mode 100644
index 0000000..08b9fcd
--- /dev/null
+++ b/cells/o2bb2ai/sky130_fd_sc_ls__o2bb2ai_4.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__o2bb2ai_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__o2bb2ai_4.sp ('sky130_fd_sc_ls__o2bb2ai_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/o2bb2ai/sky130_fd_sc_ls__o2bb2ai_4.spice ('sky130_fd_sc_ls__o2bb2ai_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:21:03 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__o2bb2ai_4 sky130_fd_sc_ls__o2bb2ai_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__o2bb2ai_4
+SOURCE CELL NAME: sky130_fd_sc_ls__o2bb2ai_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 20 20 MN (4 pins)
+ 20 20 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 41 40
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 3 3 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1 (5 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 3 3 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 40 layout mos transistors were reduced to 10.
+ 30 mos transistors were deleted by parallel reduction.
+ 40 source mos transistors were reduced to 10.
+ 30 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1_N A2_N B2 B1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o2bb2ai/sky130_fd_sc_ls__o2bb2ai_4.pex.spice b/cells/o2bb2ai/sky130_fd_sc_ls__o2bb2ai_4.pex.spice
index 2f73443..3c9e126 100644
--- a/cells/o2bb2ai/sky130_fd_sc_ls__o2bb2ai_4.pex.spice
+++ b/cells/o2bb2ai/sky130_fd_sc_ls__o2bb2ai_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o2bb2ai_4.pex.spice
-* Created: Fri Aug 28 13:50:59 2020
+* Created: Wed Sep 2 11:21:06 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o2bb2ai/sky130_fd_sc_ls__o2bb2ai_4.pxi.spice b/cells/o2bb2ai/sky130_fd_sc_ls__o2bb2ai_4.pxi.spice
index aef4d02..d83b7fe 100644
--- a/cells/o2bb2ai/sky130_fd_sc_ls__o2bb2ai_4.pxi.spice
+++ b/cells/o2bb2ai/sky130_fd_sc_ls__o2bb2ai_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o2bb2ai_4.pxi.spice
-* Created: Fri Aug 28 13:50:59 2020
+* Created: Wed Sep 2 11:21:06 2020
*
x_PM_SKY130_FD_SC_LS__O2BB2AI_4%A1_N N_A1_N_M1007_g N_A1_N_c_173_n
+ N_A1_N_M1000_g N_A1_N_M1031_g N_A1_N_c_174_n N_A1_N_M1010_g N_A1_N_M1032_g
diff --git a/cells/o2bb2ai/sky130_fd_sc_ls__o2bb2ai_4.spice b/cells/o2bb2ai/sky130_fd_sc_ls__o2bb2ai_4.spice
index 272ac24..0307c1e 100644
--- a/cells/o2bb2ai/sky130_fd_sc_ls__o2bb2ai_4.spice
+++ b/cells/o2bb2ai/sky130_fd_sc_ls__o2bb2ai_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o2bb2ai_4.spice
-* Created: Fri Aug 28 13:50:59 2020
+* Created: Wed Sep 2 11:21:06 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o311a/sky130_fd_sc_ls__o311a_1.lvs.report b/cells/o311a/sky130_fd_sc_ls__o311a_1.lvs.report
new file mode 100644
index 0000000..ee423ab
--- /dev/null
+++ b/cells/o311a/sky130_fd_sc_ls__o311a_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__o311a_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__o311a_1.sp ('sky130_fd_sc_ls__o311a_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/o311a/sky130_fd_sc_ls__o311a_1.spice ('sky130_fd_sc_ls__o311a_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:21:10 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__o311a_1 sky130_fd_sc_ls__o311a_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__o311a_1
+SOURCE CELL NAME: sky130_fd_sc_ls__o311a_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 15 15
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 11 11
+
+ Instances: 1 1 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 1 SMP3 (5 pins)
+ 1 1 SPMN_3_1_1 (7 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 3 3 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP3
+ 1 1 0 0 SPMN_3_1_1
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB C1 B1 A2 A3 A1 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o311a/sky130_fd_sc_ls__o311a_1.pex.spice b/cells/o311a/sky130_fd_sc_ls__o311a_1.pex.spice
index 50120eb..1744787 100644
--- a/cells/o311a/sky130_fd_sc_ls__o311a_1.pex.spice
+++ b/cells/o311a/sky130_fd_sc_ls__o311a_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o311a_1.pex.spice
-* Created: Fri Aug 28 13:51:20 2020
+* Created: Wed Sep 2 11:21:13 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o311a/sky130_fd_sc_ls__o311a_1.pxi.spice b/cells/o311a/sky130_fd_sc_ls__o311a_1.pxi.spice
index 91f0706..1ec3f3b 100644
--- a/cells/o311a/sky130_fd_sc_ls__o311a_1.pxi.spice
+++ b/cells/o311a/sky130_fd_sc_ls__o311a_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o311a_1.pxi.spice
-* Created: Fri Aug 28 13:51:20 2020
+* Created: Wed Sep 2 11:21:13 2020
*
x_PM_SKY130_FD_SC_LS__O311A_1%C1 N_C1_c_79_n N_C1_c_84_n N_C1_M1006_g
+ N_C1_M1002_g C1 N_C1_c_82_n PM_SKY130_FD_SC_LS__O311A_1%C1
diff --git a/cells/o311a/sky130_fd_sc_ls__o311a_1.spice b/cells/o311a/sky130_fd_sc_ls__o311a_1.spice
index d172b71..3ec4436 100644
--- a/cells/o311a/sky130_fd_sc_ls__o311a_1.spice
+++ b/cells/o311a/sky130_fd_sc_ls__o311a_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o311a_1.spice
-* Created: Fri Aug 28 13:51:20 2020
+* Created: Wed Sep 2 11:21:13 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o311a/sky130_fd_sc_ls__o311a_2.lvs.report b/cells/o311a/sky130_fd_sc_ls__o311a_2.lvs.report
new file mode 100644
index 0000000..067af67
--- /dev/null
+++ b/cells/o311a/sky130_fd_sc_ls__o311a_2.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__o311a_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__o311a_2.sp ('sky130_fd_sc_ls__o311a_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/o311a/sky130_fd_sc_ls__o311a_2.spice ('sky130_fd_sc_ls__o311a_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:21:16 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__o311a_2 sky130_fd_sc_ls__o311a_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__o311a_2
+SOURCE CELL NAME: sky130_fd_sc_ls__o311a_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 15 15
+
+ Instances: 7 7 MN (4 pins)
+ 7 7 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 15 14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 11 11
+
+ Instances: 1 1 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 1 SMP3 (5 pins)
+ 1 1 SPMN_3_1_1 (7 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 3 3 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP3
+ 1 1 0 0 SPMN_3_1_1
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB C1 B1 A3 A2 A1 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o311a/sky130_fd_sc_ls__o311a_2.pex.spice b/cells/o311a/sky130_fd_sc_ls__o311a_2.pex.spice
index 1984f40..ce338b8 100644
--- a/cells/o311a/sky130_fd_sc_ls__o311a_2.pex.spice
+++ b/cells/o311a/sky130_fd_sc_ls__o311a_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o311a_2.pex.spice
-* Created: Fri Aug 28 13:51:31 2020
+* Created: Wed Sep 2 11:21:20 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o311a/sky130_fd_sc_ls__o311a_2.pxi.spice b/cells/o311a/sky130_fd_sc_ls__o311a_2.pxi.spice
index 2204e29..d8f43c5 100644
--- a/cells/o311a/sky130_fd_sc_ls__o311a_2.pxi.spice
+++ b/cells/o311a/sky130_fd_sc_ls__o311a_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o311a_2.pxi.spice
-* Created: Fri Aug 28 13:51:31 2020
+* Created: Wed Sep 2 11:21:20 2020
*
x_PM_SKY130_FD_SC_LS__O311A_2%C1 N_C1_M1000_g N_C1_c_72_n N_C1_M1006_g
+ N_C1_c_69_n N_C1_c_70_n C1 PM_SKY130_FD_SC_LS__O311A_2%C1
diff --git a/cells/o311a/sky130_fd_sc_ls__o311a_2.spice b/cells/o311a/sky130_fd_sc_ls__o311a_2.spice
index 761ce47..82d619c 100644
--- a/cells/o311a/sky130_fd_sc_ls__o311a_2.spice
+++ b/cells/o311a/sky130_fd_sc_ls__o311a_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o311a_2.spice
-* Created: Fri Aug 28 13:51:31 2020
+* Created: Wed Sep 2 11:21:20 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o311a/sky130_fd_sc_ls__o311a_4.lvs.report b/cells/o311a/sky130_fd_sc_ls__o311a_4.lvs.report
new file mode 100644
index 0000000..4a9d92e
--- /dev/null
+++ b/cells/o311a/sky130_fd_sc_ls__o311a_4.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__o311a_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__o311a_4.sp ('sky130_fd_sc_ls__o311a_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/o311a/sky130_fd_sc_ls__o311a_4.spice ('sky130_fd_sc_ls__o311a_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:21:23 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__o311a_4 sky130_fd_sc_ls__o311a_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__o311a_4
+SOURCE CELL NAME: sky130_fd_sc_ls__o311a_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 15 15
+
+ Instances: 14 14 MN (4 pins)
+ 14 14 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 29 28
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 11 11
+
+ Instances: 1 1 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 1 SMP3 (5 pins)
+ 1 1 SPMN_3_1_1 (7 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 3 3 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP3
+ 1 1 0 0 SPMN_3_1_1
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 28 layout mos transistors were reduced to 12.
+ 16 mos transistors were deleted by parallel reduction.
+ 28 source mos transistors were reduced to 12.
+ 16 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1 C1 A3 A2 A1 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o311a/sky130_fd_sc_ls__o311a_4.pex.spice b/cells/o311a/sky130_fd_sc_ls__o311a_4.pex.spice
index d96cdbf..7dc50c2 100644
--- a/cells/o311a/sky130_fd_sc_ls__o311a_4.pex.spice
+++ b/cells/o311a/sky130_fd_sc_ls__o311a_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o311a_4.pex.spice
-* Created: Fri Aug 28 13:51:41 2020
+* Created: Wed Sep 2 11:21:27 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o311a/sky130_fd_sc_ls__o311a_4.pxi.spice b/cells/o311a/sky130_fd_sc_ls__o311a_4.pxi.spice
index 2e94145..1534415 100644
--- a/cells/o311a/sky130_fd_sc_ls__o311a_4.pxi.spice
+++ b/cells/o311a/sky130_fd_sc_ls__o311a_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o311a_4.pxi.spice
-* Created: Fri Aug 28 13:51:41 2020
+* Created: Wed Sep 2 11:21:27 2020
*
x_PM_SKY130_FD_SC_LS__O311A_4%A_83_244# N_A_83_244#_M1008_d N_A_83_244#_M1011_s
+ N_A_83_244#_M1015_d N_A_83_244#_M1000_d N_A_83_244#_c_158_n
diff --git a/cells/o311a/sky130_fd_sc_ls__o311a_4.spice b/cells/o311a/sky130_fd_sc_ls__o311a_4.spice
index 2e193f4..53af2ed 100644
--- a/cells/o311a/sky130_fd_sc_ls__o311a_4.spice
+++ b/cells/o311a/sky130_fd_sc_ls__o311a_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o311a_4.spice
-* Created: Fri Aug 28 13:51:41 2020
+* Created: Wed Sep 2 11:21:27 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o311ai/sky130_fd_sc_ls__o311ai_1.lvs.report b/cells/o311ai/sky130_fd_sc_ls__o311ai_1.lvs.report
new file mode 100644
index 0000000..4faa93a
--- /dev/null
+++ b/cells/o311ai/sky130_fd_sc_ls__o311ai_1.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__o311ai_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__o311ai_1.sp ('sky130_fd_sc_ls__o311ai_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/o311ai/sky130_fd_sc_ls__o311ai_1.spice ('sky130_fd_sc_ls__o311ai_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:21:31 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__o311ai_1 sky130_fd_sc_ls__o311ai_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__o311ai_1
+SOURCE CELL NAME: sky130_fd_sc_ls__o311ai_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 14 14
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 10 10
+
+ Instances: 2 2 MP (4 pins)
+ 1 1 SMP3 (5 pins)
+ 1 1 SPMN_3_1_1 (7 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP3
+ 1 1 0 0 SPMN_3_1_1
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1 A2 A3 B1 C1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o311ai/sky130_fd_sc_ls__o311ai_1.pex.spice b/cells/o311ai/sky130_fd_sc_ls__o311ai_1.pex.spice
index ee959fd..dd9b3a9 100644
--- a/cells/o311ai/sky130_fd_sc_ls__o311ai_1.pex.spice
+++ b/cells/o311ai/sky130_fd_sc_ls__o311ai_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o311ai_1.pex.spice
-* Created: Fri Aug 28 13:51:51 2020
+* Created: Wed Sep 2 11:21:34 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o311ai/sky130_fd_sc_ls__o311ai_1.pxi.spice b/cells/o311ai/sky130_fd_sc_ls__o311ai_1.pxi.spice
index f41192b..0cba859 100644
--- a/cells/o311ai/sky130_fd_sc_ls__o311ai_1.pxi.spice
+++ b/cells/o311ai/sky130_fd_sc_ls__o311ai_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o311ai_1.pxi.spice
-* Created: Fri Aug 28 13:51:51 2020
+* Created: Wed Sep 2 11:21:34 2020
*
x_PM_SKY130_FD_SC_LS__O311AI_1%A1 N_A1_M1002_g N_A1_c_50_n N_A1_M1003_g A1
+ N_A1_c_51_n PM_SKY130_FD_SC_LS__O311AI_1%A1
diff --git a/cells/o311ai/sky130_fd_sc_ls__o311ai_1.spice b/cells/o311ai/sky130_fd_sc_ls__o311ai_1.spice
index 0ed3086..e704139 100644
--- a/cells/o311ai/sky130_fd_sc_ls__o311ai_1.spice
+++ b/cells/o311ai/sky130_fd_sc_ls__o311ai_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o311ai_1.spice
-* Created: Fri Aug 28 13:51:51 2020
+* Created: Wed Sep 2 11:21:34 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o311ai/sky130_fd_sc_ls__o311ai_2.lvs.report b/cells/o311ai/sky130_fd_sc_ls__o311ai_2.lvs.report
new file mode 100644
index 0000000..5883244
--- /dev/null
+++ b/cells/o311ai/sky130_fd_sc_ls__o311ai_2.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__o311ai_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__o311ai_2.sp ('sky130_fd_sc_ls__o311ai_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/o311ai/sky130_fd_sc_ls__o311ai_2.spice ('sky130_fd_sc_ls__o311ai_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:21:38 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__o311ai_2 sky130_fd_sc_ls__o311ai_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__o311ai_2
+SOURCE CELL NAME: sky130_fd_sc_ls__o311ai_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 14 14
+
+ Instances: 10 10 MN (4 pins)
+ 10 10 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 21 20
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 10 10
+
+ Instances: 2 2 MP (4 pins)
+ 1 1 SMP3 (5 pins)
+ 1 1 SPMN_3_1_1 (7 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP3
+ 1 1 0 0 SPMN_3_1_1
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 20 layout mos transistors were reduced to 10.
+ 10 mos transistors were deleted by parallel reduction.
+ 20 source mos transistors were reduced to 10.
+ 10 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1 A2 A3 B1 C1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o311ai/sky130_fd_sc_ls__o311ai_2.pex.spice b/cells/o311ai/sky130_fd_sc_ls__o311ai_2.pex.spice
index 758783e..f169320 100644
--- a/cells/o311ai/sky130_fd_sc_ls__o311ai_2.pex.spice
+++ b/cells/o311ai/sky130_fd_sc_ls__o311ai_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o311ai_2.pex.spice
-* Created: Fri Aug 28 13:52:08 2020
+* Created: Wed Sep 2 11:21:42 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o311ai/sky130_fd_sc_ls__o311ai_2.pxi.spice b/cells/o311ai/sky130_fd_sc_ls__o311ai_2.pxi.spice
index 00d4dfc..ce6ff9c 100644
--- a/cells/o311ai/sky130_fd_sc_ls__o311ai_2.pxi.spice
+++ b/cells/o311ai/sky130_fd_sc_ls__o311ai_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o311ai_2.pxi.spice
-* Created: Fri Aug 28 13:52:08 2020
+* Created: Wed Sep 2 11:21:42 2020
*
x_PM_SKY130_FD_SC_LS__O311AI_2%A1 N_A1_M1016_g N_A1_c_103_n N_A1_M1003_g
+ N_A1_c_104_n N_A1_M1009_g N_A1_M1018_g A1 A1 N_A1_c_102_n
diff --git a/cells/o311ai/sky130_fd_sc_ls__o311ai_2.spice b/cells/o311ai/sky130_fd_sc_ls__o311ai_2.spice
index 40caca6..5a65945 100644
--- a/cells/o311ai/sky130_fd_sc_ls__o311ai_2.spice
+++ b/cells/o311ai/sky130_fd_sc_ls__o311ai_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o311ai_2.spice
-* Created: Fri Aug 28 13:52:08 2020
+* Created: Wed Sep 2 11:21:42 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o311ai/sky130_fd_sc_ls__o311ai_4.lvs.report b/cells/o311ai/sky130_fd_sc_ls__o311ai_4.lvs.report
new file mode 100644
index 0000000..d5fa3da
--- /dev/null
+++ b/cells/o311ai/sky130_fd_sc_ls__o311ai_4.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__o311ai_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__o311ai_4.sp ('sky130_fd_sc_ls__o311ai_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/o311ai/sky130_fd_sc_ls__o311ai_4.spice ('sky130_fd_sc_ls__o311ai_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:21:46 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__o311ai_4 sky130_fd_sc_ls__o311ai_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__o311ai_4
+SOURCE CELL NAME: sky130_fd_sc_ls__o311ai_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 14 14
+
+ Instances: 20 20 MN (4 pins)
+ 16 16 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 37 36
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 10 10
+
+ Instances: 2 2 MP (4 pins)
+ 1 1 SMP3 (5 pins)
+ 1 1 SPMN_3_1_1 (7 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP3
+ 1 1 0 0 SPMN_3_1_1
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 36 layout mos transistors were reduced to 10.
+ 26 mos transistors were deleted by parallel reduction.
+ 36 source mos transistors were reduced to 10.
+ 26 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB C1 B1 A3 A2 A1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o311ai/sky130_fd_sc_ls__o311ai_4.pex.spice b/cells/o311ai/sky130_fd_sc_ls__o311ai_4.pex.spice
index 26000e4..c7cf86e 100644
--- a/cells/o311ai/sky130_fd_sc_ls__o311ai_4.pex.spice
+++ b/cells/o311ai/sky130_fd_sc_ls__o311ai_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o311ai_4.pex.spice
-* Created: Fri Aug 28 13:52:29 2020
+* Created: Wed Sep 2 11:21:50 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o311ai/sky130_fd_sc_ls__o311ai_4.pxi.spice b/cells/o311ai/sky130_fd_sc_ls__o311ai_4.pxi.spice
index a871996..1d82f85 100644
--- a/cells/o311ai/sky130_fd_sc_ls__o311ai_4.pxi.spice
+++ b/cells/o311ai/sky130_fd_sc_ls__o311ai_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o311ai_4.pxi.spice
-* Created: Fri Aug 28 13:52:29 2020
+* Created: Wed Sep 2 11:21:50 2020
*
x_PM_SKY130_FD_SC_LS__O311AI_4%C1 N_C1_c_146_n N_C1_M1003_g N_C1_c_153_n
+ N_C1_M1011_g N_C1_c_147_n N_C1_M1018_g N_C1_c_154_n N_C1_M1022_g N_C1_c_148_n
diff --git a/cells/o311ai/sky130_fd_sc_ls__o311ai_4.spice b/cells/o311ai/sky130_fd_sc_ls__o311ai_4.spice
index 0f1c4ff..fdb02f6 100644
--- a/cells/o311ai/sky130_fd_sc_ls__o311ai_4.spice
+++ b/cells/o311ai/sky130_fd_sc_ls__o311ai_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o311ai_4.spice
-* Created: Fri Aug 28 13:52:29 2020
+* Created: Wed Sep 2 11:21:50 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o31a/sky130_fd_sc_ls__o31a_1.lvs.report b/cells/o31a/sky130_fd_sc_ls__o31a_1.lvs.report
new file mode 100644
index 0000000..9a716fc
--- /dev/null
+++ b/cells/o31a/sky130_fd_sc_ls__o31a_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__o31a_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__o31a_1.sp ('sky130_fd_sc_ls__o31a_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/o31a/sky130_fd_sc_ls__o31a_1.spice ('sky130_fd_sc_ls__o31a_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:21:54 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__o31a_1 sky130_fd_sc_ls__o31a_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__o31a_1
+SOURCE CELL NAME: sky130_fd_sc_ls__o31a_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 1 1 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 1 SMP3 (5 pins)
+ 1 1 SPMN_3_1 (6 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP3
+ 1 1 0 0 SPMN_3_1
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1 A2 A3 B1 X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o31a/sky130_fd_sc_ls__o31a_1.pex.spice b/cells/o31a/sky130_fd_sc_ls__o31a_1.pex.spice
index 3d4a1bc..46ce517 100644
--- a/cells/o31a/sky130_fd_sc_ls__o31a_1.pex.spice
+++ b/cells/o31a/sky130_fd_sc_ls__o31a_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o31a_1.pex.spice
-* Created: Fri Aug 28 13:52:40 2020
+* Created: Wed Sep 2 11:21:57 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o31a/sky130_fd_sc_ls__o31a_1.pxi.spice b/cells/o31a/sky130_fd_sc_ls__o31a_1.pxi.spice
index 3996303..7242d7b 100644
--- a/cells/o31a/sky130_fd_sc_ls__o31a_1.pxi.spice
+++ b/cells/o31a/sky130_fd_sc_ls__o31a_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o31a_1.pxi.spice
-* Created: Fri Aug 28 13:52:40 2020
+* Created: Wed Sep 2 11:21:57 2020
*
x_PM_SKY130_FD_SC_LS__O31A_1%A_84_48# N_A_84_48#_M1002_d N_A_84_48#_M1006_d
+ N_A_84_48#_M1008_g N_A_84_48#_c_61_n N_A_84_48#_M1004_g N_A_84_48#_c_62_n
diff --git a/cells/o31a/sky130_fd_sc_ls__o31a_1.spice b/cells/o31a/sky130_fd_sc_ls__o31a_1.spice
index 75d7387..4a02033 100644
--- a/cells/o31a/sky130_fd_sc_ls__o31a_1.spice
+++ b/cells/o31a/sky130_fd_sc_ls__o31a_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o31a_1.spice
-* Created: Fri Aug 28 13:52:40 2020
+* Created: Wed Sep 2 11:21:57 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o31a/sky130_fd_sc_ls__o31a_2.lvs.report b/cells/o31a/sky130_fd_sc_ls__o31a_2.lvs.report
new file mode 100644
index 0000000..bd05683
--- /dev/null
+++ b/cells/o31a/sky130_fd_sc_ls__o31a_2.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__o31a_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__o31a_2.sp ('sky130_fd_sc_ls__o31a_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/o31a/sky130_fd_sc_ls__o31a_2.spice ('sky130_fd_sc_ls__o31a_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:22:01 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__o31a_2 sky130_fd_sc_ls__o31a_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__o31a_2
+SOURCE CELL NAME: sky130_fd_sc_ls__o31a_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 1 1 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 1 SMP3 (5 pins)
+ 1 1 SPMN_3_1 (6 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP3
+ 1 1 0 0 SPMN_3_1
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1 A2 A3 B1 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o31a/sky130_fd_sc_ls__o31a_2.pex.spice b/cells/o31a/sky130_fd_sc_ls__o31a_2.pex.spice
index 5bb29a8..ebfafb4 100644
--- a/cells/o31a/sky130_fd_sc_ls__o31a_2.pex.spice
+++ b/cells/o31a/sky130_fd_sc_ls__o31a_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o31a_2.pex.spice
-* Created: Fri Aug 28 13:52:50 2020
+* Created: Wed Sep 2 11:22:05 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o31a/sky130_fd_sc_ls__o31a_2.pxi.spice b/cells/o31a/sky130_fd_sc_ls__o31a_2.pxi.spice
index a7ee163..d538f66 100644
--- a/cells/o31a/sky130_fd_sc_ls__o31a_2.pxi.spice
+++ b/cells/o31a/sky130_fd_sc_ls__o31a_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o31a_2.pxi.spice
-* Created: Fri Aug 28 13:52:50 2020
+* Created: Wed Sep 2 11:22:05 2020
*
x_PM_SKY130_FD_SC_LS__O31A_2%A_55_264# N_A_55_264#_M1002_d N_A_55_264#_M1011_d
+ N_A_55_264#_c_69_n N_A_55_264#_M1007_g N_A_55_264#_M1005_g N_A_55_264#_c_71_n
diff --git a/cells/o31a/sky130_fd_sc_ls__o31a_2.spice b/cells/o31a/sky130_fd_sc_ls__o31a_2.spice
index bbc46e4..b802d04 100644
--- a/cells/o31a/sky130_fd_sc_ls__o31a_2.spice
+++ b/cells/o31a/sky130_fd_sc_ls__o31a_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o31a_2.spice
-* Created: Fri Aug 28 13:52:50 2020
+* Created: Wed Sep 2 11:22:05 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o31a/sky130_fd_sc_ls__o31a_4.lvs.report b/cells/o31a/sky130_fd_sc_ls__o31a_4.lvs.report
new file mode 100644
index 0000000..6327aa4
--- /dev/null
+++ b/cells/o31a/sky130_fd_sc_ls__o31a_4.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__o31a_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__o31a_4.sp ('sky130_fd_sc_ls__o31a_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/o31a/sky130_fd_sc_ls__o31a_4.spice ('sky130_fd_sc_ls__o31a_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:22:09 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__o31a_4 sky130_fd_sc_ls__o31a_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__o31a_4
+SOURCE CELL NAME: sky130_fd_sc_ls__o31a_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 12 12 MN (4 pins)
+ 12 12 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 25 24
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 1 1 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 1 SMP3 (5 pins)
+ 1 1 SPMN_3_1 (6 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP3
+ 1 1 0 0 SPMN_3_1
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 24 layout mos transistors were reduced to 10.
+ 14 mos transistors were deleted by parallel reduction.
+ 24 source mos transistors were reduced to 10.
+ 14 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1 A3 A1 A2 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o31a/sky130_fd_sc_ls__o31a_4.pex.spice b/cells/o31a/sky130_fd_sc_ls__o31a_4.pex.spice
index 3883b29..68f2557 100644
--- a/cells/o31a/sky130_fd_sc_ls__o31a_4.pex.spice
+++ b/cells/o31a/sky130_fd_sc_ls__o31a_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o31a_4.pex.spice
-* Created: Fri Aug 28 13:53:00 2020
+* Created: Wed Sep 2 11:22:12 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o31a/sky130_fd_sc_ls__o31a_4.pxi.spice b/cells/o31a/sky130_fd_sc_ls__o31a_4.pxi.spice
index a80dd5e..502bf2e 100644
--- a/cells/o31a/sky130_fd_sc_ls__o31a_4.pxi.spice
+++ b/cells/o31a/sky130_fd_sc_ls__o31a_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o31a_4.pxi.spice
-* Created: Fri Aug 28 13:53:00 2020
+* Created: Wed Sep 2 11:22:12 2020
*
x_PM_SKY130_FD_SC_LS__O31A_4%A_86_260# N_A_86_260#_M1008_s N_A_86_260#_M1006_d
+ N_A_86_260#_M1001_s N_A_86_260#_c_140_n N_A_86_260#_M1003_g
diff --git a/cells/o31a/sky130_fd_sc_ls__o31a_4.spice b/cells/o31a/sky130_fd_sc_ls__o31a_4.spice
index 7f754a9..5740ee8 100644
--- a/cells/o31a/sky130_fd_sc_ls__o31a_4.spice
+++ b/cells/o31a/sky130_fd_sc_ls__o31a_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o31a_4.spice
-* Created: Fri Aug 28 13:53:00 2020
+* Created: Wed Sep 2 11:22:12 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o31ai/sky130_fd_sc_ls__o31ai_1.lvs.report b/cells/o31ai/sky130_fd_sc_ls__o31ai_1.lvs.report
new file mode 100644
index 0000000..74f5cd1
--- /dev/null
+++ b/cells/o31ai/sky130_fd_sc_ls__o31ai_1.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__o31ai_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__o31ai_1.sp ('sky130_fd_sc_ls__o31ai_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/o31ai/sky130_fd_sc_ls__o31ai_1.spice ('sky130_fd_sc_ls__o31ai_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:22:16 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__o31ai_1 sky130_fd_sc_ls__o31ai_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__o31ai_1
+SOURCE CELL NAME: sky130_fd_sc_ls__o31ai_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 12 12
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 9 9
+
+ Instances: 1 1 MP (4 pins)
+ 1 1 SMP3 (5 pins)
+ 1 1 SPMN_3_1 (6 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP3
+ 1 1 0 0 SPMN_3_1
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1 A2 A3 B1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o31ai/sky130_fd_sc_ls__o31ai_1.pex.spice b/cells/o31ai/sky130_fd_sc_ls__o31ai_1.pex.spice
index 326f405..4bd59d0 100644
--- a/cells/o31ai/sky130_fd_sc_ls__o31ai_1.pex.spice
+++ b/cells/o31ai/sky130_fd_sc_ls__o31ai_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o31ai_1.pex.spice
-* Created: Fri Aug 28 13:53:17 2020
+* Created: Wed Sep 2 11:22:19 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o31ai/sky130_fd_sc_ls__o31ai_1.pxi.spice b/cells/o31ai/sky130_fd_sc_ls__o31ai_1.pxi.spice
index 1888567..a7bfe14 100644
--- a/cells/o31ai/sky130_fd_sc_ls__o31ai_1.pxi.spice
+++ b/cells/o31ai/sky130_fd_sc_ls__o31ai_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o31ai_1.pxi.spice
-* Created: Fri Aug 28 13:53:17 2020
+* Created: Wed Sep 2 11:22:19 2020
*
x_PM_SKY130_FD_SC_LS__O31AI_1%A1 N_A1_c_43_n N_A1_M1005_g N_A1_c_44_n
+ N_A1_M1001_g A1 PM_SKY130_FD_SC_LS__O31AI_1%A1
diff --git a/cells/o31ai/sky130_fd_sc_ls__o31ai_1.spice b/cells/o31ai/sky130_fd_sc_ls__o31ai_1.spice
index 73479b7..342c885 100644
--- a/cells/o31ai/sky130_fd_sc_ls__o31ai_1.spice
+++ b/cells/o31ai/sky130_fd_sc_ls__o31ai_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o31ai_1.spice
-* Created: Fri Aug 28 13:53:17 2020
+* Created: Wed Sep 2 11:22:19 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o31ai/sky130_fd_sc_ls__o31ai_2.lvs.report b/cells/o31ai/sky130_fd_sc_ls__o31ai_2.lvs.report
new file mode 100644
index 0000000..22dcd2d
--- /dev/null
+++ b/cells/o31ai/sky130_fd_sc_ls__o31ai_2.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__o31ai_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__o31ai_2.sp ('sky130_fd_sc_ls__o31ai_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/o31ai/sky130_fd_sc_ls__o31ai_2.spice ('sky130_fd_sc_ls__o31ai_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:22:23 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__o31ai_2 sky130_fd_sc_ls__o31ai_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__o31ai_2
+SOURCE CELL NAME: sky130_fd_sc_ls__o31ai_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 12 12
+
+ Instances: 8 8 MN (4 pins)
+ 8 8 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 17 16
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 9 9
+
+ Instances: 1 1 MP (4 pins)
+ 1 1 SMP3 (5 pins)
+ 1 1 SPMN_3_1 (6 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP3
+ 1 1 0 0 SPMN_3_1
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 16 layout mos transistors were reduced to 8.
+ 8 mos transistors were deleted by parallel reduction.
+ 16 source mos transistors were reduced to 8.
+ 8 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1 A2 A3 B1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o31ai/sky130_fd_sc_ls__o31ai_2.pex.spice b/cells/o31ai/sky130_fd_sc_ls__o31ai_2.pex.spice
index d513557..0cbb825 100644
--- a/cells/o31ai/sky130_fd_sc_ls__o31ai_2.pex.spice
+++ b/cells/o31ai/sky130_fd_sc_ls__o31ai_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o31ai_2.pex.spice
-* Created: Fri Aug 28 13:53:37 2020
+* Created: Wed Sep 2 11:22:26 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o31ai/sky130_fd_sc_ls__o31ai_2.pxi.spice b/cells/o31ai/sky130_fd_sc_ls__o31ai_2.pxi.spice
index 928f36c..23df4a0 100644
--- a/cells/o31ai/sky130_fd_sc_ls__o31ai_2.pxi.spice
+++ b/cells/o31ai/sky130_fd_sc_ls__o31ai_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o31ai_2.pxi.spice
-* Created: Fri Aug 28 13:53:37 2020
+* Created: Wed Sep 2 11:22:26 2020
*
x_PM_SKY130_FD_SC_LS__O31AI_2%A1 N_A1_M1012_g N_A1_c_85_n N_A1_M1005_g
+ N_A1_c_86_n N_A1_M1006_g N_A1_c_82_n N_A1_M1014_g A1 A1 A1 N_A1_c_84_n
diff --git a/cells/o31ai/sky130_fd_sc_ls__o31ai_2.spice b/cells/o31ai/sky130_fd_sc_ls__o31ai_2.spice
index 6dfecb6..bd461d9 100644
--- a/cells/o31ai/sky130_fd_sc_ls__o31ai_2.spice
+++ b/cells/o31ai/sky130_fd_sc_ls__o31ai_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o31ai_2.spice
-* Created: Fri Aug 28 13:53:37 2020
+* Created: Wed Sep 2 11:22:26 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o31ai/sky130_fd_sc_ls__o31ai_4.lvs.report b/cells/o31ai/sky130_fd_sc_ls__o31ai_4.lvs.report
new file mode 100644
index 0000000..19b3524
--- /dev/null
+++ b/cells/o31ai/sky130_fd_sc_ls__o31ai_4.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__o31ai_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__o31ai_4.sp ('sky130_fd_sc_ls__o31ai_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/o31ai/sky130_fd_sc_ls__o31ai_4.spice ('sky130_fd_sc_ls__o31ai_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:22:30 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__o31ai_4 sky130_fd_sc_ls__o31ai_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__o31ai_4
+SOURCE CELL NAME: sky130_fd_sc_ls__o31ai_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 12 12
+
+ Instances: 16 16 MN (4 pins)
+ 14 14 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 31 30
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 9 9
+
+ Instances: 1 1 MP (4 pins)
+ 1 1 SMP3 (5 pins)
+ 1 1 SPMN_3_1 (6 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP3
+ 1 1 0 0 SPMN_3_1
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 30 layout mos transistors were reduced to 8.
+ 22 mos transistors were deleted by parallel reduction.
+ 30 source mos transistors were reduced to 8.
+ 22 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1 A2 A3 B1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o31ai/sky130_fd_sc_ls__o31ai_4.pex.spice b/cells/o31ai/sky130_fd_sc_ls__o31ai_4.pex.spice
index 42edcfc..3e269b3 100644
--- a/cells/o31ai/sky130_fd_sc_ls__o31ai_4.pex.spice
+++ b/cells/o31ai/sky130_fd_sc_ls__o31ai_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o31ai_4.pex.spice
-* Created: Fri Aug 28 13:53:48 2020
+* Created: Wed Sep 2 11:22:33 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o31ai/sky130_fd_sc_ls__o31ai_4.pxi.spice b/cells/o31ai/sky130_fd_sc_ls__o31ai_4.pxi.spice
index 0f33c72..9de3f95 100644
--- a/cells/o31ai/sky130_fd_sc_ls__o31ai_4.pxi.spice
+++ b/cells/o31ai/sky130_fd_sc_ls__o31ai_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o31ai_4.pxi.spice
-* Created: Fri Aug 28 13:53:48 2020
+* Created: Wed Sep 2 11:22:33 2020
*
x_PM_SKY130_FD_SC_LS__O31AI_4%A1 N_A1_M1003_g N_A1_c_140_n N_A1_M1015_g
+ N_A1_c_141_n N_A1_M1016_g N_A1_M1018_g N_A1_c_142_n N_A1_M1020_g N_A1_M1026_g
diff --git a/cells/o31ai/sky130_fd_sc_ls__o31ai_4.spice b/cells/o31ai/sky130_fd_sc_ls__o31ai_4.spice
index e3cf0af..1815b6a 100644
--- a/cells/o31ai/sky130_fd_sc_ls__o31ai_4.spice
+++ b/cells/o31ai/sky130_fd_sc_ls__o31ai_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o31ai_4.spice
-* Created: Fri Aug 28 13:53:48 2020
+* Created: Wed Sep 2 11:22:33 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o32a/sky130_fd_sc_ls__o32a_1.lvs.report b/cells/o32a/sky130_fd_sc_ls__o32a_1.lvs.report
new file mode 100644
index 0000000..103b9fd
--- /dev/null
+++ b/cells/o32a/sky130_fd_sc_ls__o32a_1.lvs.report
@@ -0,0 +1,470 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__o32a_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__o32a_1.sp ('sky130_fd_sc_ls__o32a_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/o32a/sky130_fd_sc_ls__o32a_1.spice ('sky130_fd_sc_ls__o32a_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:22:37 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__o32a_1 sky130_fd_sc_ls__o32a_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__o32a_1
+SOURCE CELL NAME: sky130_fd_sc_ls__o32a_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 15 15
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 11 11
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SMP3 (5 pins)
+ 1 1 SPMN_3_2 (7 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ 1 1 0 0 SMP3
+ 1 1 0 0 SPMN_3_2
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1 A2 A3 B2 B1 X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o32a/sky130_fd_sc_ls__o32a_1.pex.spice b/cells/o32a/sky130_fd_sc_ls__o32a_1.pex.spice
index bbfaa91..b00be36 100644
--- a/cells/o32a/sky130_fd_sc_ls__o32a_1.pex.spice
+++ b/cells/o32a/sky130_fd_sc_ls__o32a_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o32a_1.pex.spice
-* Created: Fri Aug 28 13:53:58 2020
+* Created: Wed Sep 2 11:22:40 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o32a/sky130_fd_sc_ls__o32a_1.pxi.spice b/cells/o32a/sky130_fd_sc_ls__o32a_1.pxi.spice
index e557e43..46e2fc1 100644
--- a/cells/o32a/sky130_fd_sc_ls__o32a_1.pxi.spice
+++ b/cells/o32a/sky130_fd_sc_ls__o32a_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o32a_1.pxi.spice
-* Created: Fri Aug 28 13:53:58 2020
+* Created: Wed Sep 2 11:22:40 2020
*
x_PM_SKY130_FD_SC_LS__O32A_1%A_83_264# N_A_83_264#_M1002_d N_A_83_264#_M1011_d
+ N_A_83_264#_c_68_n N_A_83_264#_M1007_g N_A_83_264#_M1004_g N_A_83_264#_c_70_n
diff --git a/cells/o32a/sky130_fd_sc_ls__o32a_1.spice b/cells/o32a/sky130_fd_sc_ls__o32a_1.spice
index b51ab70..38a2b05 100644
--- a/cells/o32a/sky130_fd_sc_ls__o32a_1.spice
+++ b/cells/o32a/sky130_fd_sc_ls__o32a_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o32a_1.spice
-* Created: Fri Aug 28 13:53:58 2020
+* Created: Wed Sep 2 11:22:40 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o32a/sky130_fd_sc_ls__o32a_2.lvs.report b/cells/o32a/sky130_fd_sc_ls__o32a_2.lvs.report
new file mode 100644
index 0000000..26391dd
--- /dev/null
+++ b/cells/o32a/sky130_fd_sc_ls__o32a_2.lvs.report
@@ -0,0 +1,475 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__o32a_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__o32a_2.sp ('sky130_fd_sc_ls__o32a_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/o32a/sky130_fd_sc_ls__o32a_2.spice ('sky130_fd_sc_ls__o32a_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:22:44 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__o32a_2 sky130_fd_sc_ls__o32a_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__o32a_2
+SOURCE CELL NAME: sky130_fd_sc_ls__o32a_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 15 15
+
+ Instances: 7 7 MN (4 pins)
+ 7 7 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 15 14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 11 11
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SMP3 (5 pins)
+ 1 1 SPMN_3_2 (7 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ 1 1 0 0 SMP3
+ 1 1 0 0 SPMN_3_2
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1 A2 A3 B2 B1 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o32a/sky130_fd_sc_ls__o32a_2.pex.spice b/cells/o32a/sky130_fd_sc_ls__o32a_2.pex.spice
index 9b4e781..994c0e5 100644
--- a/cells/o32a/sky130_fd_sc_ls__o32a_2.pex.spice
+++ b/cells/o32a/sky130_fd_sc_ls__o32a_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o32a_2.pex.spice
-* Created: Fri Aug 28 13:54:08 2020
+* Created: Wed Sep 2 11:22:47 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o32a/sky130_fd_sc_ls__o32a_2.pxi.spice b/cells/o32a/sky130_fd_sc_ls__o32a_2.pxi.spice
index d58bfb9..ad4096a 100644
--- a/cells/o32a/sky130_fd_sc_ls__o32a_2.pxi.spice
+++ b/cells/o32a/sky130_fd_sc_ls__o32a_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o32a_2.pxi.spice
-* Created: Fri Aug 28 13:54:08 2020
+* Created: Wed Sep 2 11:22:47 2020
*
x_PM_SKY130_FD_SC_LS__O32A_2%A_83_264# N_A_83_264#_M1002_d N_A_83_264#_M1004_d
+ N_A_83_264#_c_80_n N_A_83_264#_c_88_n N_A_83_264#_M1008_g N_A_83_264#_M1007_g
diff --git a/cells/o32a/sky130_fd_sc_ls__o32a_2.spice b/cells/o32a/sky130_fd_sc_ls__o32a_2.spice
index 6b243ea..f816a3a 100644
--- a/cells/o32a/sky130_fd_sc_ls__o32a_2.spice
+++ b/cells/o32a/sky130_fd_sc_ls__o32a_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o32a_2.spice
-* Created: Fri Aug 28 13:54:08 2020
+* Created: Wed Sep 2 11:22:47 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o32a/sky130_fd_sc_ls__o32a_4.lvs.report b/cells/o32a/sky130_fd_sc_ls__o32a_4.lvs.report
new file mode 100644
index 0000000..8b8ed8d
--- /dev/null
+++ b/cells/o32a/sky130_fd_sc_ls__o32a_4.lvs.report
@@ -0,0 +1,475 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__o32a_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__o32a_4.sp ('sky130_fd_sc_ls__o32a_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/o32a/sky130_fd_sc_ls__o32a_4.spice ('sky130_fd_sc_ls__o32a_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:22:51 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__o32a_4 sky130_fd_sc_ls__o32a_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__o32a_4
+SOURCE CELL NAME: sky130_fd_sc_ls__o32a_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 15 15
+
+ Instances: 14 14 MN (4 pins)
+ 14 14 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 29 28
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 11 11
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SMP3 (5 pins)
+ 1 1 SPMN_3_2 (7 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ 1 1 0 0 SMP3
+ 1 1 0 0 SPMN_3_2
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 28 layout mos transistors were reduced to 12.
+ 16 mos transistors were deleted by parallel reduction.
+ 28 source mos transistors were reduced to 12.
+ 16 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1 B2 A3 A2 A1 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o32a/sky130_fd_sc_ls__o32a_4.pex.spice b/cells/o32a/sky130_fd_sc_ls__o32a_4.pex.spice
index b7faa7a..cc0bad6 100644
--- a/cells/o32a/sky130_fd_sc_ls__o32a_4.pex.spice
+++ b/cells/o32a/sky130_fd_sc_ls__o32a_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o32a_4.pex.spice
-* Created: Fri Aug 28 13:54:26 2020
+* Created: Wed Sep 2 11:22:54 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o32a/sky130_fd_sc_ls__o32a_4.pxi.spice b/cells/o32a/sky130_fd_sc_ls__o32a_4.pxi.spice
index 2ec8d36..2201323 100644
--- a/cells/o32a/sky130_fd_sc_ls__o32a_4.pxi.spice
+++ b/cells/o32a/sky130_fd_sc_ls__o32a_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o32a_4.pxi.spice
-* Created: Fri Aug 28 13:54:26 2020
+* Created: Wed Sep 2 11:22:54 2020
*
x_PM_SKY130_FD_SC_LS__O32A_4%A_83_256# N_A_83_256#_M1008_d N_A_83_256#_M1020_s
+ N_A_83_256#_M1017_d N_A_83_256#_M1002_d N_A_83_256#_c_161_n
diff --git a/cells/o32a/sky130_fd_sc_ls__o32a_4.spice b/cells/o32a/sky130_fd_sc_ls__o32a_4.spice
index cb30b63..a933260 100644
--- a/cells/o32a/sky130_fd_sc_ls__o32a_4.spice
+++ b/cells/o32a/sky130_fd_sc_ls__o32a_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o32a_4.spice
-* Created: Fri Aug 28 13:54:26 2020
+* Created: Wed Sep 2 11:22:54 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o32ai/sky130_fd_sc_ls__o32ai_1.lvs.report b/cells/o32ai/sky130_fd_sc_ls__o32ai_1.lvs.report
new file mode 100644
index 0000000..dc98e5c
--- /dev/null
+++ b/cells/o32ai/sky130_fd_sc_ls__o32ai_1.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__o32ai_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__o32ai_1.sp ('sky130_fd_sc_ls__o32ai_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/o32ai/sky130_fd_sc_ls__o32ai_1.spice ('sky130_fd_sc_ls__o32ai_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:22:58 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__o32ai_1 sky130_fd_sc_ls__o32ai_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__o32ai_1
+SOURCE CELL NAME: sky130_fd_sc_ls__o32ai_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 14 14
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 10 10
+
+ Instances: 1 1 SMP2 (4 pins)
+ 1 1 SMP3 (5 pins)
+ 1 1 SPMN_3_2 (7 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 SMP2
+ 1 1 0 0 SMP3
+ 1 1 0 0 SPMN_3_2
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1 B2 A3 A2 A1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o32ai/sky130_fd_sc_ls__o32ai_1.pex.spice b/cells/o32ai/sky130_fd_sc_ls__o32ai_1.pex.spice
index 52db8b0..60c1843 100644
--- a/cells/o32ai/sky130_fd_sc_ls__o32ai_1.pex.spice
+++ b/cells/o32ai/sky130_fd_sc_ls__o32ai_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o32ai_1.pex.spice
-* Created: Fri Aug 28 13:54:46 2020
+* Created: Wed Sep 2 11:23:01 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o32ai/sky130_fd_sc_ls__o32ai_1.pxi.spice b/cells/o32ai/sky130_fd_sc_ls__o32ai_1.pxi.spice
index 7fab5f2..0883fd6 100644
--- a/cells/o32ai/sky130_fd_sc_ls__o32ai_1.pxi.spice
+++ b/cells/o32ai/sky130_fd_sc_ls__o32ai_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o32ai_1.pxi.spice
-* Created: Fri Aug 28 13:54:46 2020
+* Created: Wed Sep 2 11:23:01 2020
*
x_PM_SKY130_FD_SC_LS__O32AI_1%B1 N_B1_c_48_n N_B1_M1008_g N_B1_c_49_n
+ N_B1_M1005_g B1 PM_SKY130_FD_SC_LS__O32AI_1%B1
diff --git a/cells/o32ai/sky130_fd_sc_ls__o32ai_1.spice b/cells/o32ai/sky130_fd_sc_ls__o32ai_1.spice
index 0cbd078..068b99d 100644
--- a/cells/o32ai/sky130_fd_sc_ls__o32ai_1.spice
+++ b/cells/o32ai/sky130_fd_sc_ls__o32ai_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o32ai_1.spice
-* Created: Fri Aug 28 13:54:46 2020
+* Created: Wed Sep 2 11:23:01 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o32ai/sky130_fd_sc_ls__o32ai_2.lvs.report b/cells/o32ai/sky130_fd_sc_ls__o32ai_2.lvs.report
new file mode 100644
index 0000000..5785672
--- /dev/null
+++ b/cells/o32ai/sky130_fd_sc_ls__o32ai_2.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__o32ai_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__o32ai_2.sp ('sky130_fd_sc_ls__o32ai_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/o32ai/sky130_fd_sc_ls__o32ai_2.spice ('sky130_fd_sc_ls__o32ai_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:23:04 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__o32ai_2 sky130_fd_sc_ls__o32ai_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__o32ai_2
+SOURCE CELL NAME: sky130_fd_sc_ls__o32ai_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 14 14
+
+ Instances: 10 10 MN (4 pins)
+ 10 10 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 21 20
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 10 10
+
+ Instances: 1 1 SMP2 (4 pins)
+ 1 1 SMP3 (5 pins)
+ 1 1 SPMN_3_2 (7 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 SMP2
+ 1 1 0 0 SMP3
+ 1 1 0 0 SPMN_3_2
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 20 layout mos transistors were reduced to 10.
+ 10 mos transistors were deleted by parallel reduction.
+ 20 source mos transistors were reduced to 10.
+ 10 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B2 B1 A3 A2 A1 Y VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o32ai/sky130_fd_sc_ls__o32ai_2.pex.spice b/cells/o32ai/sky130_fd_sc_ls__o32ai_2.pex.spice
index b98e808..3ac5e76 100644
--- a/cells/o32ai/sky130_fd_sc_ls__o32ai_2.pex.spice
+++ b/cells/o32ai/sky130_fd_sc_ls__o32ai_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o32ai_2.pex.spice
-* Created: Fri Aug 28 13:54:57 2020
+* Created: Wed Sep 2 11:23:08 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o32ai/sky130_fd_sc_ls__o32ai_2.pxi.spice b/cells/o32ai/sky130_fd_sc_ls__o32ai_2.pxi.spice
index 09c376f..7222d7c 100644
--- a/cells/o32ai/sky130_fd_sc_ls__o32ai_2.pxi.spice
+++ b/cells/o32ai/sky130_fd_sc_ls__o32ai_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o32ai_2.pxi.spice
-* Created: Fri Aug 28 13:54:57 2020
+* Created: Wed Sep 2 11:23:08 2020
*
x_PM_SKY130_FD_SC_LS__O32AI_2%B2 N_B2_M1015_g N_B2_c_101_n N_B2_M1007_g
+ N_B2_M1016_g N_B2_c_102_n N_B2_M1008_g B2 B2 B2 N_B2_c_100_n
diff --git a/cells/o32ai/sky130_fd_sc_ls__o32ai_2.spice b/cells/o32ai/sky130_fd_sc_ls__o32ai_2.spice
index cc9e3fe..b922252 100644
--- a/cells/o32ai/sky130_fd_sc_ls__o32ai_2.spice
+++ b/cells/o32ai/sky130_fd_sc_ls__o32ai_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o32ai_2.spice
-* Created: Fri Aug 28 13:54:57 2020
+* Created: Wed Sep 2 11:23:08 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o32ai/sky130_fd_sc_ls__o32ai_4.lvs.report b/cells/o32ai/sky130_fd_sc_ls__o32ai_4.lvs.report
new file mode 100644
index 0000000..1088cd8
--- /dev/null
+++ b/cells/o32ai/sky130_fd_sc_ls__o32ai_4.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__o32ai_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__o32ai_4.sp ('sky130_fd_sc_ls__o32ai_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/o32ai/sky130_fd_sc_ls__o32ai_4.spice ('sky130_fd_sc_ls__o32ai_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:23:11 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__o32ai_4 sky130_fd_sc_ls__o32ai_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__o32ai_4
+SOURCE CELL NAME: sky130_fd_sc_ls__o32ai_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 14 14
+
+ Instances: 20 20 MN (4 pins)
+ 20 20 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 41 40
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 10 10
+
+ Instances: 1 1 SMP2 (4 pins)
+ 1 1 SMP3 (5 pins)
+ 1 1 SPMN_3_2 (7 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 SMP2
+ 1 1 0 0 SMP3
+ 1 1 0 0 SPMN_3_2
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 40 layout mos transistors were reduced to 10.
+ 30 mos transistors were deleted by parallel reduction.
+ 40 source mos transistors were reduced to 10.
+ 30 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B2 B1 A3 A2 A1 Y VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o32ai/sky130_fd_sc_ls__o32ai_4.pex.spice b/cells/o32ai/sky130_fd_sc_ls__o32ai_4.pex.spice
index f23b3f1..92fa380 100644
--- a/cells/o32ai/sky130_fd_sc_ls__o32ai_4.pex.spice
+++ b/cells/o32ai/sky130_fd_sc_ls__o32ai_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o32ai_4.pex.spice
-* Created: Fri Aug 28 13:55:07 2020
+* Created: Wed Sep 2 11:23:15 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o32ai/sky130_fd_sc_ls__o32ai_4.pxi.spice b/cells/o32ai/sky130_fd_sc_ls__o32ai_4.pxi.spice
index a7d443f..3d5eb44 100644
--- a/cells/o32ai/sky130_fd_sc_ls__o32ai_4.pxi.spice
+++ b/cells/o32ai/sky130_fd_sc_ls__o32ai_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o32ai_4.pxi.spice
-* Created: Fri Aug 28 13:55:07 2020
+* Created: Wed Sep 2 11:23:15 2020
*
x_PM_SKY130_FD_SC_LS__O32AI_4%B2 N_B2_M1015_g N_B2_c_159_n N_B2_M1004_g
+ N_B2_M1025_g N_B2_c_160_n N_B2_M1020_g N_B2_c_161_n N_B2_M1021_g N_B2_M1029_g
diff --git a/cells/o32ai/sky130_fd_sc_ls__o32ai_4.spice b/cells/o32ai/sky130_fd_sc_ls__o32ai_4.spice
index 66f281d..b39b743 100644
--- a/cells/o32ai/sky130_fd_sc_ls__o32ai_4.spice
+++ b/cells/o32ai/sky130_fd_sc_ls__o32ai_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o32ai_4.spice
-* Created: Fri Aug 28 13:55:07 2020
+* Created: Wed Sep 2 11:23:15 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o41a/sky130_fd_sc_ls__o41a_1.lvs.report b/cells/o41a/sky130_fd_sc_ls__o41a_1.lvs.report
new file mode 100644
index 0000000..72e1fb8
--- /dev/null
+++ b/cells/o41a/sky130_fd_sc_ls__o41a_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__o41a_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__o41a_1.sp ('sky130_fd_sc_ls__o41a_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/o41a/sky130_fd_sc_ls__o41a_1.spice ('sky130_fd_sc_ls__o41a_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:23:19 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__o41a_1 sky130_fd_sc_ls__o41a_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__o41a_1
+SOURCE CELL NAME: sky130_fd_sc_ls__o41a_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 15 15
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 11 11
+
+ Instances: 1 1 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 1 SMP4 (6 pins)
+ 1 1 SPMN_4_1 (7 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP4
+ 1 1 0 0 SPMN_4_1
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1 A4 A3 A2 A1 X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o41a/sky130_fd_sc_ls__o41a_1.pex.spice b/cells/o41a/sky130_fd_sc_ls__o41a_1.pex.spice
index 1c6d143..f9f0969 100644
--- a/cells/o41a/sky130_fd_sc_ls__o41a_1.pex.spice
+++ b/cells/o41a/sky130_fd_sc_ls__o41a_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o41a_1.pex.spice
-* Created: Fri Aug 28 13:55:17 2020
+* Created: Wed Sep 2 11:23:22 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o41a/sky130_fd_sc_ls__o41a_1.pxi.spice b/cells/o41a/sky130_fd_sc_ls__o41a_1.pxi.spice
index 3235e5d..9ec8c84 100644
--- a/cells/o41a/sky130_fd_sc_ls__o41a_1.pxi.spice
+++ b/cells/o41a/sky130_fd_sc_ls__o41a_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o41a_1.pxi.spice
-* Created: Fri Aug 28 13:55:17 2020
+* Created: Wed Sep 2 11:23:22 2020
*
x_PM_SKY130_FD_SC_LS__O41A_1%A_83_270# N_A_83_270#_M1005_s N_A_83_270#_M1002_d
+ N_A_83_270#_M1010_g N_A_83_270#_c_70_n N_A_83_270#_M1006_g N_A_83_270#_c_75_n
diff --git a/cells/o41a/sky130_fd_sc_ls__o41a_1.spice b/cells/o41a/sky130_fd_sc_ls__o41a_1.spice
index df07c24..cac104e 100644
--- a/cells/o41a/sky130_fd_sc_ls__o41a_1.spice
+++ b/cells/o41a/sky130_fd_sc_ls__o41a_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o41a_1.spice
-* Created: Fri Aug 28 13:55:17 2020
+* Created: Wed Sep 2 11:23:22 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o41a/sky130_fd_sc_ls__o41a_2.lvs.report b/cells/o41a/sky130_fd_sc_ls__o41a_2.lvs.report
new file mode 100644
index 0000000..0868978
--- /dev/null
+++ b/cells/o41a/sky130_fd_sc_ls__o41a_2.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__o41a_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__o41a_2.sp ('sky130_fd_sc_ls__o41a_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/o41a/sky130_fd_sc_ls__o41a_2.spice ('sky130_fd_sc_ls__o41a_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:23:26 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__o41a_2 sky130_fd_sc_ls__o41a_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__o41a_2
+SOURCE CELL NAME: sky130_fd_sc_ls__o41a_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 15 15
+
+ Instances: 7 7 MN (4 pins)
+ 7 7 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 15 14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 11 11
+
+ Instances: 1 1 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 1 SMP4 (6 pins)
+ 1 1 SPMN_4_1 (7 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP4
+ 1 1 0 0 SPMN_4_1
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1 A2 A3 A4 B1 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o41a/sky130_fd_sc_ls__o41a_2.pex.spice b/cells/o41a/sky130_fd_sc_ls__o41a_2.pex.spice
index 76e3213..877e6b5 100644
--- a/cells/o41a/sky130_fd_sc_ls__o41a_2.pex.spice
+++ b/cells/o41a/sky130_fd_sc_ls__o41a_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o41a_2.pex.spice
-* Created: Fri Aug 28 13:55:35 2020
+* Created: Wed Sep 2 11:23:29 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o41a/sky130_fd_sc_ls__o41a_2.pxi.spice b/cells/o41a/sky130_fd_sc_ls__o41a_2.pxi.spice
index 457d8e4..2a91cb2 100644
--- a/cells/o41a/sky130_fd_sc_ls__o41a_2.pxi.spice
+++ b/cells/o41a/sky130_fd_sc_ls__o41a_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o41a_2.pxi.spice
-* Created: Fri Aug 28 13:55:35 2020
+* Created: Wed Sep 2 11:23:29 2020
*
x_PM_SKY130_FD_SC_LS__O41A_2%A1 N_A1_M1010_g N_A1_c_73_n N_A1_M1007_g A1
+ N_A1_c_74_n PM_SKY130_FD_SC_LS__O41A_2%A1
diff --git a/cells/o41a/sky130_fd_sc_ls__o41a_2.spice b/cells/o41a/sky130_fd_sc_ls__o41a_2.spice
index 59e0688..ec280e2 100644
--- a/cells/o41a/sky130_fd_sc_ls__o41a_2.spice
+++ b/cells/o41a/sky130_fd_sc_ls__o41a_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o41a_2.spice
-* Created: Fri Aug 28 13:55:35 2020
+* Created: Wed Sep 2 11:23:29 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o41a/sky130_fd_sc_ls__o41a_4.lvs.report b/cells/o41a/sky130_fd_sc_ls__o41a_4.lvs.report
new file mode 100644
index 0000000..cb8cc20
--- /dev/null
+++ b/cells/o41a/sky130_fd_sc_ls__o41a_4.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__o41a_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__o41a_4.sp ('sky130_fd_sc_ls__o41a_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/o41a/sky130_fd_sc_ls__o41a_4.spice ('sky130_fd_sc_ls__o41a_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:23:32 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__o41a_4 sky130_fd_sc_ls__o41a_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__o41a_4
+SOURCE CELL NAME: sky130_fd_sc_ls__o41a_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 15 15
+
+ Instances: 14 14 MN (4 pins)
+ 14 14 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 29 28
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 11 11
+
+ Instances: 1 1 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 1 SMP4 (6 pins)
+ 1 1 SPMN_4_1 (7 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP4
+ 1 1 0 0 SPMN_4_1
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 28 layout mos transistors were reduced to 12.
+ 16 mos transistors were deleted by parallel reduction.
+ 28 source mos transistors were reduced to 12.
+ 16 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1 A4 A3 A1 A2 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o41a/sky130_fd_sc_ls__o41a_4.pex.spice b/cells/o41a/sky130_fd_sc_ls__o41a_4.pex.spice
index 8f55793..6f53c73 100644
--- a/cells/o41a/sky130_fd_sc_ls__o41a_4.pex.spice
+++ b/cells/o41a/sky130_fd_sc_ls__o41a_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o41a_4.pex.spice
-* Created: Fri Aug 28 13:55:55 2020
+* Created: Wed Sep 2 11:23:36 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o41a/sky130_fd_sc_ls__o41a_4.pxi.spice b/cells/o41a/sky130_fd_sc_ls__o41a_4.pxi.spice
index 1f964d5..f0adf35 100644
--- a/cells/o41a/sky130_fd_sc_ls__o41a_4.pxi.spice
+++ b/cells/o41a/sky130_fd_sc_ls__o41a_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o41a_4.pxi.spice
-* Created: Fri Aug 28 13:55:55 2020
+* Created: Wed Sep 2 11:23:36 2020
*
x_PM_SKY130_FD_SC_LS__O41A_4%A_110_48# N_A_110_48#_M1003_s N_A_110_48#_M1010_d
+ N_A_110_48#_M1022_s N_A_110_48#_M1006_g N_A_110_48#_c_151_n
diff --git a/cells/o41a/sky130_fd_sc_ls__o41a_4.spice b/cells/o41a/sky130_fd_sc_ls__o41a_4.spice
index c5d2585..d6f8f23 100644
--- a/cells/o41a/sky130_fd_sc_ls__o41a_4.spice
+++ b/cells/o41a/sky130_fd_sc_ls__o41a_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o41a_4.spice
-* Created: Fri Aug 28 13:55:55 2020
+* Created: Wed Sep 2 11:23:36 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o41ai/sky130_fd_sc_ls__o41ai_1.lvs.report b/cells/o41ai/sky130_fd_sc_ls__o41ai_1.lvs.report
new file mode 100644
index 0000000..dc105e1
--- /dev/null
+++ b/cells/o41ai/sky130_fd_sc_ls__o41ai_1.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__o41ai_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__o41ai_1.sp ('sky130_fd_sc_ls__o41ai_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/o41ai/sky130_fd_sc_ls__o41ai_1.spice ('sky130_fd_sc_ls__o41ai_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:23:39 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__o41ai_1 sky130_fd_sc_ls__o41ai_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__o41ai_1
+SOURCE CELL NAME: sky130_fd_sc_ls__o41ai_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 14 14
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 10 10
+
+ Instances: 1 1 MP (4 pins)
+ 1 1 SMP4 (6 pins)
+ 1 1 SPMN_4_1 (7 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP4
+ 1 1 0 0 SPMN_4_1
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1 A4 A3 A2 A1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o41ai/sky130_fd_sc_ls__o41ai_1.pex.spice b/cells/o41ai/sky130_fd_sc_ls__o41ai_1.pex.spice
index 13f33c9..161e693 100644
--- a/cells/o41ai/sky130_fd_sc_ls__o41ai_1.pex.spice
+++ b/cells/o41ai/sky130_fd_sc_ls__o41ai_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o41ai_1.pex.spice
-* Created: Fri Aug 28 13:56:06 2020
+* Created: Wed Sep 2 11:23:43 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o41ai/sky130_fd_sc_ls__o41ai_1.pxi.spice b/cells/o41ai/sky130_fd_sc_ls__o41ai_1.pxi.spice
index b067dc1..88c3de7 100644
--- a/cells/o41ai/sky130_fd_sc_ls__o41ai_1.pxi.spice
+++ b/cells/o41ai/sky130_fd_sc_ls__o41ai_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o41ai_1.pxi.spice
-* Created: Fri Aug 28 13:56:06 2020
+* Created: Wed Sep 2 11:23:43 2020
*
x_PM_SKY130_FD_SC_LS__O41AI_1%B1 N_B1_M1008_g N_B1_c_60_n N_B1_M1001_g
+ N_B1_c_57_n N_B1_c_58_n B1 PM_SKY130_FD_SC_LS__O41AI_1%B1
diff --git a/cells/o41ai/sky130_fd_sc_ls__o41ai_1.spice b/cells/o41ai/sky130_fd_sc_ls__o41ai_1.spice
index 5868276..16bc07b 100644
--- a/cells/o41ai/sky130_fd_sc_ls__o41ai_1.spice
+++ b/cells/o41ai/sky130_fd_sc_ls__o41ai_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o41ai_1.spice
-* Created: Fri Aug 28 13:56:06 2020
+* Created: Wed Sep 2 11:23:43 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o41ai/sky130_fd_sc_ls__o41ai_2.lvs.report b/cells/o41ai/sky130_fd_sc_ls__o41ai_2.lvs.report
new file mode 100644
index 0000000..ee28f3e
--- /dev/null
+++ b/cells/o41ai/sky130_fd_sc_ls__o41ai_2.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__o41ai_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__o41ai_2.sp ('sky130_fd_sc_ls__o41ai_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/o41ai/sky130_fd_sc_ls__o41ai_2.spice ('sky130_fd_sc_ls__o41ai_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:23:47 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__o41ai_2 sky130_fd_sc_ls__o41ai_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__o41ai_2
+SOURCE CELL NAME: sky130_fd_sc_ls__o41ai_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 14 14
+
+ Instances: 10 10 MN (4 pins)
+ 10 10 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 21 20
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 10 10
+
+ Instances: 1 1 MP (4 pins)
+ 1 1 SMP4 (6 pins)
+ 1 1 SPMN_4_1 (7 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP4
+ 1 1 0 0 SPMN_4_1
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 20 layout mos transistors were reduced to 10.
+ 10 mos transistors were deleted by parallel reduction.
+ 20 source mos transistors were reduced to 10.
+ 10 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1 A4 A3 A2 A1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o41ai/sky130_fd_sc_ls__o41ai_2.pex.spice b/cells/o41ai/sky130_fd_sc_ls__o41ai_2.pex.spice
index fa12c12..5d8ba3b 100644
--- a/cells/o41ai/sky130_fd_sc_ls__o41ai_2.pex.spice
+++ b/cells/o41ai/sky130_fd_sc_ls__o41ai_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o41ai_2.pex.spice
-* Created: Fri Aug 28 13:56:16 2020
+* Created: Wed Sep 2 11:23:50 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o41ai/sky130_fd_sc_ls__o41ai_2.pxi.spice b/cells/o41ai/sky130_fd_sc_ls__o41ai_2.pxi.spice
index 850168c..b864fff 100644
--- a/cells/o41ai/sky130_fd_sc_ls__o41ai_2.pxi.spice
+++ b/cells/o41ai/sky130_fd_sc_ls__o41ai_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o41ai_2.pxi.spice
-* Created: Fri Aug 28 13:56:16 2020
+* Created: Wed Sep 2 11:23:50 2020
*
x_PM_SKY130_FD_SC_LS__O41AI_2%B1 N_B1_c_120_n N_B1_M1015_g N_B1_c_121_n
+ N_B1_M1016_g N_B1_c_112_n N_B1_M1003_g N_B1_c_113_n N_B1_c_114_n N_B1_c_115_n
diff --git a/cells/o41ai/sky130_fd_sc_ls__o41ai_2.spice b/cells/o41ai/sky130_fd_sc_ls__o41ai_2.spice
index 25640f9..de0b4bf 100644
--- a/cells/o41ai/sky130_fd_sc_ls__o41ai_2.spice
+++ b/cells/o41ai/sky130_fd_sc_ls__o41ai_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o41ai_2.spice
-* Created: Fri Aug 28 13:56:16 2020
+* Created: Wed Sep 2 11:23:50 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o41ai/sky130_fd_sc_ls__o41ai_4.lvs.report b/cells/o41ai/sky130_fd_sc_ls__o41ai_4.lvs.report
new file mode 100644
index 0000000..e4c95b5
--- /dev/null
+++ b/cells/o41ai/sky130_fd_sc_ls__o41ai_4.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__o41ai_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__o41ai_4.sp ('sky130_fd_sc_ls__o41ai_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/o41ai/sky130_fd_sc_ls__o41ai_4.spice ('sky130_fd_sc_ls__o41ai_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:23:54 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__o41ai_4 sky130_fd_sc_ls__o41ai_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__o41ai_4
+SOURCE CELL NAME: sky130_fd_sc_ls__o41ai_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 14 14
+
+ Instances: 20 20 MN (4 pins)
+ 18 18 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 39 38
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 10 10
+
+ Instances: 1 1 MP (4 pins)
+ 1 1 SMP4 (6 pins)
+ 1 1 SPMN_4_1 (7 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP4
+ 1 1 0 0 SPMN_4_1
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 38 layout mos transistors were reduced to 10.
+ 28 mos transistors were deleted by parallel reduction.
+ 38 source mos transistors were reduced to 10.
+ 28 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1 A4 A3 A2 A1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o41ai/sky130_fd_sc_ls__o41ai_4.pex.spice b/cells/o41ai/sky130_fd_sc_ls__o41ai_4.pex.spice
index 2463863..e3e1cf1 100644
--- a/cells/o41ai/sky130_fd_sc_ls__o41ai_4.pex.spice
+++ b/cells/o41ai/sky130_fd_sc_ls__o41ai_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o41ai_4.pex.spice
-* Created: Fri Aug 28 13:56:26 2020
+* Created: Wed Sep 2 11:23:57 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o41ai/sky130_fd_sc_ls__o41ai_4.pxi.spice b/cells/o41ai/sky130_fd_sc_ls__o41ai_4.pxi.spice
index 7cd8ebf..78d4fcd 100644
--- a/cells/o41ai/sky130_fd_sc_ls__o41ai_4.pxi.spice
+++ b/cells/o41ai/sky130_fd_sc_ls__o41ai_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o41ai_4.pxi.spice
-* Created: Fri Aug 28 13:56:26 2020
+* Created: Wed Sep 2 11:23:57 2020
*
x_PM_SKY130_FD_SC_LS__O41AI_4%B1 N_B1_c_149_n N_B1_M1010_g N_B1_c_156_n
+ N_B1_M1018_g N_B1_c_150_n N_B1_M1012_g N_B1_c_157_n N_B1_M1020_g N_B1_c_151_n
diff --git a/cells/o41ai/sky130_fd_sc_ls__o41ai_4.spice b/cells/o41ai/sky130_fd_sc_ls__o41ai_4.spice
index 1ee4e1f..043b029 100644
--- a/cells/o41ai/sky130_fd_sc_ls__o41ai_4.spice
+++ b/cells/o41ai/sky130_fd_sc_ls__o41ai_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__o41ai_4.spice
-* Created: Fri Aug 28 13:56:26 2020
+* Created: Wed Sep 2 11:23:57 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/or2/sky130_fd_sc_ls__or2_1.lvs.report b/cells/or2/sky130_fd_sc_ls__or2_1.lvs.report
new file mode 100644
index 0000000..b89d810
--- /dev/null
+++ b/cells/or2/sky130_fd_sc_ls__or2_1.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__or2_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__or2_1.sp ('sky130_fd_sc_ls__or2_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/or2/sky130_fd_sc_ls__or2_1.spice ('sky130_fd_sc_ls__or2_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:24:01 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__or2_1 sky130_fd_sc_ls__or2_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__or2_1
+SOURCE CELL NAME: sky130_fd_sc_ls__or2_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 9 9
+
+ Instances: 3 3 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 7 6
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 3 3 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 3 3 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/or2/sky130_fd_sc_ls__or2_1.pex.spice b/cells/or2/sky130_fd_sc_ls__or2_1.pex.spice
index 37050f7..b9e16f5 100644
--- a/cells/or2/sky130_fd_sc_ls__or2_1.pex.spice
+++ b/cells/or2/sky130_fd_sc_ls__or2_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__or2_1.pex.spice
-* Created: Fri Aug 28 13:56:43 2020
+* Created: Wed Sep 2 11:24:04 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/or2/sky130_fd_sc_ls__or2_1.pxi.spice b/cells/or2/sky130_fd_sc_ls__or2_1.pxi.spice
index 8529d53..648e72a 100644
--- a/cells/or2/sky130_fd_sc_ls__or2_1.pxi.spice
+++ b/cells/or2/sky130_fd_sc_ls__or2_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__or2_1.pxi.spice
-* Created: Fri Aug 28 13:56:43 2020
+* Created: Wed Sep 2 11:24:04 2020
*
x_PM_SKY130_FD_SC_LS__OR2_1%B N_B_c_41_n N_B_c_45_n N_B_M1000_g N_B_M1004_g B
+ N_B_c_42_n N_B_c_43_n PM_SKY130_FD_SC_LS__OR2_1%B
diff --git a/cells/or2/sky130_fd_sc_ls__or2_1.spice b/cells/or2/sky130_fd_sc_ls__or2_1.spice
index b65d7f3..41bd499 100644
--- a/cells/or2/sky130_fd_sc_ls__or2_1.spice
+++ b/cells/or2/sky130_fd_sc_ls__or2_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__or2_1.spice
-* Created: Fri Aug 28 13:56:43 2020
+* Created: Wed Sep 2 11:24:04 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/or2/sky130_fd_sc_ls__or2_2.lvs.report b/cells/or2/sky130_fd_sc_ls__or2_2.lvs.report
new file mode 100644
index 0000000..cd97b81
--- /dev/null
+++ b/cells/or2/sky130_fd_sc_ls__or2_2.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__or2_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__or2_2.sp ('sky130_fd_sc_ls__or2_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/or2/sky130_fd_sc_ls__or2_2.spice ('sky130_fd_sc_ls__or2_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:24:08 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__or2_2 sky130_fd_sc_ls__or2_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__or2_2
+SOURCE CELL NAME: sky130_fd_sc_ls__or2_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 9 9
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 3 3 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 3 3 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/or2/sky130_fd_sc_ls__or2_2.pex.spice b/cells/or2/sky130_fd_sc_ls__or2_2.pex.spice
index 7898141..b48d527 100644
--- a/cells/or2/sky130_fd_sc_ls__or2_2.pex.spice
+++ b/cells/or2/sky130_fd_sc_ls__or2_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__or2_2.pex.spice
-* Created: Fri Aug 28 13:57:04 2020
+* Created: Wed Sep 2 11:24:11 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/or2/sky130_fd_sc_ls__or2_2.pxi.spice b/cells/or2/sky130_fd_sc_ls__or2_2.pxi.spice
index e9ffa62..eda7618 100644
--- a/cells/or2/sky130_fd_sc_ls__or2_2.pxi.spice
+++ b/cells/or2/sky130_fd_sc_ls__or2_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__or2_2.pxi.spice
-* Created: Fri Aug 28 13:57:04 2020
+* Created: Wed Sep 2 11:24:11 2020
*
x_PM_SKY130_FD_SC_LS__OR2_2%B N_B_c_48_n N_B_M1004_g N_B_c_49_n N_B_M1007_g B
+ PM_SKY130_FD_SC_LS__OR2_2%B
diff --git a/cells/or2/sky130_fd_sc_ls__or2_2.spice b/cells/or2/sky130_fd_sc_ls__or2_2.spice
index 2264c24..ee9ed45 100644
--- a/cells/or2/sky130_fd_sc_ls__or2_2.spice
+++ b/cells/or2/sky130_fd_sc_ls__or2_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__or2_2.spice
-* Created: Fri Aug 28 13:57:04 2020
+* Created: Wed Sep 2 11:24:11 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/or2/sky130_fd_sc_ls__or2_4.lvs.report b/cells/or2/sky130_fd_sc_ls__or2_4.lvs.report
new file mode 100644
index 0000000..42c4a98
--- /dev/null
+++ b/cells/or2/sky130_fd_sc_ls__or2_4.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__or2_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__or2_4.sp ('sky130_fd_sc_ls__or2_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/or2/sky130_fd_sc_ls__or2_4.spice ('sky130_fd_sc_ls__or2_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:24:14 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__or2_4 sky130_fd_sc_ls__or2_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__or2_4
+SOURCE CELL NAME: sky130_fd_sc_ls__or2_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 9 9
+
+ Instances: 6 6 MN (4 pins)
+ 8 8 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 15 14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 3 3 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 3 3 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 12 layout mos transistors were reduced to 4.
+ 8 mos transistors were deleted by parallel reduction.
+ 12 source mos transistors were reduced to 4.
+ 8 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A B VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/or2/sky130_fd_sc_ls__or2_4.pex.spice b/cells/or2/sky130_fd_sc_ls__or2_4.pex.spice
index 883bf5d..4f3faa0 100644
--- a/cells/or2/sky130_fd_sc_ls__or2_4.pex.spice
+++ b/cells/or2/sky130_fd_sc_ls__or2_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__or2_4.pex.spice
-* Created: Fri Aug 28 13:57:15 2020
+* Created: Wed Sep 2 11:24:18 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/or2/sky130_fd_sc_ls__or2_4.pxi.spice b/cells/or2/sky130_fd_sc_ls__or2_4.pxi.spice
index c8cd4cc..4d8f006 100644
--- a/cells/or2/sky130_fd_sc_ls__or2_4.pxi.spice
+++ b/cells/or2/sky130_fd_sc_ls__or2_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__or2_4.pxi.spice
-* Created: Fri Aug 28 13:57:15 2020
+* Created: Wed Sep 2 11:24:18 2020
*
x_PM_SKY130_FD_SC_LS__OR2_4%A_83_260# N_A_83_260#_M1004_d N_A_83_260#_M1003_d
+ N_A_83_260#_M1005_g N_A_83_260#_c_87_n N_A_83_260#_M1001_g N_A_83_260#_M1006_g
diff --git a/cells/or2/sky130_fd_sc_ls__or2_4.spice b/cells/or2/sky130_fd_sc_ls__or2_4.spice
index 012c476..3239fc2 100644
--- a/cells/or2/sky130_fd_sc_ls__or2_4.spice
+++ b/cells/or2/sky130_fd_sc_ls__or2_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__or2_4.spice
-* Created: Fri Aug 28 13:57:15 2020
+* Created: Wed Sep 2 11:24:18 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/or2b/sky130_fd_sc_ls__or2b_1.lvs.report b/cells/or2b/sky130_fd_sc_ls__or2b_1.lvs.report
new file mode 100644
index 0000000..edb1018
--- /dev/null
+++ b/cells/or2b/sky130_fd_sc_ls__or2b_1.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__or2b_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__or2b_1.sp ('sky130_fd_sc_ls__or2b_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/or2b/sky130_fd_sc_ls__or2b_1.spice ('sky130_fd_sc_ls__or2b_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:24:21 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__or2b_1 sky130_fd_sc_ls__or2b_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__or2b_1
+SOURCE CELL NAME: sky130_fd_sc_ls__or2b_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 10 10
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 9 9
+
+ Instances: 4 4 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 7 7
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 4 4 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 7 7 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B_N A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/or2b/sky130_fd_sc_ls__or2b_1.pex.spice b/cells/or2b/sky130_fd_sc_ls__or2b_1.pex.spice
index e3365d8..0afa725 100644
--- a/cells/or2b/sky130_fd_sc_ls__or2b_1.pex.spice
+++ b/cells/or2b/sky130_fd_sc_ls__or2b_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__or2b_1.pex.spice
-* Created: Fri Aug 28 13:57:25 2020
+* Created: Wed Sep 2 11:24:25 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/or2b/sky130_fd_sc_ls__or2b_1.pxi.spice b/cells/or2b/sky130_fd_sc_ls__or2b_1.pxi.spice
index dc375fc..5605174 100644
--- a/cells/or2b/sky130_fd_sc_ls__or2b_1.pxi.spice
+++ b/cells/or2b/sky130_fd_sc_ls__or2b_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__or2b_1.pxi.spice
-* Created: Fri Aug 28 13:57:25 2020
+* Created: Wed Sep 2 11:24:25 2020
*
x_PM_SKY130_FD_SC_LS__OR2B_1%B_N N_B_N_c_59_n N_B_N_c_64_n N_B_N_c_65_n
+ N_B_N_M1005_g N_B_N_c_60_n N_B_N_c_61_n N_B_N_M1003_g B_N
diff --git a/cells/or2b/sky130_fd_sc_ls__or2b_1.spice b/cells/or2b/sky130_fd_sc_ls__or2b_1.spice
index d207125..9e31b50 100644
--- a/cells/or2b/sky130_fd_sc_ls__or2b_1.spice
+++ b/cells/or2b/sky130_fd_sc_ls__or2b_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__or2b_1.spice
-* Created: Fri Aug 28 13:57:25 2020
+* Created: Wed Sep 2 11:24:25 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/or2b/sky130_fd_sc_ls__or2b_2.lvs.report b/cells/or2b/sky130_fd_sc_ls__or2b_2.lvs.report
new file mode 100644
index 0000000..91e5f5e
--- /dev/null
+++ b/cells/or2b/sky130_fd_sc_ls__or2b_2.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__or2b_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__or2b_2.sp ('sky130_fd_sc_ls__or2b_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/or2b/sky130_fd_sc_ls__or2b_2.spice ('sky130_fd_sc_ls__or2b_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:24:28 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__or2b_2 sky130_fd_sc_ls__or2b_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__or2b_2
+SOURCE CELL NAME: sky130_fd_sc_ls__or2b_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 10 10
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 9 9
+
+ Instances: 4 4 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 7 7
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 4 4 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 7 7 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B_N A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/or2b/sky130_fd_sc_ls__or2b_2.pex.spice b/cells/or2b/sky130_fd_sc_ls__or2b_2.pex.spice
index 780cadd..4f00f5b 100644
--- a/cells/or2b/sky130_fd_sc_ls__or2b_2.pex.spice
+++ b/cells/or2b/sky130_fd_sc_ls__or2b_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__or2b_2.pex.spice
-* Created: Fri Aug 28 13:57:35 2020
+* Created: Wed Sep 2 11:24:31 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/or2b/sky130_fd_sc_ls__or2b_2.pxi.spice b/cells/or2b/sky130_fd_sc_ls__or2b_2.pxi.spice
index 5b1e5ad..9e18555 100644
--- a/cells/or2b/sky130_fd_sc_ls__or2b_2.pxi.spice
+++ b/cells/or2b/sky130_fd_sc_ls__or2b_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__or2b_2.pxi.spice
-* Created: Fri Aug 28 13:57:35 2020
+* Created: Wed Sep 2 11:24:31 2020
*
x_PM_SKY130_FD_SC_LS__OR2B_2%B_N N_B_N_M1001_g N_B_N_c_64_n N_B_N_M1006_g B_N
+ N_B_N_c_65_n PM_SKY130_FD_SC_LS__OR2B_2%B_N
diff --git a/cells/or2b/sky130_fd_sc_ls__or2b_2.spice b/cells/or2b/sky130_fd_sc_ls__or2b_2.spice
index 13a3ce5..d1f0c7b 100644
--- a/cells/or2b/sky130_fd_sc_ls__or2b_2.spice
+++ b/cells/or2b/sky130_fd_sc_ls__or2b_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__or2b_2.spice
-* Created: Fri Aug 28 13:57:35 2020
+* Created: Wed Sep 2 11:24:31 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/or2b/sky130_fd_sc_ls__or2b_4.lvs.report b/cells/or2b/sky130_fd_sc_ls__or2b_4.lvs.report
new file mode 100644
index 0000000..30de4ee
--- /dev/null
+++ b/cells/or2b/sky130_fd_sc_ls__or2b_4.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__or2b_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__or2b_4.sp ('sky130_fd_sc_ls__or2b_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/or2b/sky130_fd_sc_ls__or2b_4.spice ('sky130_fd_sc_ls__or2b_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:24:35 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__or2b_4 sky130_fd_sc_ls__or2b_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__or2b_4
+SOURCE CELL NAME: sky130_fd_sc_ls__or2b_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 10 10
+
+ Instances: 9 9 MN (4 pins)
+ 9 9 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 19 18
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 9 9
+
+ Instances: 4 4 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 7 7
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 4 4 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 7 7 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 16 layout mos transistors were reduced to 6.
+ 10 mos transistors were deleted by parallel reduction.
+ 16 source mos transistors were reduced to 6.
+ 10 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A B_N VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/or2b/sky130_fd_sc_ls__or2b_4.pex.spice b/cells/or2b/sky130_fd_sc_ls__or2b_4.pex.spice
index c9528f9..0fb82a0 100644
--- a/cells/or2b/sky130_fd_sc_ls__or2b_4.pex.spice
+++ b/cells/or2b/sky130_fd_sc_ls__or2b_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__or2b_4.pex.spice
-* Created: Fri Aug 28 13:57:52 2020
+* Created: Wed Sep 2 11:24:38 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/or2b/sky130_fd_sc_ls__or2b_4.pxi.spice b/cells/or2b/sky130_fd_sc_ls__or2b_4.pxi.spice
index 777f554..e662432 100644
--- a/cells/or2b/sky130_fd_sc_ls__or2b_4.pxi.spice
+++ b/cells/or2b/sky130_fd_sc_ls__or2b_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__or2b_4.pxi.spice
-* Created: Fri Aug 28 13:57:52 2020
+* Created: Wed Sep 2 11:24:38 2020
*
x_PM_SKY130_FD_SC_LS__OR2B_4%A_81_296# N_A_81_296#_M1004_d N_A_81_296#_M1009_d
+ N_A_81_296#_M1001_d N_A_81_296#_M1008_g N_A_81_296#_c_129_n
diff --git a/cells/or2b/sky130_fd_sc_ls__or2b_4.spice b/cells/or2b/sky130_fd_sc_ls__or2b_4.spice
index 9933381..1ac36dc 100644
--- a/cells/or2b/sky130_fd_sc_ls__or2b_4.spice
+++ b/cells/or2b/sky130_fd_sc_ls__or2b_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__or2b_4.spice
-* Created: Fri Aug 28 13:57:52 2020
+* Created: Wed Sep 2 11:24:38 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/or3/sky130_fd_sc_ls__or3_1.lvs.report b/cells/or3/sky130_fd_sc_ls__or3_1.lvs.report
new file mode 100644
index 0000000..42c1db1
--- /dev/null
+++ b/cells/or3/sky130_fd_sc_ls__or3_1.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__or3_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__or3_1.sp ('sky130_fd_sc_ls__or3_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/or3/sky130_fd_sc_ls__or3_1.spice ('sky130_fd_sc_ls__or3_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:24:41 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__or3_1 sky130_fd_sc_ls__or3_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__or3_1
+SOURCE CELL NAME: sky130_fd_sc_ls__or3_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 11 11
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 9 9
+
+ Instances: 4 4 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMP3 (5 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 4 4 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP3
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB C B A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/or3/sky130_fd_sc_ls__or3_1.pex.spice b/cells/or3/sky130_fd_sc_ls__or3_1.pex.spice
index c11f30d..07badc5 100644
--- a/cells/or3/sky130_fd_sc_ls__or3_1.pex.spice
+++ b/cells/or3/sky130_fd_sc_ls__or3_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__or3_1.pex.spice
-* Created: Fri Aug 28 13:58:13 2020
+* Created: Wed Sep 2 11:24:45 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/or3/sky130_fd_sc_ls__or3_1.pxi.spice b/cells/or3/sky130_fd_sc_ls__or3_1.pxi.spice
index 825a15d..94e2802 100644
--- a/cells/or3/sky130_fd_sc_ls__or3_1.pxi.spice
+++ b/cells/or3/sky130_fd_sc_ls__or3_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__or3_1.pxi.spice
-* Created: Fri Aug 28 13:58:13 2020
+* Created: Wed Sep 2 11:24:45 2020
*
x_PM_SKY130_FD_SC_LS__OR3_1%C N_C_M1006_g N_C_c_50_n N_C_M1004_g C N_C_c_51_n
+ PM_SKY130_FD_SC_LS__OR3_1%C
diff --git a/cells/or3/sky130_fd_sc_ls__or3_1.spice b/cells/or3/sky130_fd_sc_ls__or3_1.spice
index cff9b7c..c4804b7 100644
--- a/cells/or3/sky130_fd_sc_ls__or3_1.spice
+++ b/cells/or3/sky130_fd_sc_ls__or3_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__or3_1.spice
-* Created: Fri Aug 28 13:58:13 2020
+* Created: Wed Sep 2 11:24:45 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/or3/sky130_fd_sc_ls__or3_2.lvs.report b/cells/or3/sky130_fd_sc_ls__or3_2.lvs.report
new file mode 100644
index 0000000..8756230
--- /dev/null
+++ b/cells/or3/sky130_fd_sc_ls__or3_2.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__or3_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__or3_2.sp ('sky130_fd_sc_ls__or3_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/or3/sky130_fd_sc_ls__or3_2.spice ('sky130_fd_sc_ls__or3_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:24:48 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__or3_2 sky130_fd_sc_ls__or3_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__or3_2
+SOURCE CELL NAME: sky130_fd_sc_ls__or3_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 11 11
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 9 9
+
+ Instances: 4 4 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMP3 (5 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 4 4 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP3
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB C B A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/or3/sky130_fd_sc_ls__or3_2.pex.spice b/cells/or3/sky130_fd_sc_ls__or3_2.pex.spice
index baf3a34..30f9db0 100644
--- a/cells/or3/sky130_fd_sc_ls__or3_2.pex.spice
+++ b/cells/or3/sky130_fd_sc_ls__or3_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__or3_2.pex.spice
-* Created: Fri Aug 28 13:58:24 2020
+* Created: Wed Sep 2 11:24:52 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/or3/sky130_fd_sc_ls__or3_2.pxi.spice b/cells/or3/sky130_fd_sc_ls__or3_2.pxi.spice
index 6029d9e..f6cc635 100644
--- a/cells/or3/sky130_fd_sc_ls__or3_2.pxi.spice
+++ b/cells/or3/sky130_fd_sc_ls__or3_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__or3_2.pxi.spice
-* Created: Fri Aug 28 13:58:24 2020
+* Created: Wed Sep 2 11:24:52 2020
*
x_PM_SKY130_FD_SC_LS__OR3_2%C N_C_M1008_g N_C_c_61_n N_C_c_66_n N_C_M1003_g C C
+ N_C_c_62_n N_C_c_63_n N_C_c_64_n PM_SKY130_FD_SC_LS__OR3_2%C
diff --git a/cells/or3/sky130_fd_sc_ls__or3_2.spice b/cells/or3/sky130_fd_sc_ls__or3_2.spice
index c81c3be..f635777 100644
--- a/cells/or3/sky130_fd_sc_ls__or3_2.spice
+++ b/cells/or3/sky130_fd_sc_ls__or3_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__or3_2.spice
-* Created: Fri Aug 28 13:58:24 2020
+* Created: Wed Sep 2 11:24:52 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/or3/sky130_fd_sc_ls__or3_4.lvs.report b/cells/or3/sky130_fd_sc_ls__or3_4.lvs.report
new file mode 100644
index 0000000..533fe3d
--- /dev/null
+++ b/cells/or3/sky130_fd_sc_ls__or3_4.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__or3_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__or3_4.sp ('sky130_fd_sc_ls__or3_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/or3/sky130_fd_sc_ls__or3_4.spice ('sky130_fd_sc_ls__or3_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:24:56 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__or3_4 sky130_fd_sc_ls__or3_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__or3_4
+SOURCE CELL NAME: sky130_fd_sc_ls__or3_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 11 11
+
+ Instances: 7 7 MN (4 pins)
+ 10 10 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 18 17
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 9 9
+
+ Instances: 4 4 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMP3 (5 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 4 4 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP3
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 14 layout mos transistors were reduced to 5.
+ 9 mos transistors were deleted by parallel reduction.
+ 14 source mos transistors were reduced to 5.
+ 9 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A B C VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/or3/sky130_fd_sc_ls__or3_4.pex.spice b/cells/or3/sky130_fd_sc_ls__or3_4.pex.spice
index 715048d..69b5176 100644
--- a/cells/or3/sky130_fd_sc_ls__or3_4.pex.spice
+++ b/cells/or3/sky130_fd_sc_ls__or3_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__or3_4.pex.spice
-* Created: Fri Aug 28 13:58:34 2020
+* Created: Wed Sep 2 11:24:59 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/or3/sky130_fd_sc_ls__or3_4.pxi.spice b/cells/or3/sky130_fd_sc_ls__or3_4.pxi.spice
index c7710cf..78fb8c9 100644
--- a/cells/or3/sky130_fd_sc_ls__or3_4.pxi.spice
+++ b/cells/or3/sky130_fd_sc_ls__or3_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__or3_4.pxi.spice
-* Created: Fri Aug 28 13:58:34 2020
+* Created: Wed Sep 2 11:24:59 2020
*
x_PM_SKY130_FD_SC_LS__OR3_4%A N_A_c_93_n N_A_c_105_n N_A_M1002_g N_A_c_94_n
+ N_A_c_107_n N_A_M1006_g N_A_M1004_g N_A_c_95_n N_A_c_96_n N_A_c_97_n
diff --git a/cells/or3/sky130_fd_sc_ls__or3_4.spice b/cells/or3/sky130_fd_sc_ls__or3_4.spice
index cc8d865..cd7456d 100644
--- a/cells/or3/sky130_fd_sc_ls__or3_4.spice
+++ b/cells/or3/sky130_fd_sc_ls__or3_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__or3_4.spice
-* Created: Fri Aug 28 13:58:34 2020
+* Created: Wed Sep 2 11:24:59 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/or3b/sky130_fd_sc_ls__or3b_1.lvs.report b/cells/or3b/sky130_fd_sc_ls__or3b_1.lvs.report
new file mode 100644
index 0000000..23918db
--- /dev/null
+++ b/cells/or3b/sky130_fd_sc_ls__or3b_1.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__or3b_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__or3b_1.sp ('sky130_fd_sc_ls__or3b_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/or3b/sky130_fd_sc_ls__or3b_1.spice ('sky130_fd_sc_ls__or3b_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:25:03 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__or3b_1 sky130_fd_sc_ls__or3b_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__or3b_1
+SOURCE CELL NAME: sky130_fd_sc_ls__or3b_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 12 12
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 10 10
+
+ Instances: 5 5 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 1 SMP3 (5 pins)
+ ------ ------
+ Total Inst: 8 8
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 5 5 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP3
+ ------- ------- --------- ---------
+ Total Inst: 8 8 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB C_N B A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/or3b/sky130_fd_sc_ls__or3b_1.pex.spice b/cells/or3b/sky130_fd_sc_ls__or3b_1.pex.spice
index 40811c5..0f5fed5 100644
--- a/cells/or3b/sky130_fd_sc_ls__or3b_1.pex.spice
+++ b/cells/or3b/sky130_fd_sc_ls__or3b_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__or3b_1.pex.spice
-* Created: Fri Aug 28 13:58:44 2020
+* Created: Wed Sep 2 11:25:06 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/or3b/sky130_fd_sc_ls__or3b_1.pxi.spice b/cells/or3b/sky130_fd_sc_ls__or3b_1.pxi.spice
index 619a2a2..81015fb 100644
--- a/cells/or3b/sky130_fd_sc_ls__or3b_1.pxi.spice
+++ b/cells/or3b/sky130_fd_sc_ls__or3b_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__or3b_1.pxi.spice
-* Created: Fri Aug 28 13:58:44 2020
+* Created: Wed Sep 2 11:25:06 2020
*
x_PM_SKY130_FD_SC_LS__OR3B_1%C_N N_C_N_c_77_n N_C_N_c_82_n N_C_N_c_83_n
+ N_C_N_M1007_g N_C_N_M1006_g N_C_N_c_79_n C_N C_N N_C_N_c_80_n N_C_N_c_81_n
diff --git a/cells/or3b/sky130_fd_sc_ls__or3b_1.spice b/cells/or3b/sky130_fd_sc_ls__or3b_1.spice
index a9fc770..04f1600 100644
--- a/cells/or3b/sky130_fd_sc_ls__or3b_1.spice
+++ b/cells/or3b/sky130_fd_sc_ls__or3b_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__or3b_1.spice
-* Created: Fri Aug 28 13:58:44 2020
+* Created: Wed Sep 2 11:25:06 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/or3b/sky130_fd_sc_ls__or3b_2.lvs.report b/cells/or3b/sky130_fd_sc_ls__or3b_2.lvs.report
new file mode 100644
index 0000000..7852f19
--- /dev/null
+++ b/cells/or3b/sky130_fd_sc_ls__or3b_2.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__or3b_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__or3b_2.sp ('sky130_fd_sc_ls__or3b_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/or3b/sky130_fd_sc_ls__or3b_2.spice ('sky130_fd_sc_ls__or3b_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:25:10 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__or3b_2 sky130_fd_sc_ls__or3b_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__or3b_2
+SOURCE CELL NAME: sky130_fd_sc_ls__or3b_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 12 12
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 10 10
+
+ Instances: 5 5 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 1 SMP3 (5 pins)
+ ------ ------
+ Total Inst: 8 8
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 5 5 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP3
+ ------- ------- --------- ---------
+ Total Inst: 8 8 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB C_N A B VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/or3b/sky130_fd_sc_ls__or3b_2.pex.spice b/cells/or3b/sky130_fd_sc_ls__or3b_2.pex.spice
index 81d925c..bf36385 100644
--- a/cells/or3b/sky130_fd_sc_ls__or3b_2.pex.spice
+++ b/cells/or3b/sky130_fd_sc_ls__or3b_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__or3b_2.pex.spice
-* Created: Fri Aug 28 13:59:01 2020
+* Created: Wed Sep 2 11:25:13 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/or3b/sky130_fd_sc_ls__or3b_2.pxi.spice b/cells/or3b/sky130_fd_sc_ls__or3b_2.pxi.spice
index bd03667..4b6f5b1 100644
--- a/cells/or3b/sky130_fd_sc_ls__or3b_2.pxi.spice
+++ b/cells/or3b/sky130_fd_sc_ls__or3b_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__or3b_2.pxi.spice
-* Created: Fri Aug 28 13:59:01 2020
+* Created: Wed Sep 2 11:25:13 2020
*
x_PM_SKY130_FD_SC_LS__OR3B_2%C_N N_C_N_c_68_n N_C_N_M1007_g N_C_N_M1004_g C_N
+ N_C_N_c_70_n PM_SKY130_FD_SC_LS__OR3B_2%C_N
diff --git a/cells/or3b/sky130_fd_sc_ls__or3b_2.spice b/cells/or3b/sky130_fd_sc_ls__or3b_2.spice
index 62f769e..62c7bed 100644
--- a/cells/or3b/sky130_fd_sc_ls__or3b_2.spice
+++ b/cells/or3b/sky130_fd_sc_ls__or3b_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__or3b_2.spice
-* Created: Fri Aug 28 13:59:01 2020
+* Created: Wed Sep 2 11:25:13 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/or3b/sky130_fd_sc_ls__or3b_4.lvs.report b/cells/or3b/sky130_fd_sc_ls__or3b_4.lvs.report
new file mode 100644
index 0000000..92173f9
--- /dev/null
+++ b/cells/or3b/sky130_fd_sc_ls__or3b_4.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__or3b_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__or3b_4.sp ('sky130_fd_sc_ls__or3b_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/or3b/sky130_fd_sc_ls__or3b_4.spice ('sky130_fd_sc_ls__or3b_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:25:17 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__or3b_4 sky130_fd_sc_ls__or3b_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__or3b_4
+SOURCE CELL NAME: sky130_fd_sc_ls__or3b_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 12 12
+
+ Instances: 8 8 MN (4 pins)
+ 11 11 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 20 19
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 10 10
+
+ Instances: 5 5 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 1 SMP3 (5 pins)
+ ------ ------
+ Total Inst: 8 8
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 5 5 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP3
+ ------- ------- --------- ---------
+ Total Inst: 8 8 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 14 layout mos transistors were reduced to 5.
+ 9 mos transistors were deleted by parallel reduction.
+ 14 source mos transistors were reduced to 5.
+ 9 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB C_N A B VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/or3b/sky130_fd_sc_ls__or3b_4.pex.spice b/cells/or3b/sky130_fd_sc_ls__or3b_4.pex.spice
index d2b09d7..4b91160 100644
--- a/cells/or3b/sky130_fd_sc_ls__or3b_4.pex.spice
+++ b/cells/or3b/sky130_fd_sc_ls__or3b_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__or3b_4.pex.spice
-* Created: Fri Aug 28 13:59:22 2020
+* Created: Wed Sep 2 11:25:20 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/or3b/sky130_fd_sc_ls__or3b_4.pxi.spice b/cells/or3b/sky130_fd_sc_ls__or3b_4.pxi.spice
index 7a4adfb..afd7fe7 100644
--- a/cells/or3b/sky130_fd_sc_ls__or3b_4.pxi.spice
+++ b/cells/or3b/sky130_fd_sc_ls__or3b_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__or3b_4.pxi.spice
-* Created: Fri Aug 28 13:59:22 2020
+* Created: Wed Sep 2 11:25:20 2020
*
x_PM_SKY130_FD_SC_LS__OR3B_4%C_N N_C_N_c_112_n N_C_N_c_113_n N_C_N_c_119_n
+ N_C_N_M1013_g N_C_N_M1010_g C_N N_C_N_c_115_n N_C_N_c_116_n N_C_N_c_117_n
diff --git a/cells/or3b/sky130_fd_sc_ls__or3b_4.spice b/cells/or3b/sky130_fd_sc_ls__or3b_4.spice
index 6449549..16dc82a 100644
--- a/cells/or3b/sky130_fd_sc_ls__or3b_4.spice
+++ b/cells/or3b/sky130_fd_sc_ls__or3b_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__or3b_4.spice
-* Created: Fri Aug 28 13:59:22 2020
+* Created: Wed Sep 2 11:25:20 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/or4/sky130_fd_sc_ls__or4_1.lvs.report b/cells/or4/sky130_fd_sc_ls__or4_1.lvs.report
new file mode 100644
index 0000000..be2ee71
--- /dev/null
+++ b/cells/or4/sky130_fd_sc_ls__or4_1.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__or4_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__or4_1.sp ('sky130_fd_sc_ls__or4_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/or4/sky130_fd_sc_ls__or4_1.spice ('sky130_fd_sc_ls__or4_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:25:24 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__or4_1 sky130_fd_sc_ls__or4_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__or4_1
+SOURCE CELL NAME: sky130_fd_sc_ls__or4_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 5 5 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMP4 (6 pins)
+ ------ ------
+ Total Inst: 7 7
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 5 5 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP4
+ ------- ------- --------- ---------
+ Total Inst: 7 7 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D C B A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/or4/sky130_fd_sc_ls__or4_1.pex.spice b/cells/or4/sky130_fd_sc_ls__or4_1.pex.spice
index 57449a1..db992b2 100644
--- a/cells/or4/sky130_fd_sc_ls__or4_1.pex.spice
+++ b/cells/or4/sky130_fd_sc_ls__or4_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__or4_1.pex.spice
-* Created: Fri Aug 28 13:59:33 2020
+* Created: Wed Sep 2 11:25:27 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/or4/sky130_fd_sc_ls__or4_1.pxi.spice b/cells/or4/sky130_fd_sc_ls__or4_1.pxi.spice
index 8896a84..d14a3ff 100644
--- a/cells/or4/sky130_fd_sc_ls__or4_1.pxi.spice
+++ b/cells/or4/sky130_fd_sc_ls__or4_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__or4_1.pxi.spice
-* Created: Fri Aug 28 13:59:33 2020
+* Created: Wed Sep 2 11:25:27 2020
*
x_PM_SKY130_FD_SC_LS__OR4_1%D N_D_M1002_g N_D_c_59_n N_D_M1000_g D N_D_c_60_n
+ PM_SKY130_FD_SC_LS__OR4_1%D
diff --git a/cells/or4/sky130_fd_sc_ls__or4_1.spice b/cells/or4/sky130_fd_sc_ls__or4_1.spice
index 1ace876..49e3ad8 100644
--- a/cells/or4/sky130_fd_sc_ls__or4_1.spice
+++ b/cells/or4/sky130_fd_sc_ls__or4_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__or4_1.spice
-* Created: Fri Aug 28 13:59:33 2020
+* Created: Wed Sep 2 11:25:27 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/or4/sky130_fd_sc_ls__or4_2.lvs.report b/cells/or4/sky130_fd_sc_ls__or4_2.lvs.report
new file mode 100644
index 0000000..4d6fdb8
--- /dev/null
+++ b/cells/or4/sky130_fd_sc_ls__or4_2.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__or4_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__or4_2.sp ('sky130_fd_sc_ls__or4_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/or4/sky130_fd_sc_ls__or4_2.spice ('sky130_fd_sc_ls__or4_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:25:31 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__or4_2 sky130_fd_sc_ls__or4_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__or4_2
+SOURCE CELL NAME: sky130_fd_sc_ls__or4_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 5 5 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMP4 (6 pins)
+ ------ ------
+ Total Inst: 7 7
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 5 5 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP4
+ ------- ------- --------- ---------
+ Total Inst: 7 7 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D C B A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/or4/sky130_fd_sc_ls__or4_2.pex.spice b/cells/or4/sky130_fd_sc_ls__or4_2.pex.spice
index 8ebfbdc..872aa58 100644
--- a/cells/or4/sky130_fd_sc_ls__or4_2.pex.spice
+++ b/cells/or4/sky130_fd_sc_ls__or4_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__or4_2.pex.spice
-* Created: Fri Aug 28 13:59:44 2020
+* Created: Wed Sep 2 11:25:34 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/or4/sky130_fd_sc_ls__or4_2.pxi.spice b/cells/or4/sky130_fd_sc_ls__or4_2.pxi.spice
index b4c6baf..f7c2fcb 100644
--- a/cells/or4/sky130_fd_sc_ls__or4_2.pxi.spice
+++ b/cells/or4/sky130_fd_sc_ls__or4_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__or4_2.pxi.spice
-* Created: Fri Aug 28 13:59:44 2020
+* Created: Wed Sep 2 11:25:34 2020
*
x_PM_SKY130_FD_SC_LS__OR4_2%D N_D_M1004_g N_D_c_67_n N_D_M1000_g D
+ PM_SKY130_FD_SC_LS__OR4_2%D
diff --git a/cells/or4/sky130_fd_sc_ls__or4_2.spice b/cells/or4/sky130_fd_sc_ls__or4_2.spice
index 0b153ea..09dd2af 100644
--- a/cells/or4/sky130_fd_sc_ls__or4_2.spice
+++ b/cells/or4/sky130_fd_sc_ls__or4_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__or4_2.spice
-* Created: Fri Aug 28 13:59:44 2020
+* Created: Wed Sep 2 11:25:34 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/or4/sky130_fd_sc_ls__or4_4.lvs.report b/cells/or4/sky130_fd_sc_ls__or4_4.lvs.report
new file mode 100644
index 0000000..1998aa1
--- /dev/null
+++ b/cells/or4/sky130_fd_sc_ls__or4_4.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__or4_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__or4_4.sp ('sky130_fd_sc_ls__or4_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/or4/sky130_fd_sc_ls__or4_4.spice ('sky130_fd_sc_ls__or4_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:25:38 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__or4_4 sky130_fd_sc_ls__or4_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__or4_4
+SOURCE CELL NAME: sky130_fd_sc_ls__or4_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 8 8 MN (4 pins)
+ 12 12 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 21 20
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 5 5 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMP4 (6 pins)
+ ------ ------
+ Total Inst: 7 7
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 5 5 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP4
+ ------- ------- --------- ---------
+ Total Inst: 7 7 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 16 layout mos transistors were reduced to 6.
+ 10 mos transistors were deleted by parallel reduction.
+ 16 source mos transistors were reduced to 6.
+ 10 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B A C D VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/or4/sky130_fd_sc_ls__or4_4.pex.spice b/cells/or4/sky130_fd_sc_ls__or4_4.pex.spice
index 007dbb1..375256a 100644
--- a/cells/or4/sky130_fd_sc_ls__or4_4.pex.spice
+++ b/cells/or4/sky130_fd_sc_ls__or4_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__or4_4.pex.spice
-* Created: Fri Aug 28 13:59:54 2020
+* Created: Wed Sep 2 11:25:41 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/or4/sky130_fd_sc_ls__or4_4.pxi.spice b/cells/or4/sky130_fd_sc_ls__or4_4.pxi.spice
index 8ed25a2..2307ff3 100644
--- a/cells/or4/sky130_fd_sc_ls__or4_4.pxi.spice
+++ b/cells/or4/sky130_fd_sc_ls__or4_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__or4_4.pxi.spice
-* Created: Fri Aug 28 13:59:54 2020
+* Created: Wed Sep 2 11:25:41 2020
*
x_PM_SKY130_FD_SC_LS__OR4_4%A_83_264# N_A_83_264#_M1003_d N_A_83_264#_M1013_d
+ N_A_83_264#_M1002_s N_A_83_264#_c_120_n N_A_83_264#_M1001_g
diff --git a/cells/or4/sky130_fd_sc_ls__or4_4.spice b/cells/or4/sky130_fd_sc_ls__or4_4.spice
index 207ae0c..8549893 100644
--- a/cells/or4/sky130_fd_sc_ls__or4_4.spice
+++ b/cells/or4/sky130_fd_sc_ls__or4_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__or4_4.spice
-* Created: Fri Aug 28 13:59:54 2020
+* Created: Wed Sep 2 11:25:41 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/or4b/sky130_fd_sc_ls__or4b_1.lvs.report b/cells/or4b/sky130_fd_sc_ls__or4b_1.lvs.report
new file mode 100644
index 0000000..bdfecd3
--- /dev/null
+++ b/cells/or4b/sky130_fd_sc_ls__or4b_1.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__or4b_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__or4b_1.sp ('sky130_fd_sc_ls__or4b_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/or4b/sky130_fd_sc_ls__or4b_1.spice ('sky130_fd_sc_ls__or4b_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:25:45 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__or4b_1 sky130_fd_sc_ls__or4b_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__or4b_1
+SOURCE CELL NAME: sky130_fd_sc_ls__or4b_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 14 14
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 11 11
+
+ Instances: 6 6 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 1 SMP4 (6 pins)
+ ------ ------
+ Total Inst: 9 9
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 6 6 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP4
+ ------- ------- --------- ---------
+ Total Inst: 9 9 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D_N C B A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/or4b/sky130_fd_sc_ls__or4b_1.pex.spice b/cells/or4b/sky130_fd_sc_ls__or4b_1.pex.spice
index 75f432d..f3a2ce2 100644
--- a/cells/or4b/sky130_fd_sc_ls__or4b_1.pex.spice
+++ b/cells/or4b/sky130_fd_sc_ls__or4b_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__or4b_1.pex.spice
-* Created: Fri Aug 28 14:00:11 2020
+* Created: Wed Sep 2 11:25:48 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/or4b/sky130_fd_sc_ls__or4b_1.pxi.spice b/cells/or4b/sky130_fd_sc_ls__or4b_1.pxi.spice
index de46f47..b2cb246 100644
--- a/cells/or4b/sky130_fd_sc_ls__or4b_1.pxi.spice
+++ b/cells/or4b/sky130_fd_sc_ls__or4b_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__or4b_1.pxi.spice
-* Created: Fri Aug 28 14:00:11 2020
+* Created: Wed Sep 2 11:25:48 2020
*
x_PM_SKY130_FD_SC_LS__OR4B_1%D_N N_D_N_M1008_g N_D_N_c_81_n N_D_N_c_84_n
+ N_D_N_c_85_n N_D_N_M1006_g D_N N_D_N_c_82_n PM_SKY130_FD_SC_LS__OR4B_1%D_N
diff --git a/cells/or4b/sky130_fd_sc_ls__or4b_1.spice b/cells/or4b/sky130_fd_sc_ls__or4b_1.spice
index e66a4b0..dceffaa 100644
--- a/cells/or4b/sky130_fd_sc_ls__or4b_1.spice
+++ b/cells/or4b/sky130_fd_sc_ls__or4b_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__or4b_1.spice
-* Created: Fri Aug 28 14:00:11 2020
+* Created: Wed Sep 2 11:25:48 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/or4b/sky130_fd_sc_ls__or4b_2.lvs.report b/cells/or4b/sky130_fd_sc_ls__or4b_2.lvs.report
new file mode 100644
index 0000000..f7e0cce
--- /dev/null
+++ b/cells/or4b/sky130_fd_sc_ls__or4b_2.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__or4b_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__or4b_2.sp ('sky130_fd_sc_ls__or4b_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/or4b/sky130_fd_sc_ls__or4b_2.spice ('sky130_fd_sc_ls__or4b_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:25:52 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__or4b_2 sky130_fd_sc_ls__or4b_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__or4b_2
+SOURCE CELL NAME: sky130_fd_sc_ls__or4b_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 14 14
+
+ Instances: 7 7 MN (4 pins)
+ 7 7 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 15 14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 11 11
+
+ Instances: 6 6 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 1 SMP4 (6 pins)
+ ------ ------
+ Total Inst: 9 9
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 6 6 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP4
+ ------- ------- --------- ---------
+ Total Inst: 9 9 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D_N A B C VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/or4b/sky130_fd_sc_ls__or4b_2.pex.spice b/cells/or4b/sky130_fd_sc_ls__or4b_2.pex.spice
index 831a676..392d68d 100644
--- a/cells/or4b/sky130_fd_sc_ls__or4b_2.pex.spice
+++ b/cells/or4b/sky130_fd_sc_ls__or4b_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__or4b_2.pex.spice
-* Created: Fri Aug 28 14:00:32 2020
+* Created: Wed Sep 2 11:25:55 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/or4b/sky130_fd_sc_ls__or4b_2.pxi.spice b/cells/or4b/sky130_fd_sc_ls__or4b_2.pxi.spice
index 50e21fd..af58f7c 100644
--- a/cells/or4b/sky130_fd_sc_ls__or4b_2.pxi.spice
+++ b/cells/or4b/sky130_fd_sc_ls__or4b_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__or4b_2.pxi.spice
-* Created: Fri Aug 28 14:00:32 2020
+* Created: Wed Sep 2 11:25:55 2020
*
x_PM_SKY130_FD_SC_LS__OR4B_2%D_N N_D_N_c_80_n N_D_N_M1005_g N_D_N_M1009_g D_N
+ N_D_N_c_82_n PM_SKY130_FD_SC_LS__OR4B_2%D_N
diff --git a/cells/or4b/sky130_fd_sc_ls__or4b_2.spice b/cells/or4b/sky130_fd_sc_ls__or4b_2.spice
index 4c3f8ee..005c3a8 100644
--- a/cells/or4b/sky130_fd_sc_ls__or4b_2.spice
+++ b/cells/or4b/sky130_fd_sc_ls__or4b_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__or4b_2.spice
-* Created: Fri Aug 28 14:00:32 2020
+* Created: Wed Sep 2 11:25:55 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/or4b/sky130_fd_sc_ls__or4b_4.lvs.report b/cells/or4b/sky130_fd_sc_ls__or4b_4.lvs.report
new file mode 100644
index 0000000..26470ec
--- /dev/null
+++ b/cells/or4b/sky130_fd_sc_ls__or4b_4.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__or4b_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__or4b_4.sp ('sky130_fd_sc_ls__or4b_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/or4b/sky130_fd_sc_ls__or4b_4.spice ('sky130_fd_sc_ls__or4b_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:25:59 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__or4b_4 sky130_fd_sc_ls__or4b_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__or4b_4
+SOURCE CELL NAME: sky130_fd_sc_ls__or4b_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 14 14
+
+ Instances: 9 9 MN (4 pins)
+ 13 13 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 23 22
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 11 11
+
+ Instances: 6 6 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 1 SMP4 (6 pins)
+ ------ ------
+ Total Inst: 9 9
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 6 6 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP4
+ ------- ------- --------- ---------
+ Total Inst: 9 9 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 16 layout mos transistors were reduced to 6.
+ 10 mos transistors were deleted by parallel reduction.
+ 16 source mos transistors were reduced to 6.
+ 10 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B A C D_N VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/or4b/sky130_fd_sc_ls__or4b_4.pex.spice b/cells/or4b/sky130_fd_sc_ls__or4b_4.pex.spice
index 7cd8fb9..3af48aa 100644
--- a/cells/or4b/sky130_fd_sc_ls__or4b_4.pex.spice
+++ b/cells/or4b/sky130_fd_sc_ls__or4b_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__or4b_4.pex.spice
-* Created: Fri Aug 28 14:00:43 2020
+* Created: Wed Sep 2 11:26:03 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/or4b/sky130_fd_sc_ls__or4b_4.pxi.spice b/cells/or4b/sky130_fd_sc_ls__or4b_4.pxi.spice
index 2b02138..81d34e7 100644
--- a/cells/or4b/sky130_fd_sc_ls__or4b_4.pxi.spice
+++ b/cells/or4b/sky130_fd_sc_ls__or4b_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__or4b_4.pxi.spice
-* Created: Fri Aug 28 14:00:43 2020
+* Created: Wed Sep 2 11:26:03 2020
*
x_PM_SKY130_FD_SC_LS__OR4B_4%B N_B_c_130_n N_B_M1018_g N_B_c_140_n N_B_M1004_g
+ N_B_c_131_n N_B_c_142_n N_B_M1015_g N_B_c_132_n N_B_c_133_n N_B_c_134_n B B
diff --git a/cells/or4b/sky130_fd_sc_ls__or4b_4.spice b/cells/or4b/sky130_fd_sc_ls__or4b_4.spice
index 4db100a..b0cdcbd 100644
--- a/cells/or4b/sky130_fd_sc_ls__or4b_4.spice
+++ b/cells/or4b/sky130_fd_sc_ls__or4b_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__or4b_4.spice
-* Created: Fri Aug 28 14:00:43 2020
+* Created: Wed Sep 2 11:26:03 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/or4bb/sky130_fd_sc_ls__or4bb_1.lvs.report b/cells/or4bb/sky130_fd_sc_ls__or4bb_1.lvs.report
new file mode 100644
index 0000000..09f4d90
--- /dev/null
+++ b/cells/or4bb/sky130_fd_sc_ls__or4bb_1.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__or4bb_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__or4bb_1.sp ('sky130_fd_sc_ls__or4bb_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/or4bb/sky130_fd_sc_ls__or4bb_1.spice ('sky130_fd_sc_ls__or4bb_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:26:06 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__or4bb_1 sky130_fd_sc_ls__or4bb_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__or4bb_1
+SOURCE CELL NAME: sky130_fd_sc_ls__or4bb_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 15 15
+
+ Instances: 7 7 MN (4 pins)
+ 7 7 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 15 14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 12 12
+
+ Instances: 7 7 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 1 SMP4 (6 pins)
+ ------ ------
+ Total Inst: 11 11
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 12 12 0 0
+
+ Instances: 7 7 0 0 MN(NSHORT)
+ 3 3 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP4
+ ------- ------- --------- ---------
+ Total Inst: 11 11 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB C_N D_N B A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/or4bb/sky130_fd_sc_ls__or4bb_1.pex.spice b/cells/or4bb/sky130_fd_sc_ls__or4bb_1.pex.spice
index fd3a2ef..2dd4128 100644
--- a/cells/or4bb/sky130_fd_sc_ls__or4bb_1.pex.spice
+++ b/cells/or4bb/sky130_fd_sc_ls__or4bb_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__or4bb_1.pex.spice
-* Created: Fri Aug 28 14:00:54 2020
+* Created: Wed Sep 2 11:26:10 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/or4bb/sky130_fd_sc_ls__or4bb_1.pxi.spice b/cells/or4bb/sky130_fd_sc_ls__or4bb_1.pxi.spice
index 2911d88..25f6726 100644
--- a/cells/or4bb/sky130_fd_sc_ls__or4bb_1.pxi.spice
+++ b/cells/or4bb/sky130_fd_sc_ls__or4bb_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__or4bb_1.pxi.spice
-* Created: Fri Aug 28 14:00:54 2020
+* Created: Wed Sep 2 11:26:10 2020
*
x_PM_SKY130_FD_SC_LS__OR4BB_1%C_N N_C_N_c_93_n N_C_N_c_98_n N_C_N_M1008_g
+ N_C_N_M1003_g C_N N_C_N_c_95_n N_C_N_c_96_n PM_SKY130_FD_SC_LS__OR4BB_1%C_N
diff --git a/cells/or4bb/sky130_fd_sc_ls__or4bb_1.spice b/cells/or4bb/sky130_fd_sc_ls__or4bb_1.spice
index 96c2dbc..a46068c 100644
--- a/cells/or4bb/sky130_fd_sc_ls__or4bb_1.spice
+++ b/cells/or4bb/sky130_fd_sc_ls__or4bb_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__or4bb_1.spice
-* Created: Fri Aug 28 14:00:54 2020
+* Created: Wed Sep 2 11:26:10 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/or4bb/sky130_fd_sc_ls__or4bb_2.lvs.report b/cells/or4bb/sky130_fd_sc_ls__or4bb_2.lvs.report
new file mode 100644
index 0000000..76430bf
--- /dev/null
+++ b/cells/or4bb/sky130_fd_sc_ls__or4bb_2.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__or4bb_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__or4bb_2.sp ('sky130_fd_sc_ls__or4bb_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/or4bb/sky130_fd_sc_ls__or4bb_2.spice ('sky130_fd_sc_ls__or4bb_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:26:14 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__or4bb_2 sky130_fd_sc_ls__or4bb_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__or4bb_2
+SOURCE CELL NAME: sky130_fd_sc_ls__or4bb_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 15 15
+
+ Instances: 8 8 MN (4 pins)
+ 8 8 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 17 16
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 12 12
+
+ Instances: 7 7 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 1 SMP4 (6 pins)
+ ------ ------
+ Total Inst: 11 11
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 12 12 0 0
+
+ Instances: 7 7 0 0 MN(NSHORT)
+ 3 3 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP4
+ ------- ------- --------- ---------
+ Total Inst: 11 11 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D_N B A C_N VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/or4bb/sky130_fd_sc_ls__or4bb_2.pex.spice b/cells/or4bb/sky130_fd_sc_ls__or4bb_2.pex.spice
index 915e97b..7911d05 100644
--- a/cells/or4bb/sky130_fd_sc_ls__or4bb_2.pex.spice
+++ b/cells/or4bb/sky130_fd_sc_ls__or4bb_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__or4bb_2.pex.spice
-* Created: Fri Aug 28 14:01:06 2020
+* Created: Wed Sep 2 11:26:17 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/or4bb/sky130_fd_sc_ls__or4bb_2.pxi.spice b/cells/or4bb/sky130_fd_sc_ls__or4bb_2.pxi.spice
index a29fed7..e331457 100644
--- a/cells/or4bb/sky130_fd_sc_ls__or4bb_2.pxi.spice
+++ b/cells/or4bb/sky130_fd_sc_ls__or4bb_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__or4bb_2.pxi.spice
-* Created: Fri Aug 28 14:01:06 2020
+* Created: Wed Sep 2 11:26:17 2020
*
x_PM_SKY130_FD_SC_LS__OR4BB_2%D_N N_D_N_c_96_n N_D_N_c_100_n N_D_N_c_101_n
+ N_D_N_M1010_g N_D_N_c_97_n N_D_N_M1004_g D_N N_D_N_c_98_n
diff --git a/cells/or4bb/sky130_fd_sc_ls__or4bb_2.spice b/cells/or4bb/sky130_fd_sc_ls__or4bb_2.spice
index 1daa8ca..8a8e179 100644
--- a/cells/or4bb/sky130_fd_sc_ls__or4bb_2.spice
+++ b/cells/or4bb/sky130_fd_sc_ls__or4bb_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__or4bb_2.spice
-* Created: Fri Aug 28 14:01:06 2020
+* Created: Wed Sep 2 11:26:17 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/or4bb/sky130_fd_sc_ls__or4bb_4.lvs.report b/cells/or4bb/sky130_fd_sc_ls__or4bb_4.lvs.report
new file mode 100644
index 0000000..24d9203
--- /dev/null
+++ b/cells/or4bb/sky130_fd_sc_ls__or4bb_4.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__or4bb_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__or4bb_4.sp ('sky130_fd_sc_ls__or4bb_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/or4bb/sky130_fd_sc_ls__or4bb_4.spice ('sky130_fd_sc_ls__or4bb_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:26:21 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__or4bb_4 sky130_fd_sc_ls__or4bb_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__or4bb_4
+SOURCE CELL NAME: sky130_fd_sc_ls__or4bb_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 15 15
+
+ Instances: 10 10 MN (4 pins)
+ 14 14 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 25 24
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 12 12
+
+ Instances: 7 7 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 1 SMP4 (6 pins)
+ ------ ------
+ Total Inst: 11 11
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 12 12 0 0
+
+ Instances: 7 7 0 0 MN(NSHORT)
+ 3 3 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP4
+ ------- ------- --------- ---------
+ Total Inst: 11 11 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 16 layout mos transistors were reduced to 6.
+ 10 mos transistors were deleted by parallel reduction.
+ 16 source mos transistors were reduced to 6.
+ 10 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D_N C_N B A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/or4bb/sky130_fd_sc_ls__or4bb_4.pex.spice b/cells/or4bb/sky130_fd_sc_ls__or4bb_4.pex.spice
index d625569..4eecac6 100644
--- a/cells/or4bb/sky130_fd_sc_ls__or4bb_4.pex.spice
+++ b/cells/or4bb/sky130_fd_sc_ls__or4bb_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__or4bb_4.pex.spice
-* Created: Fri Aug 28 14:01:22 2020
+* Created: Wed Sep 2 11:26:24 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/or4bb/sky130_fd_sc_ls__or4bb_4.pxi.spice b/cells/or4bb/sky130_fd_sc_ls__or4bb_4.pxi.spice
index f754048..271afb0 100644
--- a/cells/or4bb/sky130_fd_sc_ls__or4bb_4.pxi.spice
+++ b/cells/or4bb/sky130_fd_sc_ls__or4bb_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__or4bb_4.pxi.spice
-* Created: Fri Aug 28 14:01:22 2020
+* Created: Wed Sep 2 11:26:24 2020
*
x_PM_SKY130_FD_SC_LS__OR4BB_4%D_N N_D_N_M1006_g N_D_N_c_139_n N_D_N_M1015_g D_N
+ N_D_N_c_140_n PM_SKY130_FD_SC_LS__OR4BB_4%D_N
diff --git a/cells/or4bb/sky130_fd_sc_ls__or4bb_4.spice b/cells/or4bb/sky130_fd_sc_ls__or4bb_4.spice
index 498d3d3..61e16ee 100644
--- a/cells/or4bb/sky130_fd_sc_ls__or4bb_4.spice
+++ b/cells/or4bb/sky130_fd_sc_ls__or4bb_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__or4bb_4.spice
-* Created: Fri Aug 28 14:01:22 2020
+* Created: Wed Sep 2 11:26:24 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/sdfbbn/sky130_fd_sc_ls__sdfbbn_1.lvs.report b/cells/sdfbbn/sky130_fd_sc_ls__sdfbbn_1.lvs.report
new file mode 100644
index 0000000..9fe6164
--- /dev/null
+++ b/cells/sdfbbn/sky130_fd_sc_ls__sdfbbn_1.lvs.report
@@ -0,0 +1,470 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__sdfbbn_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__sdfbbn_1.sp ('sky130_fd_sc_ls__sdfbbn_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/sdfbbn/sky130_fd_sc_ls__sdfbbn_1.spice ('sky130_fd_sc_ls__sdfbbn_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:26:28 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__sdfbbn_1 sky130_fd_sc_ls__sdfbbn_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__sdfbbn_1
+SOURCE CELL NAME: sky130_fd_sc_ls__sdfbbn_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 12 12
+
+ Nets: 36 36
+
+ Instances: 24 24 MN (4 pins)
+ 24 24 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 49 48
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 12 12
+
+ Nets: 22 22
+
+ Instances: 8 8 MN (4 pins)
+ 10 10 MP (4 pins)
+ 5 5 SMN2 (4 pins)
+ 7 7 SMP2 (4 pins)
+ 2 2 SPMN_2_1 (5 pins)
+ ------ ------
+ Total Inst: 32 32
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 12 12 0 0
+
+ Nets: 22 22 0 0
+
+ Instances: 8 8 0 0 MN(NSHORT)
+ 10 10 0 0 MP(PHIGHVT)
+ 5 5 0 0 SMN2
+ 7 7 0 0 SMP2
+ 2 2 0 0 SPMN_2_1
+ ------- ------- --------- ---------
+ Total Inst: 32 32 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB SCD D SCE CLK_N SET_B RESET_B VPWR Q_N Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/sdfbbn/sky130_fd_sc_ls__sdfbbn_1.pex.spice b/cells/sdfbbn/sky130_fd_sc_ls__sdfbbn_1.pex.spice
index 17d4eba..439bf6b 100644
--- a/cells/sdfbbn/sky130_fd_sc_ls__sdfbbn_1.pex.spice
+++ b/cells/sdfbbn/sky130_fd_sc_ls__sdfbbn_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__sdfbbn_1.pex.spice
-* Created: Fri Aug 28 14:01:42 2020
+* Created: Wed Sep 2 11:26:31 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/sdfbbn/sky130_fd_sc_ls__sdfbbn_1.pxi.spice b/cells/sdfbbn/sky130_fd_sc_ls__sdfbbn_1.pxi.spice
index 0930290..4bb64a4 100644
--- a/cells/sdfbbn/sky130_fd_sc_ls__sdfbbn_1.pxi.spice
+++ b/cells/sdfbbn/sky130_fd_sc_ls__sdfbbn_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__sdfbbn_1.pxi.spice
-* Created: Fri Aug 28 14:01:42 2020
+* Created: Wed Sep 2 11:26:31 2020
*
x_PM_SKY130_FD_SC_LS__SDFBBN_1%SCD N_SCD_c_375_n N_SCD_c_380_n N_SCD_c_381_n
+ N_SCD_M1025_g N_SCD_M1004_g N_SCD_c_382_n SCD N_SCD_c_377_n N_SCD_c_378_n
diff --git a/cells/sdfbbn/sky130_fd_sc_ls__sdfbbn_1.spice b/cells/sdfbbn/sky130_fd_sc_ls__sdfbbn_1.spice
index e9cc411..1fdb99c 100644
--- a/cells/sdfbbn/sky130_fd_sc_ls__sdfbbn_1.spice
+++ b/cells/sdfbbn/sky130_fd_sc_ls__sdfbbn_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__sdfbbn_1.spice
-* Created: Fri Aug 28 14:01:42 2020
+* Created: Wed Sep 2 11:26:31 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/sdfbbn/sky130_fd_sc_ls__sdfbbn_2.lvs.report b/cells/sdfbbn/sky130_fd_sc_ls__sdfbbn_2.lvs.report
new file mode 100644
index 0000000..d7eddf2
--- /dev/null
+++ b/cells/sdfbbn/sky130_fd_sc_ls__sdfbbn_2.lvs.report
@@ -0,0 +1,475 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__sdfbbn_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__sdfbbn_2.sp ('sky130_fd_sc_ls__sdfbbn_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/sdfbbn/sky130_fd_sc_ls__sdfbbn_2.spice ('sky130_fd_sc_ls__sdfbbn_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:26:35 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__sdfbbn_2 sky130_fd_sc_ls__sdfbbn_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__sdfbbn_2
+SOURCE CELL NAME: sky130_fd_sc_ls__sdfbbn_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 12 12
+
+ Nets: 36 36
+
+ Instances: 26 26 MN (4 pins)
+ 26 26 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 53 52
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 12 12
+
+ Nets: 22 22
+
+ Instances: 8 8 MN (4 pins)
+ 10 10 MP (4 pins)
+ 5 5 SMN2 (4 pins)
+ 7 7 SMP2 (4 pins)
+ 2 2 SPMN_2_1 (5 pins)
+ ------ ------
+ Total Inst: 32 32
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 12 12 0 0
+
+ Nets: 22 22 0 0
+
+ Instances: 8 8 0 0 MN(NSHORT)
+ 10 10 0 0 MP(PHIGHVT)
+ 5 5 0 0 SMN2
+ 7 7 0 0 SMP2
+ 2 2 0 0 SPMN_2_1
+ ------- ------- --------- ---------
+ Total Inst: 32 32 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 8 layout mos transistors were reduced to 4.
+ 4 mos transistors were deleted by parallel reduction.
+ 8 source mos transistors were reduced to 4.
+ 4 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB SCD D SCE CLK_N SET_B RESET_B VPWR Q_N Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/sdfbbn/sky130_fd_sc_ls__sdfbbn_2.pex.spice b/cells/sdfbbn/sky130_fd_sc_ls__sdfbbn_2.pex.spice
index 07e4cc6..f4c40bb 100644
--- a/cells/sdfbbn/sky130_fd_sc_ls__sdfbbn_2.pex.spice
+++ b/cells/sdfbbn/sky130_fd_sc_ls__sdfbbn_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__sdfbbn_2.pex.spice
-* Created: Fri Aug 28 14:01:53 2020
+* Created: Wed Sep 2 11:26:39 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/sdfbbn/sky130_fd_sc_ls__sdfbbn_2.pxi.spice b/cells/sdfbbn/sky130_fd_sc_ls__sdfbbn_2.pxi.spice
index 5538ec9..fcbae50 100644
--- a/cells/sdfbbn/sky130_fd_sc_ls__sdfbbn_2.pxi.spice
+++ b/cells/sdfbbn/sky130_fd_sc_ls__sdfbbn_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__sdfbbn_2.pxi.spice
-* Created: Fri Aug 28 14:01:53 2020
+* Created: Wed Sep 2 11:26:39 2020
*
x_PM_SKY130_FD_SC_LS__SDFBBN_2%SCD N_SCD_c_377_n N_SCD_c_382_n N_SCD_M1028_g
+ N_SCD_M1004_g SCD SCD N_SCD_c_378_n N_SCD_c_379_n N_SCD_c_380_n
diff --git a/cells/sdfbbn/sky130_fd_sc_ls__sdfbbn_2.spice b/cells/sdfbbn/sky130_fd_sc_ls__sdfbbn_2.spice
index 9bd1736..0ce7085 100644
--- a/cells/sdfbbn/sky130_fd_sc_ls__sdfbbn_2.spice
+++ b/cells/sdfbbn/sky130_fd_sc_ls__sdfbbn_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__sdfbbn_2.spice
-* Created: Fri Aug 28 14:01:53 2020
+* Created: Wed Sep 2 11:26:39 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/sdfbbp/sky130_fd_sc_ls__sdfbbp_1.lvs.report b/cells/sdfbbp/sky130_fd_sc_ls__sdfbbp_1.lvs.report
new file mode 100644
index 0000000..9dd35c6
--- /dev/null
+++ b/cells/sdfbbp/sky130_fd_sc_ls__sdfbbp_1.lvs.report
@@ -0,0 +1,470 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__sdfbbp_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__sdfbbp_1.sp ('sky130_fd_sc_ls__sdfbbp_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/sdfbbp/sky130_fd_sc_ls__sdfbbp_1.spice ('sky130_fd_sc_ls__sdfbbp_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:26:42 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__sdfbbp_1 sky130_fd_sc_ls__sdfbbp_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__sdfbbp_1
+SOURCE CELL NAME: sky130_fd_sc_ls__sdfbbp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 12 12
+
+ Nets: 36 36
+
+ Instances: 24 24 MN (4 pins)
+ 24 24 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 49 48
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 12 12
+
+ Nets: 22 22
+
+ Instances: 8 8 MN (4 pins)
+ 10 10 MP (4 pins)
+ 5 5 SMN2 (4 pins)
+ 7 7 SMP2 (4 pins)
+ 2 2 SPMN_2_1 (5 pins)
+ ------ ------
+ Total Inst: 32 32
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 12 12 0 0
+
+ Nets: 22 22 0 0
+
+ Instances: 8 8 0 0 MN(NSHORT)
+ 10 10 0 0 MP(PHIGHVT)
+ 5 5 0 0 SMN2
+ 7 7 0 0 SMP2
+ 2 2 0 0 SPMN_2_1
+ ------- ------- --------- ---------
+ Total Inst: 32 32 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB SCD D SCE CLK SET_B RESET_B VPWR Q_N Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/sdfbbp/sky130_fd_sc_ls__sdfbbp_1.pex.spice b/cells/sdfbbp/sky130_fd_sc_ls__sdfbbp_1.pex.spice
index 4e30853..9c4ef54 100644
--- a/cells/sdfbbp/sky130_fd_sc_ls__sdfbbp_1.pex.spice
+++ b/cells/sdfbbp/sky130_fd_sc_ls__sdfbbp_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__sdfbbp_1.pex.spice
-* Created: Fri Aug 28 14:02:05 2020
+* Created: Wed Sep 2 11:26:46 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/sdfbbp/sky130_fd_sc_ls__sdfbbp_1.pxi.spice b/cells/sdfbbp/sky130_fd_sc_ls__sdfbbp_1.pxi.spice
index 2464ccc..fe3fd6e 100644
--- a/cells/sdfbbp/sky130_fd_sc_ls__sdfbbp_1.pxi.spice
+++ b/cells/sdfbbp/sky130_fd_sc_ls__sdfbbp_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__sdfbbp_1.pxi.spice
-* Created: Fri Aug 28 14:02:05 2020
+* Created: Wed Sep 2 11:26:46 2020
*
x_PM_SKY130_FD_SC_LS__SDFBBP_1%SCD N_SCD_c_329_n N_SCD_c_334_n N_SCD_M1026_g
+ N_SCD_M1006_g SCD SCD N_SCD_c_330_n N_SCD_c_331_n N_SCD_c_332_n
diff --git a/cells/sdfbbp/sky130_fd_sc_ls__sdfbbp_1.spice b/cells/sdfbbp/sky130_fd_sc_ls__sdfbbp_1.spice
index a9590f9..99bf87d 100644
--- a/cells/sdfbbp/sky130_fd_sc_ls__sdfbbp_1.spice
+++ b/cells/sdfbbp/sky130_fd_sc_ls__sdfbbp_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__sdfbbp_1.spice
-* Created: Fri Aug 28 14:02:05 2020
+* Created: Wed Sep 2 11:26:46 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/sdfrbp/sky130_fd_sc_ls__sdfrbp_1.lvs.report b/cells/sdfrbp/sky130_fd_sc_ls__sdfrbp_1.lvs.report
new file mode 100644
index 0000000..796bcde
--- /dev/null
+++ b/cells/sdfrbp/sky130_fd_sc_ls__sdfrbp_1.lvs.report
@@ -0,0 +1,472 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__sdfrbp_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__sdfrbp_1.sp ('sky130_fd_sc_ls__sdfrbp_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/sdfrbp/sky130_fd_sc_ls__sdfrbp_1.spice ('sky130_fd_sc_ls__sdfrbp_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:26:50 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__sdfrbp_1 sky130_fd_sc_ls__sdfrbp_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__sdfrbp_1
+SOURCE CELL NAME: sky130_fd_sc_ls__sdfrbp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 11 11
+
+ Nets: 31 31
+
+ Instances: 21 21 MN (4 pins)
+ 21 21 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 43 42
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 11 11
+
+ Nets: 20 20
+
+ Instances: 9 9 MN (4 pins)
+ 13 13 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ 4 4 SMP2 (4 pins)
+ 1 1 SPMN((2+2)*1) (7 pins)
+ ------ ------
+ Total Inst: 30 30
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 11 11 0 0
+
+ Nets: 20 20 0 0
+
+ Instances: 9 9 0 0 MN(NSHORT)
+ 13 13 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ 1 1 0 0 SMN3
+ 4 4 0 0 SMP2
+ 1 1 0 0 SPMN((2+2)*1)
+ ------- ------- --------- ---------
+ Total Inst: 30 30 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB SCE D SCD CLK RESET_B VPWR Q_N Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/sdfrbp/sky130_fd_sc_ls__sdfrbp_1.pex.spice b/cells/sdfrbp/sky130_fd_sc_ls__sdfrbp_1.pex.spice
index bfe566c..468bd4b 100644
--- a/cells/sdfrbp/sky130_fd_sc_ls__sdfrbp_1.pex.spice
+++ b/cells/sdfrbp/sky130_fd_sc_ls__sdfrbp_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__sdfrbp_1.pex.spice
-* Created: Fri Aug 28 14:02:22 2020
+* Created: Wed Sep 2 11:26:54 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/sdfrbp/sky130_fd_sc_ls__sdfrbp_1.pxi.spice b/cells/sdfrbp/sky130_fd_sc_ls__sdfrbp_1.pxi.spice
index 7ae2b69..cb9b326 100644
--- a/cells/sdfrbp/sky130_fd_sc_ls__sdfrbp_1.pxi.spice
+++ b/cells/sdfrbp/sky130_fd_sc_ls__sdfrbp_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__sdfrbp_1.pxi.spice
-* Created: Fri Aug 28 14:02:22 2020
+* Created: Wed Sep 2 11:26:54 2020
*
x_PM_SKY130_FD_SC_LS__SDFRBP_1%A_27_74# N_A_27_74#_M1032_s N_A_27_74#_M1026_s
+ N_A_27_74#_M1008_g N_A_27_74#_c_304_n N_A_27_74#_M1019_g N_A_27_74#_c_299_n
diff --git a/cells/sdfrbp/sky130_fd_sc_ls__sdfrbp_1.spice b/cells/sdfrbp/sky130_fd_sc_ls__sdfrbp_1.spice
index 8e9b453..dc2c587 100644
--- a/cells/sdfrbp/sky130_fd_sc_ls__sdfrbp_1.spice
+++ b/cells/sdfrbp/sky130_fd_sc_ls__sdfrbp_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__sdfrbp_1.spice
-* Created: Fri Aug 28 14:02:22 2020
+* Created: Wed Sep 2 11:26:54 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/sdfrbp/sky130_fd_sc_ls__sdfrbp_2.lvs.report b/cells/sdfrbp/sky130_fd_sc_ls__sdfrbp_2.lvs.report
new file mode 100644
index 0000000..40fa8ec
--- /dev/null
+++ b/cells/sdfrbp/sky130_fd_sc_ls__sdfrbp_2.lvs.report
@@ -0,0 +1,477 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__sdfrbp_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__sdfrbp_2.sp ('sky130_fd_sc_ls__sdfrbp_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/sdfrbp/sky130_fd_sc_ls__sdfrbp_2.spice ('sky130_fd_sc_ls__sdfrbp_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:26:57 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__sdfrbp_2 sky130_fd_sc_ls__sdfrbp_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__sdfrbp_2
+SOURCE CELL NAME: sky130_fd_sc_ls__sdfrbp_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 11 11
+
+ Nets: 31 31
+
+ Instances: 23 23 MN (4 pins)
+ 23 23 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 47 46
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 11 11
+
+ Nets: 20 20
+
+ Instances: 9 9 MN (4 pins)
+ 13 13 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ 4 4 SMP2 (4 pins)
+ 1 1 SPMN((2+2)*1) (7 pins)
+ ------ ------
+ Total Inst: 30 30
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 11 11 0 0
+
+ Nets: 20 20 0 0
+
+ Instances: 9 9 0 0 MN(NSHORT)
+ 13 13 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ 1 1 0 0 SMN3
+ 4 4 0 0 SMP2
+ 1 1 0 0 SPMN((2+2)*1)
+ ------- ------- --------- ---------
+ Total Inst: 30 30 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 8 layout mos transistors were reduced to 4.
+ 4 mos transistors were deleted by parallel reduction.
+ 8 source mos transistors were reduced to 4.
+ 4 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB SCE D SCD CLK RESET_B VPWR Q_N Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/sdfrbp/sky130_fd_sc_ls__sdfrbp_2.pex.spice b/cells/sdfrbp/sky130_fd_sc_ls__sdfrbp_2.pex.spice
index b431448..33f0bef 100644
--- a/cells/sdfrbp/sky130_fd_sc_ls__sdfrbp_2.pex.spice
+++ b/cells/sdfrbp/sky130_fd_sc_ls__sdfrbp_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__sdfrbp_2.pex.spice
-* Created: Fri Aug 28 14:02:43 2020
+* Created: Wed Sep 2 11:27:01 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/sdfrbp/sky130_fd_sc_ls__sdfrbp_2.pxi.spice b/cells/sdfrbp/sky130_fd_sc_ls__sdfrbp_2.pxi.spice
index edcb84a..83bb59e 100644
--- a/cells/sdfrbp/sky130_fd_sc_ls__sdfrbp_2.pxi.spice
+++ b/cells/sdfrbp/sky130_fd_sc_ls__sdfrbp_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__sdfrbp_2.pxi.spice
-* Created: Fri Aug 28 14:02:43 2020
+* Created: Wed Sep 2 11:27:01 2020
*
x_PM_SKY130_FD_SC_LS__SDFRBP_2%A_27_79# N_A_27_79#_M1027_s N_A_27_79#_M1026_s
+ N_A_27_79#_M1007_g N_A_27_79#_c_281_n N_A_27_79#_M1014_g N_A_27_79#_c_276_n
diff --git a/cells/sdfrbp/sky130_fd_sc_ls__sdfrbp_2.spice b/cells/sdfrbp/sky130_fd_sc_ls__sdfrbp_2.spice
index 6adeec5..4016f47 100644
--- a/cells/sdfrbp/sky130_fd_sc_ls__sdfrbp_2.spice
+++ b/cells/sdfrbp/sky130_fd_sc_ls__sdfrbp_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__sdfrbp_2.spice
-* Created: Fri Aug 28 14:02:43 2020
+* Created: Wed Sep 2 11:27:01 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/sdfrtn/sky130_fd_sc_ls__sdfrtn_1.lvs.report b/cells/sdfrtn/sky130_fd_sc_ls__sdfrtn_1.lvs.report
new file mode 100644
index 0000000..c05459a
--- /dev/null
+++ b/cells/sdfrtn/sky130_fd_sc_ls__sdfrtn_1.lvs.report
@@ -0,0 +1,472 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__sdfrtn_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__sdfrtn_1.sp ('sky130_fd_sc_ls__sdfrtn_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/sdfrtn/sky130_fd_sc_ls__sdfrtn_1.spice ('sky130_fd_sc_ls__sdfrtn_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:27:05 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__sdfrtn_1 sky130_fd_sc_ls__sdfrtn_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__sdfrtn_1
+SOURCE CELL NAME: sky130_fd_sc_ls__sdfrtn_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 30 30
+
+ Instances: 20 20 MN (4 pins)
+ 20 20 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 41 40
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 19 19
+
+ Instances: 8 8 MN (4 pins)
+ 12 12 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ 4 4 SMP2 (4 pins)
+ 1 1 SPMN((2+2)*1) (7 pins)
+ ------ ------
+ Total Inst: 28 28
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 19 19 0 0
+
+ Instances: 8 8 0 0 MN(NSHORT)
+ 12 12 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ 1 1 0 0 SMN3
+ 4 4 0 0 SMP2
+ 1 1 0 0 SPMN((2+2)*1)
+ ------- ------- --------- ---------
+ Total Inst: 28 28 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB SCE D SCD CLK_N RESET_B VPWR Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/sdfrtn/sky130_fd_sc_ls__sdfrtn_1.pex.spice b/cells/sdfrtn/sky130_fd_sc_ls__sdfrtn_1.pex.spice
index d9e642f..aa5ebec 100644
--- a/cells/sdfrtn/sky130_fd_sc_ls__sdfrtn_1.pex.spice
+++ b/cells/sdfrtn/sky130_fd_sc_ls__sdfrtn_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__sdfrtn_1.pex.spice
-* Created: Fri Aug 28 14:02:54 2020
+* Created: Wed Sep 2 11:27:08 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/sdfrtn/sky130_fd_sc_ls__sdfrtn_1.pxi.spice b/cells/sdfrtn/sky130_fd_sc_ls__sdfrtn_1.pxi.spice
index a07122b..1a19308 100644
--- a/cells/sdfrtn/sky130_fd_sc_ls__sdfrtn_1.pxi.spice
+++ b/cells/sdfrtn/sky130_fd_sc_ls__sdfrtn_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__sdfrtn_1.pxi.spice
-* Created: Fri Aug 28 14:02:54 2020
+* Created: Wed Sep 2 11:27:08 2020
*
x_PM_SKY130_FD_SC_LS__SDFRTN_1%SCE N_SCE_M1037_g N_SCE_c_280_n N_SCE_c_289_n
+ N_SCE_M1030_g N_SCE_M1031_g N_SCE_M1003_g N_SCE_c_282_n N_SCE_c_283_n
diff --git a/cells/sdfrtn/sky130_fd_sc_ls__sdfrtn_1.spice b/cells/sdfrtn/sky130_fd_sc_ls__sdfrtn_1.spice
index 9c6e3eb..593ec76 100644
--- a/cells/sdfrtn/sky130_fd_sc_ls__sdfrtn_1.spice
+++ b/cells/sdfrtn/sky130_fd_sc_ls__sdfrtn_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__sdfrtn_1.spice
-* Created: Fri Aug 28 14:02:54 2020
+* Created: Wed Sep 2 11:27:08 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/sdfrtp/sky130_fd_sc_ls__sdfrtp_1.lvs.report b/cells/sdfrtp/sky130_fd_sc_ls__sdfrtp_1.lvs.report
new file mode 100644
index 0000000..5f7ed1d
--- /dev/null
+++ b/cells/sdfrtp/sky130_fd_sc_ls__sdfrtp_1.lvs.report
@@ -0,0 +1,472 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__sdfrtp_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__sdfrtp_1.sp ('sky130_fd_sc_ls__sdfrtp_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/sdfrtp/sky130_fd_sc_ls__sdfrtp_1.spice ('sky130_fd_sc_ls__sdfrtp_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:27:12 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__sdfrtp_1 sky130_fd_sc_ls__sdfrtp_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__sdfrtp_1
+SOURCE CELL NAME: sky130_fd_sc_ls__sdfrtp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 30 30
+
+ Instances: 20 20 MN (4 pins)
+ 20 20 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 41 40
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 19 19
+
+ Instances: 8 8 MN (4 pins)
+ 12 12 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ 4 4 SMP2 (4 pins)
+ 1 1 SPMN((2+2)*1) (7 pins)
+ ------ ------
+ Total Inst: 28 28
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 19 19 0 0
+
+ Instances: 8 8 0 0 MN(NSHORT)
+ 12 12 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ 1 1 0 0 SMN3
+ 4 4 0 0 SMP2
+ 1 1 0 0 SPMN((2+2)*1)
+ ------- ------- --------- ---------
+ Total Inst: 28 28 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB SCE D SCD CLK RESET_B VPWR Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/sdfrtp/sky130_fd_sc_ls__sdfrtp_1.pex.spice b/cells/sdfrtp/sky130_fd_sc_ls__sdfrtp_1.pex.spice
index f043e62..15ddd76 100644
--- a/cells/sdfrtp/sky130_fd_sc_ls__sdfrtp_1.pex.spice
+++ b/cells/sdfrtp/sky130_fd_sc_ls__sdfrtp_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__sdfrtp_1.pex.spice
-* Created: Fri Aug 28 14:03:05 2020
+* Created: Wed Sep 2 11:27:16 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/sdfrtp/sky130_fd_sc_ls__sdfrtp_1.pxi.spice b/cells/sdfrtp/sky130_fd_sc_ls__sdfrtp_1.pxi.spice
index cfd8e0d..f22474f 100644
--- a/cells/sdfrtp/sky130_fd_sc_ls__sdfrtp_1.pxi.spice
+++ b/cells/sdfrtp/sky130_fd_sc_ls__sdfrtp_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__sdfrtp_1.pxi.spice
-* Created: Fri Aug 28 14:03:05 2020
+* Created: Wed Sep 2 11:27:16 2020
*
x_PM_SKY130_FD_SC_LS__SDFRTP_1%SCE N_SCE_c_308_n N_SCE_M1033_g N_SCE_c_309_n
+ N_SCE_M1020_g N_SCE_c_310_n N_SCE_c_311_n N_SCE_M1017_g N_SCE_M1024_g
diff --git a/cells/sdfrtp/sky130_fd_sc_ls__sdfrtp_1.spice b/cells/sdfrtp/sky130_fd_sc_ls__sdfrtp_1.spice
index 1310756..37f71d3 100644
--- a/cells/sdfrtp/sky130_fd_sc_ls__sdfrtp_1.spice
+++ b/cells/sdfrtp/sky130_fd_sc_ls__sdfrtp_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__sdfrtp_1.spice
-* Created: Fri Aug 28 14:03:05 2020
+* Created: Wed Sep 2 11:27:16 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/sdfrtp/sky130_fd_sc_ls__sdfrtp_2.lvs.report b/cells/sdfrtp/sky130_fd_sc_ls__sdfrtp_2.lvs.report
new file mode 100644
index 0000000..23f715a
--- /dev/null
+++ b/cells/sdfrtp/sky130_fd_sc_ls__sdfrtp_2.lvs.report
@@ -0,0 +1,477 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__sdfrtp_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__sdfrtp_2.sp ('sky130_fd_sc_ls__sdfrtp_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/sdfrtp/sky130_fd_sc_ls__sdfrtp_2.spice ('sky130_fd_sc_ls__sdfrtp_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:27:19 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__sdfrtp_2 sky130_fd_sc_ls__sdfrtp_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__sdfrtp_2
+SOURCE CELL NAME: sky130_fd_sc_ls__sdfrtp_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 30 30
+
+ Instances: 21 21 MN (4 pins)
+ 21 21 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 43 42
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 19 19
+
+ Instances: 8 8 MN (4 pins)
+ 12 12 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ 4 4 SMP2 (4 pins)
+ 1 1 SPMN((2+2)*1) (7 pins)
+ ------ ------
+ Total Inst: 28 28
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 19 19 0 0
+
+ Instances: 8 8 0 0 MN(NSHORT)
+ 12 12 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ 1 1 0 0 SMN3
+ 4 4 0 0 SMP2
+ 1 1 0 0 SPMN((2+2)*1)
+ ------- ------- --------- ---------
+ Total Inst: 28 28 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB SCE D SCD CLK RESET_B VPWR Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/sdfrtp/sky130_fd_sc_ls__sdfrtp_2.pex.spice b/cells/sdfrtp/sky130_fd_sc_ls__sdfrtp_2.pex.spice
index 91acf8c..eaf337e 100644
--- a/cells/sdfrtp/sky130_fd_sc_ls__sdfrtp_2.pex.spice
+++ b/cells/sdfrtp/sky130_fd_sc_ls__sdfrtp_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__sdfrtp_2.pex.spice
-* Created: Fri Aug 28 14:03:15 2020
+* Created: Wed Sep 2 11:27:23 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/sdfrtp/sky130_fd_sc_ls__sdfrtp_2.pxi.spice b/cells/sdfrtp/sky130_fd_sc_ls__sdfrtp_2.pxi.spice
index 4b140ca..db18a27 100644
--- a/cells/sdfrtp/sky130_fd_sc_ls__sdfrtp_2.pxi.spice
+++ b/cells/sdfrtp/sky130_fd_sc_ls__sdfrtp_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__sdfrtp_2.pxi.spice
-* Created: Fri Aug 28 14:03:15 2020
+* Created: Wed Sep 2 11:27:23 2020
*
x_PM_SKY130_FD_SC_LS__SDFRTP_2%A_27_74# N_A_27_74#_M1031_s N_A_27_74#_M1022_s
+ N_A_27_74#_c_283_n N_A_27_74#_c_284_n N_A_27_74#_M1005_g N_A_27_74#_c_290_n
diff --git a/cells/sdfrtp/sky130_fd_sc_ls__sdfrtp_2.spice b/cells/sdfrtp/sky130_fd_sc_ls__sdfrtp_2.spice
index 2ac5dcb..94a77d1 100644
--- a/cells/sdfrtp/sky130_fd_sc_ls__sdfrtp_2.spice
+++ b/cells/sdfrtp/sky130_fd_sc_ls__sdfrtp_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__sdfrtp_2.spice
-* Created: Fri Aug 28 14:03:15 2020
+* Created: Wed Sep 2 11:27:23 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/sdfrtp/sky130_fd_sc_ls__sdfrtp_4.lvs.report b/cells/sdfrtp/sky130_fd_sc_ls__sdfrtp_4.lvs.report
new file mode 100644
index 0000000..ea262f4
--- /dev/null
+++ b/cells/sdfrtp/sky130_fd_sc_ls__sdfrtp_4.lvs.report
@@ -0,0 +1,477 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__sdfrtp_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__sdfrtp_4.sp ('sky130_fd_sc_ls__sdfrtp_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/sdfrtp/sky130_fd_sc_ls__sdfrtp_4.spice ('sky130_fd_sc_ls__sdfrtp_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:27:27 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__sdfrtp_4 sky130_fd_sc_ls__sdfrtp_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__sdfrtp_4
+SOURCE CELL NAME: sky130_fd_sc_ls__sdfrtp_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 30 30
+
+ Instances: 23 23 MN (4 pins)
+ 24 24 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 48 47
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 19 19
+
+ Instances: 8 8 MN (4 pins)
+ 12 12 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ 4 4 SMP2 (4 pins)
+ 1 1 SPMN((2+2)*1) (7 pins)
+ ------ ------
+ Total Inst: 28 28
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 19 19 0 0
+
+ Instances: 8 8 0 0 MN(NSHORT)
+ 12 12 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ 1 1 0 0 SMN3
+ 4 4 0 0 SMP2
+ 1 1 0 0 SPMN((2+2)*1)
+ ------- ------- --------- ---------
+ Total Inst: 28 28 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 10 layout mos transistors were reduced to 3.
+ 7 mos transistors were deleted by parallel reduction.
+ 10 source mos transistors were reduced to 3.
+ 7 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB SCE D SCD CLK RESET_B VPWR Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/sdfrtp/sky130_fd_sc_ls__sdfrtp_4.pex.spice b/cells/sdfrtp/sky130_fd_sc_ls__sdfrtp_4.pex.spice
index 6357a0c..778ada3 100644
--- a/cells/sdfrtp/sky130_fd_sc_ls__sdfrtp_4.pex.spice
+++ b/cells/sdfrtp/sky130_fd_sc_ls__sdfrtp_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__sdfrtp_4.pex.spice
-* Created: Fri Aug 28 14:03:32 2020
+* Created: Wed Sep 2 11:27:30 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/sdfrtp/sky130_fd_sc_ls__sdfrtp_4.pxi.spice b/cells/sdfrtp/sky130_fd_sc_ls__sdfrtp_4.pxi.spice
index 1488e6a..e9eb5c4 100644
--- a/cells/sdfrtp/sky130_fd_sc_ls__sdfrtp_4.pxi.spice
+++ b/cells/sdfrtp/sky130_fd_sc_ls__sdfrtp_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__sdfrtp_4.pxi.spice
-* Created: Fri Aug 28 14:03:32 2020
+* Created: Wed Sep 2 11:27:30 2020
*
x_PM_SKY130_FD_SC_LS__SDFRTP_4%A_27_74# N_A_27_74#_M1036_s N_A_27_74#_M1023_s
+ N_A_27_74#_c_302_n N_A_27_74#_c_303_n N_A_27_74#_M1005_g N_A_27_74#_c_309_n
diff --git a/cells/sdfrtp/sky130_fd_sc_ls__sdfrtp_4.spice b/cells/sdfrtp/sky130_fd_sc_ls__sdfrtp_4.spice
index 8e5a802..28ee978 100644
--- a/cells/sdfrtp/sky130_fd_sc_ls__sdfrtp_4.spice
+++ b/cells/sdfrtp/sky130_fd_sc_ls__sdfrtp_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__sdfrtp_4.spice
-* Created: Fri Aug 28 14:03:32 2020
+* Created: Wed Sep 2 11:27:30 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/sdfsbp/sky130_fd_sc_ls__sdfsbp_1.lvs.report b/cells/sdfsbp/sky130_fd_sc_ls__sdfsbp_1.lvs.report
new file mode 100644
index 0000000..00d03ce
--- /dev/null
+++ b/cells/sdfsbp/sky130_fd_sc_ls__sdfsbp_1.lvs.report
@@ -0,0 +1,470 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__sdfsbp_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__sdfsbp_1.sp ('sky130_fd_sc_ls__sdfsbp_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/sdfsbp/sky130_fd_sc_ls__sdfsbp_1.spice ('sky130_fd_sc_ls__sdfsbp_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:27:34 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__sdfsbp_1 sky130_fd_sc_ls__sdfsbp_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__sdfsbp_1
+SOURCE CELL NAME: sky130_fd_sc_ls__sdfsbp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 11 11
+
+ Nets: 32 32
+
+ Instances: 21 21 MN (4 pins)
+ 21 21 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 43 42
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 11 11
+
+ Nets: 20 20
+
+ Instances: 8 8 MN (4 pins)
+ 11 11 MP (4 pins)
+ 5 5 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ 5 5 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 30 30
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 11 11 0 0
+
+ Nets: 20 20 0 0
+
+ Instances: 8 8 0 0 MN(NSHORT)
+ 11 11 0 0 MP(PHIGHVT)
+ 5 5 0 0 SMN2
+ 1 1 0 0 SMN3
+ 5 5 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 30 30 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB SCE D SCD CLK SET_B VPWR Q_N Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/sdfsbp/sky130_fd_sc_ls__sdfsbp_1.pex.spice b/cells/sdfsbp/sky130_fd_sc_ls__sdfsbp_1.pex.spice
index b40a8a7..e550d7c 100644
--- a/cells/sdfsbp/sky130_fd_sc_ls__sdfsbp_1.pex.spice
+++ b/cells/sdfsbp/sky130_fd_sc_ls__sdfsbp_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__sdfsbp_1.pex.spice
-* Created: Fri Aug 28 14:03:53 2020
+* Created: Wed Sep 2 11:27:37 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/sdfsbp/sky130_fd_sc_ls__sdfsbp_1.pxi.spice b/cells/sdfsbp/sky130_fd_sc_ls__sdfsbp_1.pxi.spice
index 0204a01..d8a3af0 100644
--- a/cells/sdfsbp/sky130_fd_sc_ls__sdfsbp_1.pxi.spice
+++ b/cells/sdfsbp/sky130_fd_sc_ls__sdfsbp_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__sdfsbp_1.pxi.spice
-* Created: Fri Aug 28 14:03:53 2020
+* Created: Wed Sep 2 11:27:37 2020
*
x_PM_SKY130_FD_SC_LS__SDFSBP_1%A_27_74# N_A_27_74#_M1033_s N_A_27_74#_M1026_s
+ N_A_27_74#_M1036_g N_A_27_74#_c_302_n N_A_27_74#_M1039_g N_A_27_74#_c_297_n
diff --git a/cells/sdfsbp/sky130_fd_sc_ls__sdfsbp_1.spice b/cells/sdfsbp/sky130_fd_sc_ls__sdfsbp_1.spice
index 7f0f9a5..750877e 100644
--- a/cells/sdfsbp/sky130_fd_sc_ls__sdfsbp_1.spice
+++ b/cells/sdfsbp/sky130_fd_sc_ls__sdfsbp_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__sdfsbp_1.spice
-* Created: Fri Aug 28 14:03:53 2020
+* Created: Wed Sep 2 11:27:37 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/sdfsbp/sky130_fd_sc_ls__sdfsbp_2.lvs.report b/cells/sdfsbp/sky130_fd_sc_ls__sdfsbp_2.lvs.report
new file mode 100644
index 0000000..17b17c3
--- /dev/null
+++ b/cells/sdfsbp/sky130_fd_sc_ls__sdfsbp_2.lvs.report
@@ -0,0 +1,475 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__sdfsbp_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__sdfsbp_2.sp ('sky130_fd_sc_ls__sdfsbp_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/sdfsbp/sky130_fd_sc_ls__sdfsbp_2.spice ('sky130_fd_sc_ls__sdfsbp_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:27:41 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__sdfsbp_2 sky130_fd_sc_ls__sdfsbp_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__sdfsbp_2
+SOURCE CELL NAME: sky130_fd_sc_ls__sdfsbp_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 11 11
+
+ Nets: 32 32
+
+ Instances: 25 25 MN (4 pins)
+ 25 25 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 51 50
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 11 11
+
+ Nets: 20 20
+
+ Instances: 8 8 MN (4 pins)
+ 11 11 MP (4 pins)
+ 5 5 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ 5 5 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 30 30
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 11 11 0 0
+
+ Nets: 20 20 0 0
+
+ Instances: 8 8 0 0 MN(NSHORT)
+ 11 11 0 0 MP(PHIGHVT)
+ 5 5 0 0 SMN2
+ 1 1 0 0 SMN3
+ 5 5 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 30 30 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 16 layout mos transistors were reduced to 8.
+ 8 mos transistors were deleted by parallel reduction.
+ 16 source mos transistors were reduced to 8.
+ 8 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB SCE D SCD CLK SET_B VPWR Q_N Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/sdfsbp/sky130_fd_sc_ls__sdfsbp_2.pex.spice b/cells/sdfsbp/sky130_fd_sc_ls__sdfsbp_2.pex.spice
index a1af78f..ff5f729 100644
--- a/cells/sdfsbp/sky130_fd_sc_ls__sdfsbp_2.pex.spice
+++ b/cells/sdfsbp/sky130_fd_sc_ls__sdfsbp_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__sdfsbp_2.pex.spice
-* Created: Fri Aug 28 14:04:04 2020
+* Created: Wed Sep 2 11:27:45 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/sdfsbp/sky130_fd_sc_ls__sdfsbp_2.pxi.spice b/cells/sdfsbp/sky130_fd_sc_ls__sdfsbp_2.pxi.spice
index 18d342e..37910b5 100644
--- a/cells/sdfsbp/sky130_fd_sc_ls__sdfsbp_2.pxi.spice
+++ b/cells/sdfsbp/sky130_fd_sc_ls__sdfsbp_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__sdfsbp_2.pxi.spice
-* Created: Fri Aug 28 14:04:04 2020
+* Created: Wed Sep 2 11:27:45 2020
*
x_PM_SKY130_FD_SC_LS__SDFSBP_2%A_27_74# N_A_27_74#_M1044_s N_A_27_74#_M1008_s
+ N_A_27_74#_M1035_g N_A_27_74#_c_379_n N_A_27_74#_M1042_g N_A_27_74#_c_373_n
diff --git a/cells/sdfsbp/sky130_fd_sc_ls__sdfsbp_2.spice b/cells/sdfsbp/sky130_fd_sc_ls__sdfsbp_2.spice
index 13d9f70..617130a 100644
--- a/cells/sdfsbp/sky130_fd_sc_ls__sdfsbp_2.spice
+++ b/cells/sdfsbp/sky130_fd_sc_ls__sdfsbp_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__sdfsbp_2.spice
-* Created: Fri Aug 28 14:04:04 2020
+* Created: Wed Sep 2 11:27:45 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/sdfstp/sky130_fd_sc_ls__sdfstp_1.lvs.report b/cells/sdfstp/sky130_fd_sc_ls__sdfstp_1.lvs.report
new file mode 100644
index 0000000..23b2058
--- /dev/null
+++ b/cells/sdfstp/sky130_fd_sc_ls__sdfstp_1.lvs.report
@@ -0,0 +1,470 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__sdfstp_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__sdfstp_1.sp ('sky130_fd_sc_ls__sdfstp_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/sdfstp/sky130_fd_sc_ls__sdfstp_1.spice ('sky130_fd_sc_ls__sdfstp_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:27:49 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__sdfstp_1 sky130_fd_sc_ls__sdfstp_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__sdfstp_1
+SOURCE CELL NAME: sky130_fd_sc_ls__sdfstp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 31 31
+
+ Instances: 20 20 MN (4 pins)
+ 20 20 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 41 40
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 19 19
+
+ Instances: 7 7 MN (4 pins)
+ 10 10 MP (4 pins)
+ 5 5 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ 5 5 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 28 28
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 19 19 0 0
+
+ Instances: 7 7 0 0 MN(NSHORT)
+ 10 10 0 0 MP(PHIGHVT)
+ 5 5 0 0 SMN2
+ 1 1 0 0 SMN3
+ 5 5 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 28 28 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB SCE D SCD CLK SET_B VPWR Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/sdfstp/sky130_fd_sc_ls__sdfstp_1.pex.spice b/cells/sdfstp/sky130_fd_sc_ls__sdfstp_1.pex.spice
index 06ad4b7..230afd6 100644
--- a/cells/sdfstp/sky130_fd_sc_ls__sdfstp_1.pex.spice
+++ b/cells/sdfstp/sky130_fd_sc_ls__sdfstp_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__sdfstp_1.pex.spice
-* Created: Fri Aug 28 14:04:15 2020
+* Created: Wed Sep 2 11:27:52 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/sdfstp/sky130_fd_sc_ls__sdfstp_1.pxi.spice b/cells/sdfstp/sky130_fd_sc_ls__sdfstp_1.pxi.spice
index 463dda3..0807c34 100644
--- a/cells/sdfstp/sky130_fd_sc_ls__sdfstp_1.pxi.spice
+++ b/cells/sdfstp/sky130_fd_sc_ls__sdfstp_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__sdfstp_1.pxi.spice
-* Created: Fri Aug 28 14:04:15 2020
+* Created: Wed Sep 2 11:27:52 2020
*
x_PM_SKY130_FD_SC_LS__SDFSTP_1%SCE N_SCE_c_303_n N_SCE_c_304_n N_SCE_M1026_g
+ N_SCE_M1020_g N_SCE_c_305_n N_SCE_c_306_n N_SCE_c_307_n N_SCE_M1027_g
diff --git a/cells/sdfstp/sky130_fd_sc_ls__sdfstp_1.spice b/cells/sdfstp/sky130_fd_sc_ls__sdfstp_1.spice
index cbd49a2..eece0e0 100644
--- a/cells/sdfstp/sky130_fd_sc_ls__sdfstp_1.spice
+++ b/cells/sdfstp/sky130_fd_sc_ls__sdfstp_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__sdfstp_1.spice
-* Created: Fri Aug 28 14:04:15 2020
+* Created: Wed Sep 2 11:27:52 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/sdfstp/sky130_fd_sc_ls__sdfstp_2.lvs.report b/cells/sdfstp/sky130_fd_sc_ls__sdfstp_2.lvs.report
new file mode 100644
index 0000000..5c820c7
--- /dev/null
+++ b/cells/sdfstp/sky130_fd_sc_ls__sdfstp_2.lvs.report
@@ -0,0 +1,475 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__sdfstp_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__sdfstp_2.sp ('sky130_fd_sc_ls__sdfstp_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/sdfstp/sky130_fd_sc_ls__sdfstp_2.spice ('sky130_fd_sc_ls__sdfstp_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:27:56 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__sdfstp_2 sky130_fd_sc_ls__sdfstp_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__sdfstp_2
+SOURCE CELL NAME: sky130_fd_sc_ls__sdfstp_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 31 31
+
+ Instances: 23 23 MN (4 pins)
+ 23 23 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 47 46
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 19 19
+
+ Instances: 7 7 MN (4 pins)
+ 10 10 MP (4 pins)
+ 5 5 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ 5 5 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 28 28
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 19 19 0 0
+
+ Instances: 7 7 0 0 MN(NSHORT)
+ 10 10 0 0 MP(PHIGHVT)
+ 5 5 0 0 SMN2
+ 1 1 0 0 SMN3
+ 5 5 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 28 28 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 12 layout mos transistors were reduced to 6.
+ 6 mos transistors were deleted by parallel reduction.
+ 12 source mos transistors were reduced to 6.
+ 6 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB SCE D SCD CLK SET_B VPWR Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/sdfstp/sky130_fd_sc_ls__sdfstp_2.pex.spice b/cells/sdfstp/sky130_fd_sc_ls__sdfstp_2.pex.spice
index 3dd4d37..e220563 100644
--- a/cells/sdfstp/sky130_fd_sc_ls__sdfstp_2.pex.spice
+++ b/cells/sdfstp/sky130_fd_sc_ls__sdfstp_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__sdfstp_2.pex.spice
-* Created: Fri Aug 28 14:04:33 2020
+* Created: Wed Sep 2 11:27:59 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/sdfstp/sky130_fd_sc_ls__sdfstp_2.pxi.spice b/cells/sdfstp/sky130_fd_sc_ls__sdfstp_2.pxi.spice
index aab130d..ad08de7 100644
--- a/cells/sdfstp/sky130_fd_sc_ls__sdfstp_2.pxi.spice
+++ b/cells/sdfstp/sky130_fd_sc_ls__sdfstp_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__sdfstp_2.pxi.spice
-* Created: Fri Aug 28 14:04:33 2020
+* Created: Wed Sep 2 11:27:59 2020
*
x_PM_SKY130_FD_SC_LS__SDFSTP_2%SCE N_SCE_c_327_n N_SCE_M1039_g N_SCE_c_328_n
+ N_SCE_M1021_g N_SCE_c_329_n N_SCE_M1022_g N_SCE_M1032_g N_SCE_c_322_n
diff --git a/cells/sdfstp/sky130_fd_sc_ls__sdfstp_2.spice b/cells/sdfstp/sky130_fd_sc_ls__sdfstp_2.spice
index 4269a2d..a1a27f7 100644
--- a/cells/sdfstp/sky130_fd_sc_ls__sdfstp_2.spice
+++ b/cells/sdfstp/sky130_fd_sc_ls__sdfstp_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__sdfstp_2.spice
-* Created: Fri Aug 28 14:04:33 2020
+* Created: Wed Sep 2 11:27:59 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/sdfstp/sky130_fd_sc_ls__sdfstp_4.lvs.report b/cells/sdfstp/sky130_fd_sc_ls__sdfstp_4.lvs.report
new file mode 100644
index 0000000..3ed39a9
--- /dev/null
+++ b/cells/sdfstp/sky130_fd_sc_ls__sdfstp_4.lvs.report
@@ -0,0 +1,475 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__sdfstp_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__sdfstp_4.sp ('sky130_fd_sc_ls__sdfstp_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/sdfstp/sky130_fd_sc_ls__sdfstp_4.spice ('sky130_fd_sc_ls__sdfstp_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:28:03 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__sdfstp_4 sky130_fd_sc_ls__sdfstp_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__sdfstp_4
+SOURCE CELL NAME: sky130_fd_sc_ls__sdfstp_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 31 31
+
+ Instances: 25 25 MN (4 pins)
+ 26 26 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 52 51
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 19 19
+
+ Instances: 7 7 MN (4 pins)
+ 10 10 MP (4 pins)
+ 5 5 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ 5 5 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 28 28
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 19 19 0 0
+
+ Instances: 7 7 0 0 MN(NSHORT)
+ 10 10 0 0 MP(PHIGHVT)
+ 5 5 0 0 SMN2
+ 1 1 0 0 SMN3
+ 5 5 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 28 28 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 18 layout mos transistors were reduced to 7.
+ 11 mos transistors were deleted by parallel reduction.
+ 18 source mos transistors were reduced to 7.
+ 11 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB SCE D SCD CLK SET_B VPWR Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/sdfstp/sky130_fd_sc_ls__sdfstp_4.pex.spice b/cells/sdfstp/sky130_fd_sc_ls__sdfstp_4.pex.spice
index c7ffaf7..53e6a28 100644
--- a/cells/sdfstp/sky130_fd_sc_ls__sdfstp_4.pex.spice
+++ b/cells/sdfstp/sky130_fd_sc_ls__sdfstp_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__sdfstp_4.pex.spice
-* Created: Fri Aug 28 14:04:53 2020
+* Created: Wed Sep 2 11:28:06 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/sdfstp/sky130_fd_sc_ls__sdfstp_4.pxi.spice b/cells/sdfstp/sky130_fd_sc_ls__sdfstp_4.pxi.spice
index 1f4a96c..75383f8 100644
--- a/cells/sdfstp/sky130_fd_sc_ls__sdfstp_4.pxi.spice
+++ b/cells/sdfstp/sky130_fd_sc_ls__sdfstp_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__sdfstp_4.pxi.spice
-* Created: Fri Aug 28 14:04:53 2020
+* Created: Wed Sep 2 11:28:06 2020
*
x_PM_SKY130_FD_SC_LS__SDFSTP_4%SCE N_SCE_M1045_g N_SCE_c_346_n N_SCE_M1043_g
+ N_SCE_c_347_n N_SCE_M1044_g N_SCE_M1017_g N_SCE_c_341_n N_SCE_c_342_n
diff --git a/cells/sdfstp/sky130_fd_sc_ls__sdfstp_4.spice b/cells/sdfstp/sky130_fd_sc_ls__sdfstp_4.spice
index 85e7173..04cb5f2 100644
--- a/cells/sdfstp/sky130_fd_sc_ls__sdfstp_4.spice
+++ b/cells/sdfstp/sky130_fd_sc_ls__sdfstp_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__sdfstp_4.spice
-* Created: Fri Aug 28 14:04:53 2020
+* Created: Wed Sep 2 11:28:06 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/sdfxbp/sky130_fd_sc_ls__sdfxbp_1.lvs.report b/cells/sdfxbp/sky130_fd_sc_ls__sdfxbp_1.lvs.report
new file mode 100644
index 0000000..7a14558
--- /dev/null
+++ b/cells/sdfxbp/sky130_fd_sc_ls__sdfxbp_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__sdfxbp_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__sdfxbp_1.sp ('sky130_fd_sc_ls__sdfxbp_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/sdfxbp/sky130_fd_sc_ls__sdfxbp_1.spice ('sky130_fd_sc_ls__sdfxbp_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:28:10 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__sdfxbp_1 sky130_fd_sc_ls__sdfxbp_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__sdfxbp_1
+SOURCE CELL NAME: sky130_fd_sc_ls__sdfxbp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 27 27
+
+ Instances: 18 18 MN (4 pins)
+ 18 18 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 37 36
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 19 19
+
+ Instances: 10 10 MN (4 pins)
+ 10 10 MP (4 pins)
+ 4 4 SMN2 (4 pins)
+ 4 4 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 28 28
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 19 19 0 0
+
+ Instances: 10 10 0 0 MN(NSHORT)
+ 10 10 0 0 MP(PHIGHVT)
+ 4 4 0 0 SMN2
+ 4 4 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 28 28 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB SCE D SCD CLK VPWR Q Q_N VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/sdfxbp/sky130_fd_sc_ls__sdfxbp_1.pex.spice b/cells/sdfxbp/sky130_fd_sc_ls__sdfxbp_1.pex.spice
index 18c75ab..80acc1c 100644
--- a/cells/sdfxbp/sky130_fd_sc_ls__sdfxbp_1.pex.spice
+++ b/cells/sdfxbp/sky130_fd_sc_ls__sdfxbp_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__sdfxbp_1.pex.spice
-* Created: Fri Aug 28 14:05:04 2020
+* Created: Wed Sep 2 11:28:13 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/sdfxbp/sky130_fd_sc_ls__sdfxbp_1.pxi.spice b/cells/sdfxbp/sky130_fd_sc_ls__sdfxbp_1.pxi.spice
index f2f7d4a..5b56a93 100644
--- a/cells/sdfxbp/sky130_fd_sc_ls__sdfxbp_1.pxi.spice
+++ b/cells/sdfxbp/sky130_fd_sc_ls__sdfxbp_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__sdfxbp_1.pxi.spice
-* Created: Fri Aug 28 14:05:04 2020
+* Created: Wed Sep 2 11:28:13 2020
*
x_PM_SKY130_FD_SC_LS__SDFXBP_1%A_31_74# N_A_31_74#_M1023_s N_A_31_74#_M1000_s
+ N_A_31_74#_M1004_g N_A_31_74#_c_258_n N_A_31_74#_M1032_g N_A_31_74#_c_254_n
diff --git a/cells/sdfxbp/sky130_fd_sc_ls__sdfxbp_1.spice b/cells/sdfxbp/sky130_fd_sc_ls__sdfxbp_1.spice
index 21e4ac4..5db0fd2 100644
--- a/cells/sdfxbp/sky130_fd_sc_ls__sdfxbp_1.spice
+++ b/cells/sdfxbp/sky130_fd_sc_ls__sdfxbp_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__sdfxbp_1.spice
-* Created: Fri Aug 28 14:05:04 2020
+* Created: Wed Sep 2 11:28:13 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/sdfxbp/sky130_fd_sc_ls__sdfxbp_2.lvs.report b/cells/sdfxbp/sky130_fd_sc_ls__sdfxbp_2.lvs.report
new file mode 100644
index 0000000..ca8f7fe
--- /dev/null
+++ b/cells/sdfxbp/sky130_fd_sc_ls__sdfxbp_2.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__sdfxbp_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__sdfxbp_2.sp ('sky130_fd_sc_ls__sdfxbp_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/sdfxbp/sky130_fd_sc_ls__sdfxbp_2.spice ('sky130_fd_sc_ls__sdfxbp_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:28:17 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__sdfxbp_2 sky130_fd_sc_ls__sdfxbp_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__sdfxbp_2
+SOURCE CELL NAME: sky130_fd_sc_ls__sdfxbp_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 27 27
+
+ Instances: 20 20 MN (4 pins)
+ 20 20 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 41 40
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 19 19
+
+ Instances: 10 10 MN (4 pins)
+ 10 10 MP (4 pins)
+ 4 4 SMN2 (4 pins)
+ 4 4 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 28 28
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 19 19 0 0
+
+ Instances: 10 10 0 0 MN(NSHORT)
+ 10 10 0 0 MP(PHIGHVT)
+ 4 4 0 0 SMN2
+ 4 4 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 28 28 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 8 layout mos transistors were reduced to 4.
+ 4 mos transistors were deleted by parallel reduction.
+ 8 source mos transistors were reduced to 4.
+ 4 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB SCE D SCD CLK VPWR Q Q_N VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/sdfxbp/sky130_fd_sc_ls__sdfxbp_2.pex.spice b/cells/sdfxbp/sky130_fd_sc_ls__sdfxbp_2.pex.spice
index 16bf7b1..7749a6b 100644
--- a/cells/sdfxbp/sky130_fd_sc_ls__sdfxbp_2.pex.spice
+++ b/cells/sdfxbp/sky130_fd_sc_ls__sdfxbp_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__sdfxbp_2.pex.spice
-* Created: Fri Aug 28 14:05:14 2020
+* Created: Wed Sep 2 11:28:20 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/sdfxbp/sky130_fd_sc_ls__sdfxbp_2.pxi.spice b/cells/sdfxbp/sky130_fd_sc_ls__sdfxbp_2.pxi.spice
index e01259f..e2638ae 100644
--- a/cells/sdfxbp/sky130_fd_sc_ls__sdfxbp_2.pxi.spice
+++ b/cells/sdfxbp/sky130_fd_sc_ls__sdfxbp_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__sdfxbp_2.pxi.spice
-* Created: Fri Aug 28 14:05:14 2020
+* Created: Wed Sep 2 11:28:20 2020
*
x_PM_SKY130_FD_SC_LS__SDFXBP_2%A_36_74# N_A_36_74#_M1032_s N_A_36_74#_M1023_s
+ N_A_36_74#_M1012_g N_A_36_74#_c_273_n N_A_36_74#_M1006_g N_A_36_74#_c_269_n
diff --git a/cells/sdfxbp/sky130_fd_sc_ls__sdfxbp_2.spice b/cells/sdfxbp/sky130_fd_sc_ls__sdfxbp_2.spice
index e367fe1..48681c2 100644
--- a/cells/sdfxbp/sky130_fd_sc_ls__sdfxbp_2.spice
+++ b/cells/sdfxbp/sky130_fd_sc_ls__sdfxbp_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__sdfxbp_2.spice
-* Created: Fri Aug 28 14:05:14 2020
+* Created: Wed Sep 2 11:28:20 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/sdfxtp/sky130_fd_sc_ls__sdfxtp_1.lvs.report b/cells/sdfxtp/sky130_fd_sc_ls__sdfxtp_1.lvs.report
new file mode 100644
index 0000000..e75dd64
--- /dev/null
+++ b/cells/sdfxtp/sky130_fd_sc_ls__sdfxtp_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__sdfxtp_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__sdfxtp_1.sp ('sky130_fd_sc_ls__sdfxtp_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/sdfxtp/sky130_fd_sc_ls__sdfxtp_1.spice ('sky130_fd_sc_ls__sdfxtp_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:28:24 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__sdfxtp_1 sky130_fd_sc_ls__sdfxtp_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__sdfxtp_1
+SOURCE CELL NAME: sky130_fd_sc_ls__sdfxtp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 25 25
+
+ Instances: 16 16 MN (4 pins)
+ 16 16 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 33 32
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 17 17
+
+ Instances: 8 8 MN (4 pins)
+ 8 8 MP (4 pins)
+ 4 4 SMN2 (4 pins)
+ 4 4 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 24 24
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 17 17 0 0
+
+ Instances: 8 8 0 0 MN(NSHORT)
+ 8 8 0 0 MP(PHIGHVT)
+ 4 4 0 0 SMN2
+ 4 4 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 24 24 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB SCE D SCD CLK VPWR Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/sdfxtp/sky130_fd_sc_ls__sdfxtp_1.pex.spice b/cells/sdfxtp/sky130_fd_sc_ls__sdfxtp_1.pex.spice
index 6248348..296c72c 100644
--- a/cells/sdfxtp/sky130_fd_sc_ls__sdfxtp_1.pex.spice
+++ b/cells/sdfxtp/sky130_fd_sc_ls__sdfxtp_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__sdfxtp_1.pex.spice
-* Created: Fri Aug 28 14:05:25 2020
+* Created: Wed Sep 2 11:28:27 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/sdfxtp/sky130_fd_sc_ls__sdfxtp_1.pxi.spice b/cells/sdfxtp/sky130_fd_sc_ls__sdfxtp_1.pxi.spice
index f540450..a690704 100644
--- a/cells/sdfxtp/sky130_fd_sc_ls__sdfxtp_1.pxi.spice
+++ b/cells/sdfxtp/sky130_fd_sc_ls__sdfxtp_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__sdfxtp_1.pxi.spice
-* Created: Fri Aug 28 14:05:25 2020
+* Created: Wed Sep 2 11:28:27 2020
*
x_PM_SKY130_FD_SC_LS__SDFXTP_1%A_35_74# N_A_35_74#_M1008_s N_A_35_74#_M1021_s
+ N_A_35_74#_M1017_g N_A_35_74#_c_231_n N_A_35_74#_M1012_g N_A_35_74#_c_232_n
diff --git a/cells/sdfxtp/sky130_fd_sc_ls__sdfxtp_1.spice b/cells/sdfxtp/sky130_fd_sc_ls__sdfxtp_1.spice
index 46cd0c9..f78b596 100644
--- a/cells/sdfxtp/sky130_fd_sc_ls__sdfxtp_1.spice
+++ b/cells/sdfxtp/sky130_fd_sc_ls__sdfxtp_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__sdfxtp_1.spice
-* Created: Fri Aug 28 14:05:25 2020
+* Created: Wed Sep 2 11:28:27 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/sdfxtp/sky130_fd_sc_ls__sdfxtp_2.lvs.report b/cells/sdfxtp/sky130_fd_sc_ls__sdfxtp_2.lvs.report
new file mode 100644
index 0000000..bad0b41
--- /dev/null
+++ b/cells/sdfxtp/sky130_fd_sc_ls__sdfxtp_2.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__sdfxtp_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__sdfxtp_2.sp ('sky130_fd_sc_ls__sdfxtp_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/sdfxtp/sky130_fd_sc_ls__sdfxtp_2.spice ('sky130_fd_sc_ls__sdfxtp_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:28:31 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__sdfxtp_2 sky130_fd_sc_ls__sdfxtp_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__sdfxtp_2
+SOURCE CELL NAME: sky130_fd_sc_ls__sdfxtp_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 25 25
+
+ Instances: 17 17 MN (4 pins)
+ 17 17 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 35 34
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 17 17
+
+ Instances: 8 8 MN (4 pins)
+ 8 8 MP (4 pins)
+ 4 4 SMN2 (4 pins)
+ 4 4 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 24 24
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 17 17 0 0
+
+ Instances: 8 8 0 0 MN(NSHORT)
+ 8 8 0 0 MP(PHIGHVT)
+ 4 4 0 0 SMN2
+ 4 4 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 24 24 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB SCE D SCD CLK VPWR Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/sdfxtp/sky130_fd_sc_ls__sdfxtp_2.pex.spice b/cells/sdfxtp/sky130_fd_sc_ls__sdfxtp_2.pex.spice
index edb9596..178b32c 100644
--- a/cells/sdfxtp/sky130_fd_sc_ls__sdfxtp_2.pex.spice
+++ b/cells/sdfxtp/sky130_fd_sc_ls__sdfxtp_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__sdfxtp_2.pex.spice
-* Created: Fri Aug 28 14:05:42 2020
+* Created: Wed Sep 2 11:28:34 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/sdfxtp/sky130_fd_sc_ls__sdfxtp_2.pxi.spice b/cells/sdfxtp/sky130_fd_sc_ls__sdfxtp_2.pxi.spice
index 4bdfea7..0b1ad79 100644
--- a/cells/sdfxtp/sky130_fd_sc_ls__sdfxtp_2.pxi.spice
+++ b/cells/sdfxtp/sky130_fd_sc_ls__sdfxtp_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__sdfxtp_2.pxi.spice
-* Created: Fri Aug 28 14:05:42 2020
+* Created: Wed Sep 2 11:28:34 2020
*
x_PM_SKY130_FD_SC_LS__SDFXTP_2%A_27_74# N_A_27_74#_M1030_s N_A_27_74#_M1024_s
+ N_A_27_74#_M1014_g N_A_27_74#_c_234_n N_A_27_74#_M1006_g N_A_27_74#_c_230_n
diff --git a/cells/sdfxtp/sky130_fd_sc_ls__sdfxtp_2.spice b/cells/sdfxtp/sky130_fd_sc_ls__sdfxtp_2.spice
index 299dead..cf99db4 100644
--- a/cells/sdfxtp/sky130_fd_sc_ls__sdfxtp_2.spice
+++ b/cells/sdfxtp/sky130_fd_sc_ls__sdfxtp_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__sdfxtp_2.spice
-* Created: Fri Aug 28 14:05:42 2020
+* Created: Wed Sep 2 11:28:34 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/sdfxtp/sky130_fd_sc_ls__sdfxtp_4.lvs.report b/cells/sdfxtp/sky130_fd_sc_ls__sdfxtp_4.lvs.report
new file mode 100644
index 0000000..cf22871
--- /dev/null
+++ b/cells/sdfxtp/sky130_fd_sc_ls__sdfxtp_4.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__sdfxtp_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__sdfxtp_4.sp ('sky130_fd_sc_ls__sdfxtp_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/sdfxtp/sky130_fd_sc_ls__sdfxtp_4.spice ('sky130_fd_sc_ls__sdfxtp_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:28:38 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__sdfxtp_4 sky130_fd_sc_ls__sdfxtp_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__sdfxtp_4
+SOURCE CELL NAME: sky130_fd_sc_ls__sdfxtp_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 25 25
+
+ Instances: 19 19 MN (4 pins)
+ 20 20 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 40 39
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 17 17
+
+ Instances: 8 8 MN (4 pins)
+ 8 8 MP (4 pins)
+ 4 4 SMN2 (4 pins)
+ 4 4 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 24 24
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 17 17 0 0
+
+ Instances: 8 8 0 0 MN(NSHORT)
+ 8 8 0 0 MP(PHIGHVT)
+ 4 4 0 0 SMN2
+ 4 4 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 24 24 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 10 layout mos transistors were reduced to 3.
+ 7 mos transistors were deleted by parallel reduction.
+ 10 source mos transistors were reduced to 3.
+ 7 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB SCE D SCD CLK VPWR Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/sdfxtp/sky130_fd_sc_ls__sdfxtp_4.pex.spice b/cells/sdfxtp/sky130_fd_sc_ls__sdfxtp_4.pex.spice
index 2b7aa5c..951f176 100644
--- a/cells/sdfxtp/sky130_fd_sc_ls__sdfxtp_4.pex.spice
+++ b/cells/sdfxtp/sky130_fd_sc_ls__sdfxtp_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__sdfxtp_4.pex.spice
-* Created: Fri Aug 28 14:06:02 2020
+* Created: Wed Sep 2 11:28:41 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/sdfxtp/sky130_fd_sc_ls__sdfxtp_4.pxi.spice b/cells/sdfxtp/sky130_fd_sc_ls__sdfxtp_4.pxi.spice
index de14ba0..fad3e27 100644
--- a/cells/sdfxtp/sky130_fd_sc_ls__sdfxtp_4.pxi.spice
+++ b/cells/sdfxtp/sky130_fd_sc_ls__sdfxtp_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__sdfxtp_4.pxi.spice
-* Created: Fri Aug 28 14:06:02 2020
+* Created: Wed Sep 2 11:28:41 2020
*
x_PM_SKY130_FD_SC_LS__SDFXTP_4%A_36_74# N_A_36_74#_M1036_s N_A_36_74#_M1024_s
+ N_A_36_74#_M1020_g N_A_36_74#_c_255_n N_A_36_74#_M1016_g N_A_36_74#_c_249_n
diff --git a/cells/sdfxtp/sky130_fd_sc_ls__sdfxtp_4.spice b/cells/sdfxtp/sky130_fd_sc_ls__sdfxtp_4.spice
index 14f3943..39cc450 100644
--- a/cells/sdfxtp/sky130_fd_sc_ls__sdfxtp_4.spice
+++ b/cells/sdfxtp/sky130_fd_sc_ls__sdfxtp_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__sdfxtp_4.spice
-* Created: Fri Aug 28 14:06:02 2020
+* Created: Wed Sep 2 11:28:41 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/sdlclkp/sky130_fd_sc_ls__sdlclkp_1.lvs.report b/cells/sdlclkp/sky130_fd_sc_ls__sdlclkp_1.lvs.report
new file mode 100644
index 0000000..deff403
--- /dev/null
+++ b/cells/sdlclkp/sky130_fd_sc_ls__sdlclkp_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__sdlclkp_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__sdlclkp_1.sp ('sky130_fd_sc_ls__sdlclkp_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/sdlclkp/sky130_fd_sc_ls__sdlclkp_1.spice ('sky130_fd_sc_ls__sdlclkp_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:28:45 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__sdlclkp_1 sky130_fd_sc_ls__sdlclkp_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__sdlclkp_1
+SOURCE CELL NAME: sky130_fd_sc_ls__sdlclkp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 18 18
+
+ Instances: 11 11 MN (4 pins)
+ 11 11 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 23 22
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 14 14
+
+ Instances: 7 7 MN (4 pins)
+ 7 7 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 18 18
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 14 14 0 0
+
+ Instances: 7 7 0 0 MN(NSHORT)
+ 7 7 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 18 18 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB SCE GATE CLK VPWR GCLK VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/sdlclkp/sky130_fd_sc_ls__sdlclkp_1.pex.spice b/cells/sdlclkp/sky130_fd_sc_ls__sdlclkp_1.pex.spice
index e7e0df7..92ca743 100644
--- a/cells/sdlclkp/sky130_fd_sc_ls__sdlclkp_1.pex.spice
+++ b/cells/sdlclkp/sky130_fd_sc_ls__sdlclkp_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__sdlclkp_1.pex.spice
-* Created: Fri Aug 28 14:06:13 2020
+* Created: Wed Sep 2 11:28:48 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/sdlclkp/sky130_fd_sc_ls__sdlclkp_1.pxi.spice b/cells/sdlclkp/sky130_fd_sc_ls__sdlclkp_1.pxi.spice
index 3df61fb..35c8bb3 100644
--- a/cells/sdlclkp/sky130_fd_sc_ls__sdlclkp_1.pxi.spice
+++ b/cells/sdlclkp/sky130_fd_sc_ls__sdlclkp_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__sdlclkp_1.pxi.spice
-* Created: Fri Aug 28 14:06:13 2020
+* Created: Wed Sep 2 11:28:48 2020
*
x_PM_SKY130_FD_SC_LS__SDLCLKP_1%SCE N_SCE_c_159_n N_SCE_M1009_g N_SCE_c_164_n
+ N_SCE_M1014_g SCE N_SCE_c_161_n N_SCE_c_162_n
diff --git a/cells/sdlclkp/sky130_fd_sc_ls__sdlclkp_1.spice b/cells/sdlclkp/sky130_fd_sc_ls__sdlclkp_1.spice
index 5aaea1d..3720034 100644
--- a/cells/sdlclkp/sky130_fd_sc_ls__sdlclkp_1.spice
+++ b/cells/sdlclkp/sky130_fd_sc_ls__sdlclkp_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__sdlclkp_1.spice
-* Created: Fri Aug 28 14:06:13 2020
+* Created: Wed Sep 2 11:28:48 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/sdlclkp/sky130_fd_sc_ls__sdlclkp_2.lvs.report b/cells/sdlclkp/sky130_fd_sc_ls__sdlclkp_2.lvs.report
new file mode 100644
index 0000000..733b042
--- /dev/null
+++ b/cells/sdlclkp/sky130_fd_sc_ls__sdlclkp_2.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__sdlclkp_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__sdlclkp_2.sp ('sky130_fd_sc_ls__sdlclkp_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/sdlclkp/sky130_fd_sc_ls__sdlclkp_2.spice ('sky130_fd_sc_ls__sdlclkp_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:28:52 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__sdlclkp_2 sky130_fd_sc_ls__sdlclkp_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__sdlclkp_2
+SOURCE CELL NAME: sky130_fd_sc_ls__sdlclkp_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 18 18
+
+ Instances: 12 12 MN (4 pins)
+ 12 12 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 25 24
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 14 14
+
+ Instances: 7 7 MN (4 pins)
+ 7 7 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 18 18
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 14 14 0 0
+
+ Instances: 7 7 0 0 MN(NSHORT)
+ 7 7 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 18 18 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB SCE GATE CLK VPWR GCLK VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/sdlclkp/sky130_fd_sc_ls__sdlclkp_2.pex.spice b/cells/sdlclkp/sky130_fd_sc_ls__sdlclkp_2.pex.spice
index 3fb7d70..f311d54 100644
--- a/cells/sdlclkp/sky130_fd_sc_ls__sdlclkp_2.pex.spice
+++ b/cells/sdlclkp/sky130_fd_sc_ls__sdlclkp_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__sdlclkp_2.pex.spice
-* Created: Fri Aug 28 14:06:23 2020
+* Created: Wed Sep 2 11:28:56 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/sdlclkp/sky130_fd_sc_ls__sdlclkp_2.pxi.spice b/cells/sdlclkp/sky130_fd_sc_ls__sdlclkp_2.pxi.spice
index 3c9cc64..583e663 100644
--- a/cells/sdlclkp/sky130_fd_sc_ls__sdlclkp_2.pxi.spice
+++ b/cells/sdlclkp/sky130_fd_sc_ls__sdlclkp_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__sdlclkp_2.pxi.spice
-* Created: Fri Aug 28 14:06:23 2020
+* Created: Wed Sep 2 11:28:56 2020
*
x_PM_SKY130_FD_SC_LS__SDLCLKP_2%SCE N_SCE_c_169_n N_SCE_M1011_g N_SCE_c_174_n
+ N_SCE_M1021_g SCE N_SCE_c_171_n N_SCE_c_172_n
diff --git a/cells/sdlclkp/sky130_fd_sc_ls__sdlclkp_2.spice b/cells/sdlclkp/sky130_fd_sc_ls__sdlclkp_2.spice
index 18ea8df..335a8f5 100644
--- a/cells/sdlclkp/sky130_fd_sc_ls__sdlclkp_2.spice
+++ b/cells/sdlclkp/sky130_fd_sc_ls__sdlclkp_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__sdlclkp_2.spice
-* Created: Fri Aug 28 14:06:23 2020
+* Created: Wed Sep 2 11:28:56 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/sdlclkp/sky130_fd_sc_ls__sdlclkp_4.lvs.report b/cells/sdlclkp/sky130_fd_sc_ls__sdlclkp_4.lvs.report
new file mode 100644
index 0000000..764e3b3
--- /dev/null
+++ b/cells/sdlclkp/sky130_fd_sc_ls__sdlclkp_4.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__sdlclkp_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__sdlclkp_4.sp ('sky130_fd_sc_ls__sdlclkp_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/sdlclkp/sky130_fd_sc_ls__sdlclkp_4.spice ('sky130_fd_sc_ls__sdlclkp_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:28:59 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__sdlclkp_4 sky130_fd_sc_ls__sdlclkp_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__sdlclkp_4
+SOURCE CELL NAME: sky130_fd_sc_ls__sdlclkp_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 18 18
+
+ Instances: 14 14 MN (4 pins)
+ 14 14 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 29 28
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 14 14
+
+ Instances: 7 7 MN (4 pins)
+ 7 7 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 18 18
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 14 14 0 0
+
+ Instances: 7 7 0 0 MN(NSHORT)
+ 7 7 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 18 18 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 8 layout mos transistors were reduced to 2.
+ 6 mos transistors were deleted by parallel reduction.
+ 8 source mos transistors were reduced to 2.
+ 6 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB SCE GATE CLK VPWR GCLK VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/sdlclkp/sky130_fd_sc_ls__sdlclkp_4.pex.spice b/cells/sdlclkp/sky130_fd_sc_ls__sdlclkp_4.pex.spice
index 3fab1ed..25ae065 100644
--- a/cells/sdlclkp/sky130_fd_sc_ls__sdlclkp_4.pex.spice
+++ b/cells/sdlclkp/sky130_fd_sc_ls__sdlclkp_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__sdlclkp_4.pex.spice
-* Created: Fri Aug 28 14:06:34 2020
+* Created: Wed Sep 2 11:29:03 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/sdlclkp/sky130_fd_sc_ls__sdlclkp_4.pxi.spice b/cells/sdlclkp/sky130_fd_sc_ls__sdlclkp_4.pxi.spice
index d338a27..34fee33 100644
--- a/cells/sdlclkp/sky130_fd_sc_ls__sdlclkp_4.pxi.spice
+++ b/cells/sdlclkp/sky130_fd_sc_ls__sdlclkp_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__sdlclkp_4.pxi.spice
-* Created: Fri Aug 28 14:06:34 2020
+* Created: Wed Sep 2 11:29:03 2020
*
x_PM_SKY130_FD_SC_LS__SDLCLKP_4%SCE N_SCE_c_177_n N_SCE_M1009_g N_SCE_M1019_g
+ SCE N_SCE_c_179_n PM_SKY130_FD_SC_LS__SDLCLKP_4%SCE
diff --git a/cells/sdlclkp/sky130_fd_sc_ls__sdlclkp_4.spice b/cells/sdlclkp/sky130_fd_sc_ls__sdlclkp_4.spice
index 60b840b..f1851bd 100644
--- a/cells/sdlclkp/sky130_fd_sc_ls__sdlclkp_4.spice
+++ b/cells/sdlclkp/sky130_fd_sc_ls__sdlclkp_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__sdlclkp_4.spice
-* Created: Fri Aug 28 14:06:34 2020
+* Created: Wed Sep 2 11:29:03 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/sedfxbp/sky130_fd_sc_ls__sedfxbp_1.lvs.report b/cells/sedfxbp/sky130_fd_sc_ls__sedfxbp_1.lvs.report
new file mode 100644
index 0000000..d78a200
--- /dev/null
+++ b/cells/sedfxbp/sky130_fd_sc_ls__sedfxbp_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__sedfxbp_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__sedfxbp_1.sp ('sky130_fd_sc_ls__sedfxbp_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/sedfxbp/sky130_fd_sc_ls__sedfxbp_1.spice ('sky130_fd_sc_ls__sedfxbp_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:29:06 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__sedfxbp_1 sky130_fd_sc_ls__sedfxbp_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__sedfxbp_1
+SOURCE CELL NAME: sky130_fd_sc_ls__sedfxbp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 11 11
+
+ Nets: 33 33
+
+ Instances: 22 22 MN (4 pins)
+ 22 22 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 45 44
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 11 11
+
+ Nets: 21 21
+
+ Instances: 10 10 MN (4 pins)
+ 10 10 MP (4 pins)
+ 6 6 SMN2 (4 pins)
+ 6 6 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 32 32
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 11 11 0 0
+
+ Nets: 21 21 0 0
+
+ Instances: 10 10 0 0 MN(NSHORT)
+ 10 10 0 0 MP(PHIGHVT)
+ 6 6 0 0 SMN2
+ 6 6 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 32 32 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D DE SCD SCE CLK VPWR Q Q_N VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/sedfxbp/sky130_fd_sc_ls__sedfxbp_1.pex.spice b/cells/sedfxbp/sky130_fd_sc_ls__sedfxbp_1.pex.spice
index a42e70d..2172253 100644
--- a/cells/sedfxbp/sky130_fd_sc_ls__sedfxbp_1.pex.spice
+++ b/cells/sedfxbp/sky130_fd_sc_ls__sedfxbp_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__sedfxbp_1.pex.spice
-* Created: Fri Aug 28 14:06:51 2020
+* Created: Wed Sep 2 11:29:10 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/sedfxbp/sky130_fd_sc_ls__sedfxbp_1.pxi.spice b/cells/sedfxbp/sky130_fd_sc_ls__sedfxbp_1.pxi.spice
index 4140163..32a468c 100644
--- a/cells/sedfxbp/sky130_fd_sc_ls__sedfxbp_1.pxi.spice
+++ b/cells/sedfxbp/sky130_fd_sc_ls__sedfxbp_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__sedfxbp_1.pxi.spice
-* Created: Fri Aug 28 14:06:51 2020
+* Created: Wed Sep 2 11:29:10 2020
*
x_PM_SKY130_FD_SC_LS__SEDFXBP_1%D N_D_c_337_n N_D_c_342_n N_D_c_343_n
+ N_D_M1023_g N_D_M1013_g N_D_c_339_n D D N_D_c_340_n N_D_c_341_n
diff --git a/cells/sedfxbp/sky130_fd_sc_ls__sedfxbp_1.spice b/cells/sedfxbp/sky130_fd_sc_ls__sedfxbp_1.spice
index 6dd3490..7d4b442 100644
--- a/cells/sedfxbp/sky130_fd_sc_ls__sedfxbp_1.spice
+++ b/cells/sedfxbp/sky130_fd_sc_ls__sedfxbp_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__sedfxbp_1.spice
-* Created: Fri Aug 28 14:06:51 2020
+* Created: Wed Sep 2 11:29:10 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/sedfxbp/sky130_fd_sc_ls__sedfxbp_2.lvs.report b/cells/sedfxbp/sky130_fd_sc_ls__sedfxbp_2.lvs.report
new file mode 100644
index 0000000..5a09b39
--- /dev/null
+++ b/cells/sedfxbp/sky130_fd_sc_ls__sedfxbp_2.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__sedfxbp_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__sedfxbp_2.sp ('sky130_fd_sc_ls__sedfxbp_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/sedfxbp/sky130_fd_sc_ls__sedfxbp_2.spice ('sky130_fd_sc_ls__sedfxbp_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:29:13 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__sedfxbp_2 sky130_fd_sc_ls__sedfxbp_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__sedfxbp_2
+SOURCE CELL NAME: sky130_fd_sc_ls__sedfxbp_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 11 11
+
+ Nets: 33 33
+
+ Instances: 24 24 MN (4 pins)
+ 24 24 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 49 48
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 11 11
+
+ Nets: 21 21
+
+ Instances: 10 10 MN (4 pins)
+ 10 10 MP (4 pins)
+ 6 6 SMN2 (4 pins)
+ 6 6 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 32 32
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 11 11 0 0
+
+ Nets: 21 21 0 0
+
+ Instances: 10 10 0 0 MN(NSHORT)
+ 10 10 0 0 MP(PHIGHVT)
+ 6 6 0 0 SMN2
+ 6 6 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 32 32 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 8 layout mos transistors were reduced to 4.
+ 4 mos transistors were deleted by parallel reduction.
+ 8 source mos transistors were reduced to 4.
+ 4 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D DE SCD SCE CLK VPWR Q Q_N VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/sedfxbp/sky130_fd_sc_ls__sedfxbp_2.pex.spice b/cells/sedfxbp/sky130_fd_sc_ls__sedfxbp_2.pex.spice
index e993eb8..07fb9a3 100644
--- a/cells/sedfxbp/sky130_fd_sc_ls__sedfxbp_2.pex.spice
+++ b/cells/sedfxbp/sky130_fd_sc_ls__sedfxbp_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__sedfxbp_2.pex.spice
-* Created: Fri Aug 28 14:07:12 2020
+* Created: Wed Sep 2 11:29:17 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/sedfxbp/sky130_fd_sc_ls__sedfxbp_2.pxi.spice b/cells/sedfxbp/sky130_fd_sc_ls__sedfxbp_2.pxi.spice
index 2760df6..16f9011 100644
--- a/cells/sedfxbp/sky130_fd_sc_ls__sedfxbp_2.pxi.spice
+++ b/cells/sedfxbp/sky130_fd_sc_ls__sedfxbp_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__sedfxbp_2.pxi.spice
-* Created: Fri Aug 28 14:07:12 2020
+* Created: Wed Sep 2 11:29:17 2020
*
x_PM_SKY130_FD_SC_LS__SEDFXBP_2%D N_D_c_350_n N_D_c_351_n N_D_M1004_g
+ N_D_M1047_g D D N_D_c_347_n N_D_c_348_n N_D_c_349_n N_D_c_354_n
diff --git a/cells/sedfxbp/sky130_fd_sc_ls__sedfxbp_2.spice b/cells/sedfxbp/sky130_fd_sc_ls__sedfxbp_2.spice
index 7df6eae..ca65b0f 100644
--- a/cells/sedfxbp/sky130_fd_sc_ls__sedfxbp_2.spice
+++ b/cells/sedfxbp/sky130_fd_sc_ls__sedfxbp_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__sedfxbp_2.spice
-* Created: Fri Aug 28 14:07:12 2020
+* Created: Wed Sep 2 11:29:17 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/sedfxtp/sky130_fd_sc_ls__sedfxtp_1.lvs.report b/cells/sedfxtp/sky130_fd_sc_ls__sedfxtp_1.lvs.report
new file mode 100644
index 0000000..f8f098d
--- /dev/null
+++ b/cells/sedfxtp/sky130_fd_sc_ls__sedfxtp_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__sedfxtp_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__sedfxtp_1.sp ('sky130_fd_sc_ls__sedfxtp_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/sedfxtp/sky130_fd_sc_ls__sedfxtp_1.spice ('sky130_fd_sc_ls__sedfxtp_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:29:21 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__sedfxtp_1 sky130_fd_sc_ls__sedfxtp_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__sedfxtp_1
+SOURCE CELL NAME: sky130_fd_sc_ls__sedfxtp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 32 32
+
+ Instances: 21 21 MN (4 pins)
+ 21 21 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 43 42
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 20 20
+
+ Instances: 9 9 MN (4 pins)
+ 9 9 MP (4 pins)
+ 6 6 SMN2 (4 pins)
+ 6 6 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 30 30
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 20 20 0 0
+
+ Instances: 9 9 0 0 MN(NSHORT)
+ 9 9 0 0 MP(PHIGHVT)
+ 6 6 0 0 SMN2
+ 6 6 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 30 30 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D DE SCD SCE CLK VPWR Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/sedfxtp/sky130_fd_sc_ls__sedfxtp_1.pex.spice b/cells/sedfxtp/sky130_fd_sc_ls__sedfxtp_1.pex.spice
index b7bc640..9fb21d4 100644
--- a/cells/sedfxtp/sky130_fd_sc_ls__sedfxtp_1.pex.spice
+++ b/cells/sedfxtp/sky130_fd_sc_ls__sedfxtp_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__sedfxtp_1.pex.spice
-* Created: Fri Aug 28 14:07:23 2020
+* Created: Wed Sep 2 11:29:24 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/sedfxtp/sky130_fd_sc_ls__sedfxtp_1.pxi.spice b/cells/sedfxtp/sky130_fd_sc_ls__sedfxtp_1.pxi.spice
index 64a7efd..6c16ab9 100644
--- a/cells/sedfxtp/sky130_fd_sc_ls__sedfxtp_1.pxi.spice
+++ b/cells/sedfxtp/sky130_fd_sc_ls__sedfxtp_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__sedfxtp_1.pxi.spice
-* Created: Fri Aug 28 14:07:23 2020
+* Created: Wed Sep 2 11:29:24 2020
*
x_PM_SKY130_FD_SC_LS__SEDFXTP_1%D N_D_c_329_n N_D_c_334_n N_D_c_335_n
+ N_D_M1034_g N_D_M1010_g N_D_c_331_n D D N_D_c_332_n N_D_c_333_n
diff --git a/cells/sedfxtp/sky130_fd_sc_ls__sedfxtp_1.spice b/cells/sedfxtp/sky130_fd_sc_ls__sedfxtp_1.spice
index 53a0e78..3c3086b 100644
--- a/cells/sedfxtp/sky130_fd_sc_ls__sedfxtp_1.spice
+++ b/cells/sedfxtp/sky130_fd_sc_ls__sedfxtp_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__sedfxtp_1.spice
-* Created: Fri Aug 28 14:07:23 2020
+* Created: Wed Sep 2 11:29:24 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/sedfxtp/sky130_fd_sc_ls__sedfxtp_2.lvs.report b/cells/sedfxtp/sky130_fd_sc_ls__sedfxtp_2.lvs.report
new file mode 100644
index 0000000..39865ca
--- /dev/null
+++ b/cells/sedfxtp/sky130_fd_sc_ls__sedfxtp_2.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__sedfxtp_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__sedfxtp_2.sp ('sky130_fd_sc_ls__sedfxtp_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/sedfxtp/sky130_fd_sc_ls__sedfxtp_2.spice ('sky130_fd_sc_ls__sedfxtp_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:29:28 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__sedfxtp_2 sky130_fd_sc_ls__sedfxtp_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__sedfxtp_2
+SOURCE CELL NAME: sky130_fd_sc_ls__sedfxtp_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 32 32
+
+ Instances: 22 22 MN (4 pins)
+ 22 22 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 45 44
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 20 20
+
+ Instances: 9 9 MN (4 pins)
+ 9 9 MP (4 pins)
+ 6 6 SMN2 (4 pins)
+ 6 6 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 30 30
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 20 20 0 0
+
+ Instances: 9 9 0 0 MN(NSHORT)
+ 9 9 0 0 MP(PHIGHVT)
+ 6 6 0 0 SMN2
+ 6 6 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 30 30 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D DE SCD SCE CLK VPWR Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/sedfxtp/sky130_fd_sc_ls__sedfxtp_2.pex.spice b/cells/sedfxtp/sky130_fd_sc_ls__sedfxtp_2.pex.spice
index a20b1da..5f215d9 100644
--- a/cells/sedfxtp/sky130_fd_sc_ls__sedfxtp_2.pex.spice
+++ b/cells/sedfxtp/sky130_fd_sc_ls__sedfxtp_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__sedfxtp_2.pex.spice
-* Created: Fri Aug 28 14:07:33 2020
+* Created: Wed Sep 2 11:29:31 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/sedfxtp/sky130_fd_sc_ls__sedfxtp_2.pxi.spice b/cells/sedfxtp/sky130_fd_sc_ls__sedfxtp_2.pxi.spice
index b44529d..c05269c 100644
--- a/cells/sedfxtp/sky130_fd_sc_ls__sedfxtp_2.pxi.spice
+++ b/cells/sedfxtp/sky130_fd_sc_ls__sedfxtp_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__sedfxtp_2.pxi.spice
-* Created: Fri Aug 28 14:07:33 2020
+* Created: Wed Sep 2 11:29:31 2020
*
x_PM_SKY130_FD_SC_LS__SEDFXTP_2%D N_D_c_339_n N_D_c_340_n N_D_M1009_g
+ N_D_M1005_g D D N_D_c_336_n N_D_c_337_n N_D_c_338_n N_D_c_343_n
diff --git a/cells/sedfxtp/sky130_fd_sc_ls__sedfxtp_2.spice b/cells/sedfxtp/sky130_fd_sc_ls__sedfxtp_2.spice
index 8c9369f..2b33fd7 100644
--- a/cells/sedfxtp/sky130_fd_sc_ls__sedfxtp_2.spice
+++ b/cells/sedfxtp/sky130_fd_sc_ls__sedfxtp_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__sedfxtp_2.spice
-* Created: Fri Aug 28 14:07:33 2020
+* Created: Wed Sep 2 11:29:31 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/sedfxtp/sky130_fd_sc_ls__sedfxtp_4.lvs.report b/cells/sedfxtp/sky130_fd_sc_ls__sedfxtp_4.lvs.report
new file mode 100644
index 0000000..be4d77d
--- /dev/null
+++ b/cells/sedfxtp/sky130_fd_sc_ls__sedfxtp_4.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__sedfxtp_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__sedfxtp_4.sp ('sky130_fd_sc_ls__sedfxtp_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/sedfxtp/sky130_fd_sc_ls__sedfxtp_4.spice ('sky130_fd_sc_ls__sedfxtp_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:29:35 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__sedfxtp_4 sky130_fd_sc_ls__sedfxtp_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__sedfxtp_4
+SOURCE CELL NAME: sky130_fd_sc_ls__sedfxtp_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 32 32
+
+ Instances: 24 24 MN (4 pins)
+ 24 24 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 49 48
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 20 20
+
+ Instances: 9 9 MN (4 pins)
+ 9 9 MP (4 pins)
+ 6 6 SMN2 (4 pins)
+ 6 6 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 30 30
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 20 20 0 0
+
+ Instances: 9 9 0 0 MN(NSHORT)
+ 9 9 0 0 MP(PHIGHVT)
+ 6 6 0 0 SMN2
+ 6 6 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 30 30 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 8 layout mos transistors were reduced to 2.
+ 6 mos transistors were deleted by parallel reduction.
+ 8 source mos transistors were reduced to 2.
+ 6 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D DE SCD SCE CLK VPWR Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/sedfxtp/sky130_fd_sc_ls__sedfxtp_4.pex.spice b/cells/sedfxtp/sky130_fd_sc_ls__sedfxtp_4.pex.spice
index 4db1812..c381a42 100644
--- a/cells/sedfxtp/sky130_fd_sc_ls__sedfxtp_4.pex.spice
+++ b/cells/sedfxtp/sky130_fd_sc_ls__sedfxtp_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__sedfxtp_4.pex.spice
-* Created: Fri Aug 28 14:07:44 2020
+* Created: Wed Sep 2 11:29:38 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/sedfxtp/sky130_fd_sc_ls__sedfxtp_4.pxi.spice b/cells/sedfxtp/sky130_fd_sc_ls__sedfxtp_4.pxi.spice
index 404a384..f2d41ea 100644
--- a/cells/sedfxtp/sky130_fd_sc_ls__sedfxtp_4.pxi.spice
+++ b/cells/sedfxtp/sky130_fd_sc_ls__sedfxtp_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__sedfxtp_4.pxi.spice
-* Created: Fri Aug 28 14:07:44 2020
+* Created: Wed Sep 2 11:29:38 2020
*
x_PM_SKY130_FD_SC_LS__SEDFXTP_4%D N_D_c_351_n N_D_c_352_n N_D_M1023_g
+ N_D_M1000_g D D N_D_c_348_n N_D_c_349_n N_D_c_350_n N_D_c_355_n
diff --git a/cells/sedfxtp/sky130_fd_sc_ls__sedfxtp_4.spice b/cells/sedfxtp/sky130_fd_sc_ls__sedfxtp_4.spice
index 274f389..64774f7 100644
--- a/cells/sedfxtp/sky130_fd_sc_ls__sedfxtp_4.spice
+++ b/cells/sedfxtp/sky130_fd_sc_ls__sedfxtp_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__sedfxtp_4.spice
-* Created: Fri Aug 28 14:07:44 2020
+* Created: Wed Sep 2 11:29:38 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/tap/sky130_fd_sc_ls__tap_1.lvs.report b/cells/tap/sky130_fd_sc_ls__tap_1.lvs.report
new file mode 100644
index 0000000..e6c525b
--- /dev/null
+++ b/cells/tap/sky130_fd_sc_ls__tap_1.lvs.report
@@ -0,0 +1,375 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__tap_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__tap_1.sp ('sky130_fd_sc_ls__tap_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/tap/sky130_fd_sc_ls__tap_1.spice ('sky130_fd_sc_ls__tap_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:29:42 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # # ########################
+ # # # #
+ # # NOT COMPARED #
+ # # # #
+ # # ########################
+
+
+ Error: Nothing in source.
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/tap/sky130_fd_sc_ls__tap_2.lvs.report b/cells/tap/sky130_fd_sc_ls__tap_2.lvs.report
new file mode 100644
index 0000000..2119189
--- /dev/null
+++ b/cells/tap/sky130_fd_sc_ls__tap_2.lvs.report
@@ -0,0 +1,375 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__tap_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__tap_2.sp ('sky130_fd_sc_ls__tap_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/tap/sky130_fd_sc_ls__tap_2.spice ('sky130_fd_sc_ls__tap_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:29:45 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # # ########################
+ # # # #
+ # # NOT COMPARED #
+ # # # #
+ # # ########################
+
+
+ Error: Nothing in source.
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/tapmet1/sky130_fd_sc_ls__tapmet1_2.lvs.report b/cells/tapmet1/sky130_fd_sc_ls__tapmet1_2.lvs.report
new file mode 100644
index 0000000..8d1a39a
--- /dev/null
+++ b/cells/tapmet1/sky130_fd_sc_ls__tapmet1_2.lvs.report
@@ -0,0 +1,375 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__tapmet1_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__tapmet1_2.sp ('sky130_fd_sc_ls__tapmet1_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/tapmet1/sky130_fd_sc_ls__tapmet1_2.spice ('sky130_fd_sc_ls__tapmet1_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:29:49 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # # ########################
+ # # # #
+ # # NOT COMPARED #
+ # # # #
+ # # ########################
+
+
+ Error: Nothing in source.
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/tapvgnd/sky130_fd_sc_ls__tapvgnd_1.lvs.report b/cells/tapvgnd/sky130_fd_sc_ls__tapvgnd_1.lvs.report
new file mode 100644
index 0000000..070390a
--- /dev/null
+++ b/cells/tapvgnd/sky130_fd_sc_ls__tapvgnd_1.lvs.report
@@ -0,0 +1,375 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__tapvgnd_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__tapvgnd_1.sp ('sky130_fd_sc_ls__tapvgnd_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/tapvgnd/sky130_fd_sc_ls__tapvgnd_1.spice ('sky130_fd_sc_ls__tapvgnd_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:29:52 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # # ########################
+ # # # #
+ # # NOT COMPARED #
+ # # # #
+ # # ########################
+
+
+ Error: Nothing in source.
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/tapvgnd2/sky130_fd_sc_ls__tapvgnd2_1.lvs.report b/cells/tapvgnd2/sky130_fd_sc_ls__tapvgnd2_1.lvs.report
new file mode 100644
index 0000000..7d0e25f
--- /dev/null
+++ b/cells/tapvgnd2/sky130_fd_sc_ls__tapvgnd2_1.lvs.report
@@ -0,0 +1,375 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__tapvgnd2_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__tapvgnd2_1.sp ('sky130_fd_sc_ls__tapvgnd2_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/tapvgnd2/sky130_fd_sc_ls__tapvgnd2_1.spice ('sky130_fd_sc_ls__tapvgnd2_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:29:55 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # # ########################
+ # # # #
+ # # NOT COMPARED #
+ # # # #
+ # # ########################
+
+
+ Error: Nothing in source.
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/tapvgndnovpb/sky130_fd_sc_ls__tapvgndnovpb_1.lvs.report b/cells/tapvgndnovpb/sky130_fd_sc_ls__tapvgndnovpb_1.lvs.report
new file mode 100644
index 0000000..b3b0232
--- /dev/null
+++ b/cells/tapvgndnovpb/sky130_fd_sc_ls__tapvgndnovpb_1.lvs.report
@@ -0,0 +1,375 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__tapvgndnovpb_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__tapvgndnovpb_1.sp ('sky130_fd_sc_ls__tapvgndnovpb_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/tapvgndnovpb/sky130_fd_sc_ls__tapvgndnovpb_1.spice ('sky130_fd_sc_ls__tapvgndnovpb_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:29:59 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # # ########################
+ # # # #
+ # # NOT COMPARED #
+ # # # #
+ # # ########################
+
+
+ Error: Nothing in source.
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/tapvpwrvgnd/sky130_fd_sc_ls__tapvpwrvgnd_1.lvs.report b/cells/tapvpwrvgnd/sky130_fd_sc_ls__tapvpwrvgnd_1.lvs.report
new file mode 100644
index 0000000..d2f00f0
--- /dev/null
+++ b/cells/tapvpwrvgnd/sky130_fd_sc_ls__tapvpwrvgnd_1.lvs.report
@@ -0,0 +1,375 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__tapvpwrvgnd_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__tapvpwrvgnd_1.sp ('sky130_fd_sc_ls__tapvpwrvgnd_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/tapvpwrvgnd/sky130_fd_sc_ls__tapvpwrvgnd_1.spice ('sky130_fd_sc_ls__tapvpwrvgnd_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:30:03 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # # ########################
+ # # # #
+ # # NOT COMPARED #
+ # # # #
+ # # ########################
+
+
+ Error: Nothing in source.
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/xnor2/sky130_fd_sc_ls__xnor2_1.lvs.report b/cells/xnor2/sky130_fd_sc_ls__xnor2_1.lvs.report
new file mode 100644
index 0000000..1a6adbc
--- /dev/null
+++ b/cells/xnor2/sky130_fd_sc_ls__xnor2_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__xnor2_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__xnor2_1.sp ('sky130_fd_sc_ls__xnor2_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/xnor2/sky130_fd_sc_ls__xnor2_1.spice ('sky130_fd_sc_ls__xnor2_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:30:06 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__xnor2_1 sky130_fd_sc_ls__xnor2_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__xnor2_1
+SOURCE CELL NAME: sky130_fd_sc_ls__xnor2_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 11 11
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 3 3 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1 (5 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 3 3 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B A VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/xnor2/sky130_fd_sc_ls__xnor2_1.pex.spice b/cells/xnor2/sky130_fd_sc_ls__xnor2_1.pex.spice
index 27cfa82..b7a4400 100644
--- a/cells/xnor2/sky130_fd_sc_ls__xnor2_1.pex.spice
+++ b/cells/xnor2/sky130_fd_sc_ls__xnor2_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__xnor2_1.pex.spice
-* Created: Fri Aug 28 14:08:39 2020
+* Created: Wed Sep 2 11:30:10 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/xnor2/sky130_fd_sc_ls__xnor2_1.pxi.spice b/cells/xnor2/sky130_fd_sc_ls__xnor2_1.pxi.spice
index 767b0cd..b63b710 100644
--- a/cells/xnor2/sky130_fd_sc_ls__xnor2_1.pxi.spice
+++ b/cells/xnor2/sky130_fd_sc_ls__xnor2_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__xnor2_1.pxi.spice
-* Created: Fri Aug 28 14:08:39 2020
+* Created: Wed Sep 2 11:30:10 2020
*
x_PM_SKY130_FD_SC_LS__XNOR2_1%B N_B_c_60_n N_B_M1002_g N_B_c_61_n N_B_M1001_g
+ N_B_c_62_n N_B_M1007_g N_B_M1008_g N_B_c_68_n N_B_c_80_p N_B_c_116_p
diff --git a/cells/xnor2/sky130_fd_sc_ls__xnor2_1.spice b/cells/xnor2/sky130_fd_sc_ls__xnor2_1.spice
index 204717f..c418068 100644
--- a/cells/xnor2/sky130_fd_sc_ls__xnor2_1.spice
+++ b/cells/xnor2/sky130_fd_sc_ls__xnor2_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__xnor2_1.spice
-* Created: Fri Aug 28 14:08:39 2020
+* Created: Wed Sep 2 11:30:10 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/xnor2/sky130_fd_sc_ls__xnor2_2.lvs.report b/cells/xnor2/sky130_fd_sc_ls__xnor2_2.lvs.report
new file mode 100644
index 0000000..935cbc9
--- /dev/null
+++ b/cells/xnor2/sky130_fd_sc_ls__xnor2_2.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__xnor2_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__xnor2_2.sp ('sky130_fd_sc_ls__xnor2_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/xnor2/sky130_fd_sc_ls__xnor2_2.spice ('sky130_fd_sc_ls__xnor2_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:30:13 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__xnor2_2 sky130_fd_sc_ls__xnor2_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__xnor2_2
+SOURCE CELL NAME: sky130_fd_sc_ls__xnor2_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 11 11
+
+ Instances: 8 8 MN (4 pins)
+ 8 8 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 17 16
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 3 3 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1 (5 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 3 3 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 12 layout mos transistors were reduced to 6.
+ 6 mos transistors were deleted by parallel reduction.
+ 12 source mos transistors were reduced to 6.
+ 6 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A B VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/xnor2/sky130_fd_sc_ls__xnor2_2.pex.spice b/cells/xnor2/sky130_fd_sc_ls__xnor2_2.pex.spice
index ba13c48..53a23e3 100644
--- a/cells/xnor2/sky130_fd_sc_ls__xnor2_2.pex.spice
+++ b/cells/xnor2/sky130_fd_sc_ls__xnor2_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__xnor2_2.pex.spice
-* Created: Fri Aug 28 14:08:51 2020
+* Created: Wed Sep 2 11:30:17 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/xnor2/sky130_fd_sc_ls__xnor2_2.pxi.spice b/cells/xnor2/sky130_fd_sc_ls__xnor2_2.pxi.spice
index 465c509..57f7543 100644
--- a/cells/xnor2/sky130_fd_sc_ls__xnor2_2.pxi.spice
+++ b/cells/xnor2/sky130_fd_sc_ls__xnor2_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__xnor2_2.pxi.spice
-* Created: Fri Aug 28 14:08:51 2020
+* Created: Wed Sep 2 11:30:17 2020
*
x_PM_SKY130_FD_SC_LS__XNOR2_2%A N_A_c_91_n N_A_M1000_g N_A_c_92_n N_A_M1013_g
+ N_A_c_93_n N_A_M1010_g N_A_c_94_n N_A_M1005_g N_A_c_95_n N_A_M1011_g
diff --git a/cells/xnor2/sky130_fd_sc_ls__xnor2_2.spice b/cells/xnor2/sky130_fd_sc_ls__xnor2_2.spice
index e7ed687..437387a 100644
--- a/cells/xnor2/sky130_fd_sc_ls__xnor2_2.spice
+++ b/cells/xnor2/sky130_fd_sc_ls__xnor2_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__xnor2_2.spice
-* Created: Fri Aug 28 14:08:51 2020
+* Created: Wed Sep 2 11:30:17 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/xnor2/sky130_fd_sc_ls__xnor2_4.lvs.report b/cells/xnor2/sky130_fd_sc_ls__xnor2_4.lvs.report
new file mode 100644
index 0000000..4e303b6
--- /dev/null
+++ b/cells/xnor2/sky130_fd_sc_ls__xnor2_4.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__xnor2_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__xnor2_4.sp ('sky130_fd_sc_ls__xnor2_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/xnor2/sky130_fd_sc_ls__xnor2_4.spice ('sky130_fd_sc_ls__xnor2_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:30:21 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__xnor2_4 sky130_fd_sc_ls__xnor2_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__xnor2_4
+SOURCE CELL NAME: sky130_fd_sc_ls__xnor2_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 11 11
+
+ Instances: 16 16 MN (4 pins)
+ 14 14 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 31 30
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 3 3 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1 (5 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 3 3 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 30 layout mos transistors were reduced to 10.
+ 20 mos transistors were deleted by parallel reduction.
+ 30 source mos transistors were reduced to 10.
+ 20 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A B VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/xnor2/sky130_fd_sc_ls__xnor2_4.pex.spice b/cells/xnor2/sky130_fd_sc_ls__xnor2_4.pex.spice
index 1854c05..42eb0b4 100644
--- a/cells/xnor2/sky130_fd_sc_ls__xnor2_4.pex.spice
+++ b/cells/xnor2/sky130_fd_sc_ls__xnor2_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__xnor2_4.pex.spice
-* Created: Fri Aug 28 14:09:01 2020
+* Created: Wed Sep 2 11:30:24 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/xnor2/sky130_fd_sc_ls__xnor2_4.pxi.spice b/cells/xnor2/sky130_fd_sc_ls__xnor2_4.pxi.spice
index e6acffd..5a79ea0 100644
--- a/cells/xnor2/sky130_fd_sc_ls__xnor2_4.pxi.spice
+++ b/cells/xnor2/sky130_fd_sc_ls__xnor2_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__xnor2_4.pxi.spice
-* Created: Fri Aug 28 14:09:01 2020
+* Created: Wed Sep 2 11:30:24 2020
*
x_PM_SKY130_FD_SC_LS__XNOR2_4%A N_A_M1012_g N_A_c_157_n N_A_M1015_g N_A_c_158_n
+ N_A_M1016_g N_A_M1027_g N_A_M1002_g N_A_c_159_n N_A_M1000_g N_A_M1006_g
diff --git a/cells/xnor2/sky130_fd_sc_ls__xnor2_4.spice b/cells/xnor2/sky130_fd_sc_ls__xnor2_4.spice
index 3f6911a..2c2ebb9 100644
--- a/cells/xnor2/sky130_fd_sc_ls__xnor2_4.spice
+++ b/cells/xnor2/sky130_fd_sc_ls__xnor2_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__xnor2_4.spice
-* Created: Fri Aug 28 14:09:01 2020
+* Created: Wed Sep 2 11:30:24 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/xnor3/sky130_fd_sc_ls__xnor3_1.lvs.report b/cells/xnor3/sky130_fd_sc_ls__xnor3_1.lvs.report
new file mode 100644
index 0000000..fc2c0b2
--- /dev/null
+++ b/cells/xnor3/sky130_fd_sc_ls__xnor3_1.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__xnor3_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__xnor3_1.sp ('sky130_fd_sc_ls__xnor3_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/xnor3/sky130_fd_sc_ls__xnor3_1.spice ('sky130_fd_sc_ls__xnor3_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:30:28 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__xnor3_1 sky130_fd_sc_ls__xnor3_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__xnor3_1
+SOURCE CELL NAME: sky130_fd_sc_ls__xnor3_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 15 15
+
+ Instances: 11 11 MN (4 pins)
+ 11 11 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 23 22
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 15 15
+
+ Instances: 11 11 MN (4 pins)
+ 11 11 MP (4 pins)
+ ------ ------
+ Total Inst: 22 22
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 15 15 0 0
+
+ Instances: 11 11 0 0 MN(NSHORT)
+ 11 11 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 22 22 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB C B A X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/xnor3/sky130_fd_sc_ls__xnor3_1.pex.spice b/cells/xnor3/sky130_fd_sc_ls__xnor3_1.pex.spice
index 535096b..148ca19 100644
--- a/cells/xnor3/sky130_fd_sc_ls__xnor3_1.pex.spice
+++ b/cells/xnor3/sky130_fd_sc_ls__xnor3_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__xnor3_1.pex.spice
-* Created: Fri Aug 28 14:09:11 2020
+* Created: Wed Sep 2 11:30:31 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/xnor3/sky130_fd_sc_ls__xnor3_1.pxi.spice b/cells/xnor3/sky130_fd_sc_ls__xnor3_1.pxi.spice
index 14c697b..588cba9 100644
--- a/cells/xnor3/sky130_fd_sc_ls__xnor3_1.pxi.spice
+++ b/cells/xnor3/sky130_fd_sc_ls__xnor3_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__xnor3_1.pxi.spice
-* Created: Fri Aug 28 14:09:11 2020
+* Created: Wed Sep 2 11:30:31 2020
*
x_PM_SKY130_FD_SC_LS__XNOR3_1%A_81_268# N_A_81_268#_M1011_d N_A_81_268#_M1007_d
+ N_A_81_268#_c_168_n N_A_81_268#_M1000_g N_A_81_268#_c_169_n
diff --git a/cells/xnor3/sky130_fd_sc_ls__xnor3_1.spice b/cells/xnor3/sky130_fd_sc_ls__xnor3_1.spice
index 9c6084c..6ed9d4b 100644
--- a/cells/xnor3/sky130_fd_sc_ls__xnor3_1.spice
+++ b/cells/xnor3/sky130_fd_sc_ls__xnor3_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__xnor3_1.spice
-* Created: Fri Aug 28 14:09:11 2020
+* Created: Wed Sep 2 11:30:31 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/xnor3/sky130_fd_sc_ls__xnor3_2.lvs.report b/cells/xnor3/sky130_fd_sc_ls__xnor3_2.lvs.report
new file mode 100644
index 0000000..fe0273f
--- /dev/null
+++ b/cells/xnor3/sky130_fd_sc_ls__xnor3_2.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__xnor3_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__xnor3_2.sp ('sky130_fd_sc_ls__xnor3_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/xnor3/sky130_fd_sc_ls__xnor3_2.spice ('sky130_fd_sc_ls__xnor3_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:30:35 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__xnor3_2 sky130_fd_sc_ls__xnor3_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__xnor3_2
+SOURCE CELL NAME: sky130_fd_sc_ls__xnor3_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 15 15
+
+ Instances: 12 12 MN (4 pins)
+ 12 12 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 25 24
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 15 15
+
+ Instances: 11 11 MN (4 pins)
+ 11 11 MP (4 pins)
+ ------ ------
+ Total Inst: 22 22
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 15 15 0 0
+
+ Instances: 11 11 0 0 MN(NSHORT)
+ 11 11 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 22 22 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A B C VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/xnor3/sky130_fd_sc_ls__xnor3_2.pex.spice b/cells/xnor3/sky130_fd_sc_ls__xnor3_2.pex.spice
index ae61cc0..46327a7 100644
--- a/cells/xnor3/sky130_fd_sc_ls__xnor3_2.pex.spice
+++ b/cells/xnor3/sky130_fd_sc_ls__xnor3_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__xnor3_2.pex.spice
-* Created: Fri Aug 28 14:09:40 2020
+* Created: Wed Sep 2 11:30:39 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/xnor3/sky130_fd_sc_ls__xnor3_2.pxi.spice b/cells/xnor3/sky130_fd_sc_ls__xnor3_2.pxi.spice
index 7afb23d..588a257 100644
--- a/cells/xnor3/sky130_fd_sc_ls__xnor3_2.pxi.spice
+++ b/cells/xnor3/sky130_fd_sc_ls__xnor3_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__xnor3_2.pxi.spice
-* Created: Fri Aug 28 14:09:40 2020
+* Created: Wed Sep 2 11:30:39 2020
*
x_PM_SKY130_FD_SC_LS__XNOR3_2%A_83_247# N_A_83_247#_M1007_d N_A_83_247#_M1000_d
+ N_A_83_247#_M1011_d N_A_83_247#_M1012_d N_A_83_247#_c_175_n
diff --git a/cells/xnor3/sky130_fd_sc_ls__xnor3_2.spice b/cells/xnor3/sky130_fd_sc_ls__xnor3_2.spice
index e1617c4..4a13564 100644
--- a/cells/xnor3/sky130_fd_sc_ls__xnor3_2.spice
+++ b/cells/xnor3/sky130_fd_sc_ls__xnor3_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__xnor3_2.spice
-* Created: Fri Aug 28 14:09:40 2020
+* Created: Wed Sep 2 11:30:39 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/xnor3/sky130_fd_sc_ls__xnor3_4.lvs.report b/cells/xnor3/sky130_fd_sc_ls__xnor3_4.lvs.report
new file mode 100644
index 0000000..0e1224e
--- /dev/null
+++ b/cells/xnor3/sky130_fd_sc_ls__xnor3_4.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__xnor3_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__xnor3_4.sp ('sky130_fd_sc_ls__xnor3_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/xnor3/sky130_fd_sc_ls__xnor3_4.spice ('sky130_fd_sc_ls__xnor3_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:30:43 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__xnor3_4 sky130_fd_sc_ls__xnor3_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__xnor3_4
+SOURCE CELL NAME: sky130_fd_sc_ls__xnor3_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 15 15
+
+ Instances: 14 14 MN (4 pins)
+ 14 14 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 29 28
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 15 15
+
+ Instances: 11 11 MN (4 pins)
+ 11 11 MP (4 pins)
+ ------ ------
+ Total Inst: 22 22
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 15 15 0 0
+
+ Instances: 11 11 0 0 MN(NSHORT)
+ 11 11 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 22 22 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 8 layout mos transistors were reduced to 2.
+ 6 mos transistors were deleted by parallel reduction.
+ 8 source mos transistors were reduced to 2.
+ 6 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A B C VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/xnor3/sky130_fd_sc_ls__xnor3_4.pex.spice b/cells/xnor3/sky130_fd_sc_ls__xnor3_4.pex.spice
index b03e53f..e8a4bee 100644
--- a/cells/xnor3/sky130_fd_sc_ls__xnor3_4.pex.spice
+++ b/cells/xnor3/sky130_fd_sc_ls__xnor3_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__xnor3_4.pex.spice
-* Created: Fri Aug 28 14:09:51 2020
+* Created: Wed Sep 2 11:30:46 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/xnor3/sky130_fd_sc_ls__xnor3_4.pxi.spice b/cells/xnor3/sky130_fd_sc_ls__xnor3_4.pxi.spice
index ed18e56..5c3b12b 100644
--- a/cells/xnor3/sky130_fd_sc_ls__xnor3_4.pxi.spice
+++ b/cells/xnor3/sky130_fd_sc_ls__xnor3_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__xnor3_4.pxi.spice
-* Created: Fri Aug 28 14:09:51 2020
+* Created: Wed Sep 2 11:30:46 2020
*
x_PM_SKY130_FD_SC_LS__XNOR3_4%A_75_227# N_A_75_227#_M1000_d N_A_75_227#_M1004_d
+ N_A_75_227#_M1010_d N_A_75_227#_M1017_d N_A_75_227#_c_190_n
diff --git a/cells/xnor3/sky130_fd_sc_ls__xnor3_4.spice b/cells/xnor3/sky130_fd_sc_ls__xnor3_4.spice
index c7318b4..8491449 100644
--- a/cells/xnor3/sky130_fd_sc_ls__xnor3_4.spice
+++ b/cells/xnor3/sky130_fd_sc_ls__xnor3_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__xnor3_4.spice
-* Created: Fri Aug 28 14:09:51 2020
+* Created: Wed Sep 2 11:30:46 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/xor2/sky130_fd_sc_ls__xor2_1.lvs.report b/cells/xor2/sky130_fd_sc_ls__xor2_1.lvs.report
new file mode 100644
index 0000000..897c9d2
--- /dev/null
+++ b/cells/xor2/sky130_fd_sc_ls__xor2_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__xor2_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__xor2_1.sp ('sky130_fd_sc_ls__xor2_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/xor2/sky130_fd_sc_ls__xor2_1.spice ('sky130_fd_sc_ls__xor2_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:30:50 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__xor2_1 sky130_fd_sc_ls__xor2_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__xor2_1
+SOURCE CELL NAME: sky130_fd_sc_ls__xor2_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 11 11
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 3 3 MN (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMP_2_1 (5 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 3 3 0 0 MN(NSHORT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMP_2_1
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/xor2/sky130_fd_sc_ls__xor2_1.pex.spice b/cells/xor2/sky130_fd_sc_ls__xor2_1.pex.spice
index fce2752..68f8b08 100644
--- a/cells/xor2/sky130_fd_sc_ls__xor2_1.pex.spice
+++ b/cells/xor2/sky130_fd_sc_ls__xor2_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__xor2_1.pex.spice
-* Created: Fri Aug 28 14:10:01 2020
+* Created: Wed Sep 2 11:30:53 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/xor2/sky130_fd_sc_ls__xor2_1.pxi.spice b/cells/xor2/sky130_fd_sc_ls__xor2_1.pxi.spice
index b908560..2c8459c 100644
--- a/cells/xor2/sky130_fd_sc_ls__xor2_1.pxi.spice
+++ b/cells/xor2/sky130_fd_sc_ls__xor2_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__xor2_1.pxi.spice
-* Created: Fri Aug 28 14:10:01 2020
+* Created: Wed Sep 2 11:30:53 2020
*
x_PM_SKY130_FD_SC_LS__XOR2_1%B N_B_c_68_n N_B_M1003_g N_B_M1000_g N_B_M1002_g
+ N_B_c_64_n N_B_M1004_g N_B_c_65_n B N_B_c_66_n N_B_c_67_n
diff --git a/cells/xor2/sky130_fd_sc_ls__xor2_1.spice b/cells/xor2/sky130_fd_sc_ls__xor2_1.spice
index d455141..42ab42a 100644
--- a/cells/xor2/sky130_fd_sc_ls__xor2_1.spice
+++ b/cells/xor2/sky130_fd_sc_ls__xor2_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__xor2_1.spice
-* Created: Fri Aug 28 14:10:01 2020
+* Created: Wed Sep 2 11:30:53 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/xor2/sky130_fd_sc_ls__xor2_2.lvs.report b/cells/xor2/sky130_fd_sc_ls__xor2_2.lvs.report
new file mode 100644
index 0000000..31b6b88
--- /dev/null
+++ b/cells/xor2/sky130_fd_sc_ls__xor2_2.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__xor2_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__xor2_2.sp ('sky130_fd_sc_ls__xor2_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/xor2/sky130_fd_sc_ls__xor2_2.spice ('sky130_fd_sc_ls__xor2_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:30:57 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__xor2_2 sky130_fd_sc_ls__xor2_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__xor2_2
+SOURCE CELL NAME: sky130_fd_sc_ls__xor2_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 11 11
+
+ Instances: 7 7 MN (4 pins)
+ 8 8 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 16 15
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 3 3 MN (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMP_2_1 (5 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 3 3 0 0 MN(NSHORT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMP_2_1
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 10 layout mos transistors were reduced to 5.
+ 5 mos transistors were deleted by parallel reduction.
+ 10 source mos transistors were reduced to 5.
+ 5 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A B VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/xor2/sky130_fd_sc_ls__xor2_2.pex.spice b/cells/xor2/sky130_fd_sc_ls__xor2_2.pex.spice
index 710338a..c3c24e6 100644
--- a/cells/xor2/sky130_fd_sc_ls__xor2_2.pex.spice
+++ b/cells/xor2/sky130_fd_sc_ls__xor2_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__xor2_2.pex.spice
-* Created: Fri Aug 28 14:10:11 2020
+* Created: Wed Sep 2 11:31:00 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/xor2/sky130_fd_sc_ls__xor2_2.pxi.spice b/cells/xor2/sky130_fd_sc_ls__xor2_2.pxi.spice
index 4402196..dad7f23 100644
--- a/cells/xor2/sky130_fd_sc_ls__xor2_2.pxi.spice
+++ b/cells/xor2/sky130_fd_sc_ls__xor2_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__xor2_2.pxi.spice
-* Created: Fri Aug 28 14:10:11 2020
+* Created: Wed Sep 2 11:31:00 2020
*
x_PM_SKY130_FD_SC_LS__XOR2_2%A N_A_c_80_n N_A_c_90_n N_A_M1012_g N_A_M1007_g
+ N_A_M1003_g N_A_c_91_n N_A_M1006_g N_A_M1010_g N_A_c_92_n N_A_M1011_g
diff --git a/cells/xor2/sky130_fd_sc_ls__xor2_2.spice b/cells/xor2/sky130_fd_sc_ls__xor2_2.spice
index 17b07bb..83ae18b 100644
--- a/cells/xor2/sky130_fd_sc_ls__xor2_2.spice
+++ b/cells/xor2/sky130_fd_sc_ls__xor2_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__xor2_2.spice
-* Created: Fri Aug 28 14:10:11 2020
+* Created: Wed Sep 2 11:31:00 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/xor2/sky130_fd_sc_ls__xor2_4.lvs.report b/cells/xor2/sky130_fd_sc_ls__xor2_4.lvs.report
new file mode 100644
index 0000000..0ff3136
--- /dev/null
+++ b/cells/xor2/sky130_fd_sc_ls__xor2_4.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__xor2_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__xor2_4.sp ('sky130_fd_sc_ls__xor2_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/xor2/sky130_fd_sc_ls__xor2_4.spice ('sky130_fd_sc_ls__xor2_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:31:04 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__xor2_4 sky130_fd_sc_ls__xor2_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__xor2_4
+SOURCE CELL NAME: sky130_fd_sc_ls__xor2_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 11 11
+
+ Instances: 14 14 MN (4 pins)
+ 16 16 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 31 30
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 3 3 MN (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMP_2_1 (5 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 3 3 0 0 MN(NSHORT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMP_2_1
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 30 layout mos transistors were reduced to 10.
+ 20 mos transistors were deleted by parallel reduction.
+ 30 source mos transistors were reduced to 10.
+ 20 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A B VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/xor2/sky130_fd_sc_ls__xor2_4.pex.spice b/cells/xor2/sky130_fd_sc_ls__xor2_4.pex.spice
index 311ccf5..368ef4c 100644
--- a/cells/xor2/sky130_fd_sc_ls__xor2_4.pex.spice
+++ b/cells/xor2/sky130_fd_sc_ls__xor2_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__xor2_4.pex.spice
-* Created: Fri Aug 28 14:10:21 2020
+* Created: Wed Sep 2 11:31:07 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/xor2/sky130_fd_sc_ls__xor2_4.pxi.spice b/cells/xor2/sky130_fd_sc_ls__xor2_4.pxi.spice
index 0e17293..9d43536 100644
--- a/cells/xor2/sky130_fd_sc_ls__xor2_4.pxi.spice
+++ b/cells/xor2/sky130_fd_sc_ls__xor2_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__xor2_4.pxi.spice
-* Created: Fri Aug 28 14:10:21 2020
+* Created: Wed Sep 2 11:31:07 2020
*
x_PM_SKY130_FD_SC_LS__XOR2_4%A N_A_c_161_n N_A_M1021_g N_A_M1000_g N_A_c_162_n
+ N_A_M1023_g N_A_M1016_g N_A_c_163_n N_A_M1005_g N_A_M1009_g N_A_c_164_n
diff --git a/cells/xor2/sky130_fd_sc_ls__xor2_4.spice b/cells/xor2/sky130_fd_sc_ls__xor2_4.spice
index 9f71150..e0e52bd 100644
--- a/cells/xor2/sky130_fd_sc_ls__xor2_4.spice
+++ b/cells/xor2/sky130_fd_sc_ls__xor2_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__xor2_4.spice
-* Created: Fri Aug 28 14:10:21 2020
+* Created: Wed Sep 2 11:31:07 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/xor3/sky130_fd_sc_ls__xor3_1.lvs.report b/cells/xor3/sky130_fd_sc_ls__xor3_1.lvs.report
new file mode 100644
index 0000000..8ec9d59
--- /dev/null
+++ b/cells/xor3/sky130_fd_sc_ls__xor3_1.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__xor3_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__xor3_1.sp ('sky130_fd_sc_ls__xor3_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/xor3/sky130_fd_sc_ls__xor3_1.spice ('sky130_fd_sc_ls__xor3_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:31:11 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__xor3_1 sky130_fd_sc_ls__xor3_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__xor3_1
+SOURCE CELL NAME: sky130_fd_sc_ls__xor3_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 15 15
+
+ Instances: 11 11 MN (4 pins)
+ 11 11 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 23 22
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 15 15
+
+ Instances: 11 11 MN (4 pins)
+ 11 11 MP (4 pins)
+ ------ ------
+ Total Inst: 22 22
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 15 15 0 0
+
+ Instances: 11 11 0 0 MN(NSHORT)
+ 11 11 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 22 22 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A B C VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/xor3/sky130_fd_sc_ls__xor3_1.pex.spice b/cells/xor3/sky130_fd_sc_ls__xor3_1.pex.spice
index a86686d..97d3b5b 100644
--- a/cells/xor3/sky130_fd_sc_ls__xor3_1.pex.spice
+++ b/cells/xor3/sky130_fd_sc_ls__xor3_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__xor3_1.pex.spice
-* Created: Fri Aug 28 14:10:49 2020
+* Created: Wed Sep 2 11:31:15 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/xor3/sky130_fd_sc_ls__xor3_1.pxi.spice b/cells/xor3/sky130_fd_sc_ls__xor3_1.pxi.spice
index 62d11a1..f36e08b 100644
--- a/cells/xor3/sky130_fd_sc_ls__xor3_1.pxi.spice
+++ b/cells/xor3/sky130_fd_sc_ls__xor3_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__xor3_1.pxi.spice
-* Created: Fri Aug 28 14:10:49 2020
+* Created: Wed Sep 2 11:31:15 2020
*
x_PM_SKY130_FD_SC_LS__XOR3_1%A_84_108# N_A_84_108#_M1021_d N_A_84_108#_M1018_d
+ N_A_84_108#_M1020_d N_A_84_108#_M1008_d N_A_84_108#_M1017_g
diff --git a/cells/xor3/sky130_fd_sc_ls__xor3_1.spice b/cells/xor3/sky130_fd_sc_ls__xor3_1.spice
index a97e88a..c54d812 100644
--- a/cells/xor3/sky130_fd_sc_ls__xor3_1.spice
+++ b/cells/xor3/sky130_fd_sc_ls__xor3_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__xor3_1.spice
-* Created: Fri Aug 28 14:10:49 2020
+* Created: Wed Sep 2 11:31:15 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/xor3/sky130_fd_sc_ls__xor3_2.lvs.report b/cells/xor3/sky130_fd_sc_ls__xor3_2.lvs.report
new file mode 100644
index 0000000..4b6ec5f
--- /dev/null
+++ b/cells/xor3/sky130_fd_sc_ls__xor3_2.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__xor3_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__xor3_2.sp ('sky130_fd_sc_ls__xor3_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/xor3/sky130_fd_sc_ls__xor3_2.spice ('sky130_fd_sc_ls__xor3_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:31:19 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__xor3_2 sky130_fd_sc_ls__xor3_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__xor3_2
+SOURCE CELL NAME: sky130_fd_sc_ls__xor3_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 15 15
+
+ Instances: 12 12 MN (4 pins)
+ 12 12 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 25 24
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 15 15
+
+ Instances: 11 11 MN (4 pins)
+ 11 11 MP (4 pins)
+ ------ ------
+ Total Inst: 22 22
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 15 15 0 0
+
+ Instances: 11 11 0 0 MN(NSHORT)
+ 11 11 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 22 22 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A B C VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/xor3/sky130_fd_sc_ls__xor3_2.pex.spice b/cells/xor3/sky130_fd_sc_ls__xor3_2.pex.spice
index 9c265b9..9b616f9 100644
--- a/cells/xor3/sky130_fd_sc_ls__xor3_2.pex.spice
+++ b/cells/xor3/sky130_fd_sc_ls__xor3_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__xor3_2.pex.spice
-* Created: Fri Aug 28 14:11:00 2020
+* Created: Wed Sep 2 11:31:22 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/xor3/sky130_fd_sc_ls__xor3_2.pxi.spice b/cells/xor3/sky130_fd_sc_ls__xor3_2.pxi.spice
index cae1614..8dc3f43 100644
--- a/cells/xor3/sky130_fd_sc_ls__xor3_2.pxi.spice
+++ b/cells/xor3/sky130_fd_sc_ls__xor3_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__xor3_2.pxi.spice
-* Created: Fri Aug 28 14:11:00 2020
+* Created: Wed Sep 2 11:31:22 2020
*
x_PM_SKY130_FD_SC_LS__XOR3_2%A_83_289# N_A_83_289#_M1022_d N_A_83_289#_M1020_d
+ N_A_83_289#_M1006_d N_A_83_289#_M1003_d N_A_83_289#_M1017_g
diff --git a/cells/xor3/sky130_fd_sc_ls__xor3_2.spice b/cells/xor3/sky130_fd_sc_ls__xor3_2.spice
index f856b6c..ac95371 100644
--- a/cells/xor3/sky130_fd_sc_ls__xor3_2.spice
+++ b/cells/xor3/sky130_fd_sc_ls__xor3_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__xor3_2.spice
-* Created: Fri Aug 28 14:11:00 2020
+* Created: Wed Sep 2 11:31:22 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/xor3/sky130_fd_sc_ls__xor3_4.lvs.report b/cells/xor3/sky130_fd_sc_ls__xor3_4.lvs.report
new file mode 100644
index 0000000..845c1b0
--- /dev/null
+++ b/cells/xor3/sky130_fd_sc_ls__xor3_4.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_ls__xor3_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_ls__xor3_4.sp ('sky130_fd_sc_ls__xor3_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ls/cells/xor3/sky130_fd_sc_ls__xor3_4.spice ('sky130_fd_sc_ls__xor3_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 11:31:26 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_ls__xor3_4 sky130_fd_sc_ls__xor3_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_ls__xor3_4
+SOURCE CELL NAME: sky130_fd_sc_ls__xor3_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 15 15
+
+ Instances: 14 14 MN (4 pins)
+ 14 14 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 29 28
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 15 15
+
+ Instances: 11 11 MN (4 pins)
+ 11 11 MP (4 pins)
+ ------ ------
+ Total Inst: 22 22
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 15 15 0 0
+
+ Instances: 11 11 0 0 MN(NSHORT)
+ 11 11 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 22 22 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 8 layout mos transistors were reduced to 2.
+ 6 mos transistors were deleted by parallel reduction.
+ 8 source mos transistors were reduced to 2.
+ 6 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A B C VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/xor3/sky130_fd_sc_ls__xor3_4.pex.spice b/cells/xor3/sky130_fd_sc_ls__xor3_4.pex.spice
index 6898220..7394076 100644
--- a/cells/xor3/sky130_fd_sc_ls__xor3_4.pex.spice
+++ b/cells/xor3/sky130_fd_sc_ls__xor3_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__xor3_4.pex.spice
-* Created: Fri Aug 28 14:11:10 2020
+* Created: Wed Sep 2 11:31:29 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/xor3/sky130_fd_sc_ls__xor3_4.pxi.spice b/cells/xor3/sky130_fd_sc_ls__xor3_4.pxi.spice
index 8411d09..5b34ebd 100644
--- a/cells/xor3/sky130_fd_sc_ls__xor3_4.pxi.spice
+++ b/cells/xor3/sky130_fd_sc_ls__xor3_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__xor3_4.pxi.spice
-* Created: Fri Aug 28 14:11:10 2020
+* Created: Wed Sep 2 11:31:29 2020
*
x_PM_SKY130_FD_SC_LS__XOR3_4%A_74_294# N_A_74_294#_M1024_d N_A_74_294#_M1026_d
+ N_A_74_294#_M1019_d N_A_74_294#_M1014_d N_A_74_294#_M1006_g
diff --git a/cells/xor3/sky130_fd_sc_ls__xor3_4.spice b/cells/xor3/sky130_fd_sc_ls__xor3_4.spice
index 6a1188f..9833782 100644
--- a/cells/xor3/sky130_fd_sc_ls__xor3_4.spice
+++ b/cells/xor3/sky130_fd_sc_ls__xor3_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_ls__xor3_4.spice
-* Created: Fri Aug 28 14:11:10 2020
+* Created: Wed Sep 2 11:31:29 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
