| { |
| "area": 39.96, |
| "cell_footprint": "sky130_fd_sc_ls__sdfxtp", |
| "cell_leakage_power": 11.90586, |
| "driver_waveform_fall": "ramp", |
| "driver_waveform_rise": "ramp", |
| "ff,IQ,IQ_N": { |
| "clocked_on": "CLK", |
| "next_state": "(D&!SCE) | (SCD&SCE)" |
| }, |
| "leakage_power": [ |
| { |
| "value": 14.1667167, |
| "when": "D&!SCD&!SCE&CLK" |
| }, |
| { |
| "value": 12.0181198, |
| "when": "!D&!SCD&SCE&CLK" |
| }, |
| { |
| "value": 11.5762111, |
| "when": "!D&SCD&!SCE&CLK" |
| }, |
| { |
| "value": 11.581891, |
| "when": "!D&!SCD&!SCE&!CLK" |
| }, |
| { |
| "value": 11.2895053, |
| "when": "!D&!SCD&!SCE&CLK" |
| }, |
| { |
| "value": 12.6849713, |
| "when": "D&!SCD&SCE&CLK" |
| }, |
| { |
| "value": 9.4541548, |
| "when": "D&SCD&!SCE&!CLK" |
| }, |
| { |
| "value": 10.91367, |
| "when": "!D&SCD&SCE&!CLK" |
| }, |
| { |
| "value": 10.3915356, |
| "when": "D&SCD&SCE&!CLK" |
| }, |
| { |
| "value": 9.2191659, |
| "when": "D&SCD&!SCE&CLK" |
| }, |
| { |
| "value": 10.1390629, |
| "when": "D&!SCD&!SCE&!CLK" |
| }, |
| { |
| "value": 14.9413957, |
| "when": "!D&SCD&SCE&CLK" |
| }, |
| { |
| "value": 12.5810979, |
| "when": "!D&!SCD&SCE&!CLK" |
| }, |
| { |
| "value": 14.4193057, |
| "when": "D&SCD&SCE&CLK" |
| }, |
| { |
| "value": 12.9777096, |
| "when": "D&!SCD&SCE&!CLK" |
| }, |
| { |
| "value": 12.1393073, |
| "when": "!D&SCD&!SCE&!CLK" |
| } |
| ], |
| "pg_pin,VGND": { |
| "pg_type": "primary_ground", |
| "related_bias_pin": "VPB", |
| "voltage_name": "VGND" |
| }, |
| "pg_pin,VNB": { |
| "pg_type": "nwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VNB" |
| }, |
| "pg_pin,VPB": { |
| "pg_type": "pwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VPB" |
| }, |
| "pg_pin,VPWR": { |
| "pg_type": "primary_power", |
| "related_bias_pin": "VNB", |
| "voltage_name": "VPWR" |
| }, |
| "pin,CLK": { |
| "capacitance": 0.002696, |
| "clock": "true", |
| "direction": "input", |
| "fall_capacitance": 0.0026, |
| "internal_power": { |
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| 1.48163, |
| 2.22233, |
| 3.33333, |
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| ], |
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| 0.0165775, |
| 0.0165669, |
| 0.0165637, |
| 0.0165718 |
| ] |
| }, |
| "rise_power,hidden_pwr_template13": { |
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| 0.0119334, |
| 0.0119077 |
| ] |
| } |
| }, |
| "max_transition": 5.0, |
| "min_pulse_width_high": 0.364243, |
| "min_pulse_width_low": 0.944257, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
| "rise_capacitance": 0.002793 |
| }, |
| "pin,D": { |
| "capacitance": 0.001834, |
| "clock": "false", |
| "direction": "input", |
| "fall_capacitance": 0.001742, |
| "internal_power": { |
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| 0.00594, |
| 0.0059265, |
| 0.0059181, |
| 0.0059175 |
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| 0.0012368, |
| 0.0012019, |
| 0.0011621 |
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| } |
| }, |
| "max_transition": 5.0, |
| "nextstate_type": "data", |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
| "rise_capacitance": 0.001925, |
| "timing": [ |
| { |
| "clk_width": 6.8e-08, |
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| [ |
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| [ |
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| [ |
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| 0.935431, |
| 1.3091018, |
| 1.6546964, |
| 1.979539 |
| ] |
| ] |
| }, |
| "related_pin": "CLK", |
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| [ |
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| [ |
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| 1.7275316, |
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| [ |
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| 2.1319913 |
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| [ |
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| 1.5826749, |
| 1.8184064, |
| 2.0382685 |
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| [ |
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| [ |
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| [ |
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| [ |
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| 1.3252422 |
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| ] |
| }, |
| "sim_opt": "runlvl=5 accurate=1", |
| "timing_type": "setup_rising", |
| "violation_delay_degrade_pct": 10 |
| }, |
| { |
| "clk_width": 6.8e-08, |
| "fall_constraint,vio_10_10_1": { |
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| 0.0333333, |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| ] |
| }, |
| "related_pin": "CLK", |
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| }, |
| "test_cell": { |
| "ff,IQ,IQ_N": { |
| "clocked_on": "CLK", |
| "next_state": "D" |
| }, |
| "pin,CLK": { |
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| }, |
| "pin,D": { |
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| }, |
| "pin,Q": { |
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| "function": "IQ", |
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| }, |
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| }, |
| "pin,SCE": { |
| "direction": "input", |
| "signal_type": "test_scan_enable" |
| } |
| } |
| } |
