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foss-eda-tools / skywater-pdk / libs / sky130_fd_sc_ls / refs/heads/main / . / cells / dlclkp / sky130_fd_sc_ls__dlclkp_4__ss_n40C_1v60_ccsnoise.lib.json
blob: eded7c650705305dcf8e5b8ee315776abaaeb227 [file] [log] [blame]
{
"area": 28.7712,
"cell_footprint": "sky130_fd_sc_ls__dlclkp",
"cell_leakage_power": 0.03640226,
"clock_gating_integrated_cell": "latch_posedge",
"driver_waveform_fall": "ramp",
"driver_waveform_rise": "ramp",
"leakage_power": [
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"pg_pin,VGND": {
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"voltage_name": "VGND"
},
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"pg_pin,VPB": {
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"pg_pin,VPWR": {
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},
"pin,CLK": {
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0.2322333,
0.3301028,
0.4745725,
0.6962703,
1.0203054,
1.5186825
],
[
0.045628,
0.083502,
0.1014171,
0.1288724,
0.171382,
0.2345453,
0.3300921,
0.4768433,
0.6940968,
1.0255143,
1.519613
],
[
0.0493437,
0.087468,
0.1054064,
0.1324517,
0.173686,
0.2345021,
0.3307394,
0.4774068,
0.695325,
1.0259845,
1.5191561
],
[
0.0532806,
0.0923058,
0.1098549,
0.136764,
0.1776164,
0.2381607,
0.3341462,
0.4765494,
0.6946227,
1.0259891,
1.5183379
]
]
},
"timing_sense": "positive_unate"
}
},
"pin,M0": {
"direction": "internal",
"internal_node": "M0",
"related_ground_pin": "VNB",
"related_power_pin": "VPWR"
},
"statetable,CLK GATE,M0": {
"table": [
"L L : - : L",
"L H : - : H",
"H - : - : N"
]
}
}