| { |
| "area": 22.3776, |
| "cell_footprint": "sky130_fd_sc_ls__dlclkp", |
| "cell_leakage_power": 113.0605, |
| "clock_gating_integrated_cell": "latch_posedge", |
| "driver_waveform_fall": "ramp", |
| "driver_waveform_rise": "ramp", |
| "leakage_power": [ |
| { |
| "value": 129.285624, |
| "when": "!GATE&!CLK" |
| }, |
| { |
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| "when": "!GATE&CLK" |
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| { |
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| "when": "GATE&!CLK" |
| }, |
| { |
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| "when": "GATE&CLK" |
| } |
| ], |
| "pg_pin,VGND": { |
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| "related_bias_pin": "VPB", |
| "voltage_name": "VGND" |
| }, |
| "pg_pin,VNB": { |
| "pg_type": "nwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VNB" |
| }, |
| "pg_pin,VPB": { |
| "pg_type": "pwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VPB" |
| }, |
| "pg_pin,VPWR": { |
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| "related_bias_pin": "VNB", |
| "voltage_name": "VPWR" |
| }, |
| "pin,CLK": { |
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| "clock": "true", |
| "clock_gate_clock_pin": "true", |
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| }, |
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| "clock_gate_enable_pin": "true", |
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| "max_transition": 1.5, |
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| "sim_opt": "runlvl=5 accurate=1", |
| "timing_type": "setup_rising", |
| "violation_delay_degrade_pct": 10 |
| }, |
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| }, |
| "sim_opt": "runlvl=5 accurate=1", |
| "timing_type": "hold_rising", |
| "violation_delay_degrade_pct": 10 |
| } |
| ] |
| }, |
| "pin,GCLK": { |
| "clock_gate_out_pin": "true", |
| "direction": "output", |
| "internal_power": { |
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| 1.0051087, |
| 1.4959217 |
| ], |
| [ |
| 0.0342937, |
| 0.1154813, |
| 0.1569369, |
| 0.2198682, |
| 0.3164317, |
| 0.4616442, |
| 0.6797059, |
| 1.0050031, |
| 1.4960356 |
| ], |
| [ |
| 0.0347032, |
| 0.1155106, |
| 0.1566692, |
| 0.2202434, |
| 0.315752, |
| 0.4607854, |
| 0.6785313, |
| 1.0062358, |
| 1.4953844 |
| ], |
| [ |
| 0.0369189, |
| 0.116553, |
| 0.1574778, |
| 0.2203115, |
| 0.3164583, |
| 0.4613805, |
| 0.6785743, |
| 1.0062818, |
| 1.4950393 |
| ], |
| [ |
| 0.0397257, |
| 0.1194168, |
| 0.1592538, |
| 0.2219946, |
| 0.3163336, |
| 0.4612883, |
| 0.6794641, |
| 1.0056427, |
| 1.4959918 |
| ], |
| [ |
| 0.0434526, |
| 0.1220645, |
| 0.1618611, |
| 0.2236152, |
| 0.3185841, |
| 0.4625631, |
| 0.6797885, |
| 1.0058898, |
| 1.4945312 |
| ], |
| [ |
| 0.0498397, |
| 0.1269343, |
| 0.1655148, |
| 0.2266634, |
| 0.3201507, |
| 0.4638776, |
| 0.6794203, |
| 1.0066803, |
| 1.4959356 |
| ], |
| [ |
| 0.0589521, |
| 0.1341795, |
| 0.1717891, |
| 0.2306132, |
| 0.3230771, |
| 0.464949, |
| 0.6810874, |
| 1.0059218, |
| 1.4966233 |
| ] |
| ] |
| }, |
| "timing_sense": "positive_unate" |
| } |
| }, |
| "pin,M0": { |
| "direction": "internal", |
| "internal_node": "M0", |
| "related_ground_pin": "VNB", |
| "related_power_pin": "VPWR" |
| }, |
| "statetable,CLK GATE,M0": { |
| "table": [ |
| "L L : - : L", |
| "L H : - : H", |
| "H - : - : N" |
| ] |
| } |
| } |
