{
  "area": 36.7632,
  "cell_footprint": "sdfxtp",
  "cell_leakage_power": 0.006973068,
  "driver_waveform_fall": "ramp",
  "driver_waveform_rise": "ramp",
  "ff IQ,IQ_N": {
    "clocked_on": "CLK",
    "next_state": "(D&!SCE) | (SCD&SCE)"
  },
  "leakage_power": [
    {
      "value": 0.0094687,
      "when": "D&!SCD&!SCE&CLK"
    },
    {
      "value": 0.0071467,
      "when": "!D&!SCD&SCE&CLK"
    },
    {
      "value": 0.0051162,
      "when": "!D&SCD&!SCE&CLK"
    },
    {
      "value": 0.0062256,
      "when": "!D&!SCD&!SCE&!CLK"
    },
    {
      "value": 0.0031026,
      "when": "!D&!SCD&!SCE&CLK"
    },
    {
      "value": 0.0053199,
      "when": "D&!SCD&SCE&CLK"
    },
    {
      "value": 0.007411,
      "when": "D&SCD&!SCE&CLK"
    },
    {
      "value": 0.0075116,
      "when": "D&!SCD&!SCE&!CLK"
    },
    {
      "value": 0.0072917,
      "when": "!D&SCD&SCE&CLK"
    },
    {
      "value": 0.0083678,
      "when": "!D&!SCD&SCE&!CLK"
    },
    {
      "value": 0.009469,
      "when": "D&SCD&SCE&CLK"
    },
    {
      "value": 0.0084429,
      "when": "D&!SCD&SCE&!CLK"
    },
    {
      "value": 0.0063373,
      "when": "!D&SCD&!SCE&!CLK"
    },
    {
      "value": 0.0075114,
      "when": "D&SCD&!SCE&!CLK"
    },
    {
      "value": 0.0053346,
      "when": "!D&SCD&SCE&!CLK"
    },
    {
      "value": 0.0075119,
      "when": "D&SCD&SCE&!CLK"
    }
  ],
  "pg_pin VGND": {
    "pg_type": "primary_ground",
    "voltage_name": "VGND"
  },
  "pg_pin VNB": {
    "pg_type": "primary_ground",
    "voltage_name": "VNB"
  },
  "pg_pin VPB": {
    "pg_type": "primary_power",
    "voltage_name": "VPB"
  },
  "pg_pin VPWR": {
    "pg_type": "primary_power",
    "voltage_name": "VPWR"
  },
  "pin CLK": {
    "capacitance": 0.002617,
    "clock": "true",
    "direction": "input",
    "fall_capacitance": 0.002447,
    "internal_power": {
      "fall_power hidden_pwr_template13": {
        "index_1": [
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          0.0578333,
          0.0867333,
          0.1301,
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          0.2927333,
          0.4390667,
          0.6585667,
          0.9878,
          1.4816333,
          2.2223333,
          3.3333333,
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        "values": [
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          0.0260376,
          0.0259262,
          0.025759,
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          0.0255758,
          0.0255164,
          0.0254273,
          0.0252937,
          0.0250931
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      },
      "rise_power hidden_pwr_template13": {
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        "values": [
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    },
    "max_transition": 1.5,
    "min_pulse_width_high": 0.204959,
    "min_pulse_width_low": 0.479587,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.002787
  },
  "pin D": {
    "capacitance": 0.001754,
    "clock": "false",
    "direction": "input",
    "fall_capacitance": 0.001651,
    "internal_power": {
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        "values": [
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      "rise_power hidden_pwr_template13": {
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          2.2223333,
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        ],
        "values": [
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          0.0022092,
          0.0021935,
          0.00217,
          0.0020698,
          0.0019195,
          0.0018525,
          0.0017521,
          0.0017172,
          0.0016648,
          0.0015863,
          0.0014685
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      }
    },
    "max_transition": 1.5,
    "nextstate_type": "data",
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.001856,
    "timing": [
      {
        "fall_constraint vio_10_10_1": {
          "index_1": [
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            0.1041667,
            0.2083333,
            0.4166667,
            0.8333333,
            1.6666667,
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          "values": [
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              0.2953757,
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              0.2249818,
              0.2546855,
              0.3165345,
              0.4475566,
              0.5797995,
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              0.8418438,
              0.9679831
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              0.1670065,
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              0.1879538,
              0.2164368,
              0.2795065,
              0.4117493,
              0.5427715,
              0.6737936,
              0.8035951,
              0.9297344
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          ]
        },
        "related_pin": "CLK",
        "rise_constraint vio_10_10_1": {
          "index_1": [
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            0.1041667,
            0.2083333,
            0.4166667,
            0.8333333,
            1.6666667,
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            4.1666667,
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          "index_2": [
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            0.4166667,
            0.8333333,
            1.6666667,
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          "values": [
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              0.1411602,
              0.2331198,
              0.310431,
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              0.4959779
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            [
              0.0184876,
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              0.0418763,
              0.0691387,
              0.121222,
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              0.2917135,
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              0.1969056,
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              0.3405417,
              0.4019837,
              0.4573223
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          ]
        },
        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "setup_rising",
        "violation_delay_degrade_pct": 10
      },
      {
        "fall_constraint vio_10_10_1": {
          "index_1": [
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            0.1041667,
            0.2083333,
            0.4166667,
            0.8333333,
            1.6666667,
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            0.4166667,
            0.8333333,
            1.6666667,
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          "values": [
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              -0.1890482,
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              -0.3800801,
              -0.5074401,
              -0.6360209,
              -0.7584981
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          ]
        },
        "related_pin": "CLK",
        "rise_constraint vio_10_10_1": {
          "index_1": [
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            0.1041667,
            0.2083333,
            0.4166667,
            0.8333333,
            1.6666667,
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          "index_2": [
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            0.4166667,
            0.8333333,
            1.6666667,
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          "values": [
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              -0.0266947,
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          ]
        },
        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "hold_rising",
        "violation_delay_degrade_pct": 10
      }
    ]
  },
  "pin Q": {
    "direction": "output",
    "function": "IQ",
    "internal_power": {
      "fall_power pwr_template13x21": {
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        "index_2": [
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        "values": [
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        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "setup_rising",
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        "fall_constraint vio_10_10_1": {
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    ]
  },
  "test_cell": {
    "ff IQ,IQ_N": {
      "clocked_on": "CLK",
      "next_state": "D"
    },
    "pin CLK": {
      "direction": "input"
    },
    "pin D": {
      "direction": "input"
    },
    "pin Q": {
      "direction": "output",
      "function": "IQ",
      "signal_type": "test_scan_out"
    },
    "pin SCD": {
      "direction": "input",
      "signal_type": "test_scan_in"
    },
    "pin SCE": {
      "direction": "input",
      "signal_type": "test_scan_enable"
    }
  }
}