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  "area": 12.7872,
  "cell_footprint": "o21ba",
  "cell_leakage_power": 0.0,
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    "pg_type": "primary_ground",
    "voltage_name": "VGND"
  },
  "pg_pin VNB": {
    "pg_type": "primary_ground",
    "voltage_name": "VNB"
  },
  "pg_pin VPB": {
    "pg_type": "primary_power",
    "voltage_name": "VPB"
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  "pg_pin VPWR": {
    "pg_type": "primary_power",
    "voltage_name": "VPWR"
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    "capacitance": 0.00258,
    "clock": "false",
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      "fall_power hidden_pwr_template13": {
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      "rise_power hidden_pwr_template13": {
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    "max_transition": 1.0,
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  "pin A2": {
    "capacitance": 0.003,
    "clock": "false",
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      "fall_power hidden_pwr_template13": {
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      "rise_power hidden_pwr_template13": {
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    "max_transition": 1.0,
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    "related_power_pin": "VPWR"
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    "clock": "false",
    "direction": "input",
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      "fall_power hidden_pwr_template13": {
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      "rise_power hidden_pwr_template13": {
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    },
    "max_transition": 1.0,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR"
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    "direction": "output",
    "function": "(A1&!B1_N) | (A2&!B1_N)",
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        "related_pin": "A1",
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        "when": "(!A2&!B1_N)"
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      {
        "fall_power pwr_template13x6": {
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        "rise_power pwr_template13x6": {
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              0.00791,
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      {
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        "related_pin": "B1_N",
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        "when": "(A1) | (A2)"
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    ],
    "max_capacitance": 0.07038,
    "power_down_function": "(!VPWR + VGND)",
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "timing": [
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}