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  "area": 14.3856,
  "cell_footprint": "nand4bb",
  "cell_leakage_power": 0.0,
  "pg_pin VGND": {
    "pg_type": "primary_ground",
    "voltage_name": "VGND"
  },
  "pg_pin VNB": {
    "pg_type": "primary_ground",
    "voltage_name": "VNB"
  },
  "pg_pin VPB": {
    "pg_type": "primary_power",
    "voltage_name": "VPB"
  },
  "pg_pin VPWR": {
    "pg_type": "primary_power",
    "voltage_name": "VPWR"
  },
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    "capacitance": 0.00222,
    "clock": "false",
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      "fall_power hidden_pwr_template13": {
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      "rise_power hidden_pwr_template13": {
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    "max_transition": 1.0,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR"
  },
  "pin B_N": {
    "capacitance": 0.0023,
    "clock": "false",
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      "fall_power hidden_pwr_template13": {
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        "values": [
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      "rise_power hidden_pwr_template13": {
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    "max_transition": 1.0,
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    "related_power_pin": "VPWR"
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    "capacitance": 0.00293,
    "clock": "false",
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      "fall_power hidden_pwr_template13": {
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        "values": [
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      "rise_power hidden_pwr_template13": {
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    "max_transition": 1.0,
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    "related_power_pin": "VPWR"
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    "capacitance": 0.00297,
    "clock": "false",
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    "internal_power": {
      "fall_power hidden_pwr_template13": {
        "index_1": [
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        "values": [
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      "rise_power hidden_pwr_template13": {
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        "values": [
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    "max_transition": 1.0,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR"
  },
  "pin Y": {
    "direction": "output",
    "function": "(A_N) | (B_N) | (!C) | (!D)",
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        "fall_power pwr_template13x5": {
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      {
        "fall_power pwr_template13x5": {
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