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  "area": 7.992,
  "cell_footprint": "nand2b",
  "cell_leakage_power": 0.0,
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    "pg_type": "primary_ground",
    "voltage_name": "VGND"
  },
  "pg_pin VNB": {
    "pg_type": "primary_ground",
    "voltage_name": "VNB"
  },
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    "pg_type": "primary_power",
    "voltage_name": "VPB"
  },
  "pg_pin VPWR": {
    "pg_type": "primary_power",
    "voltage_name": "VPWR"
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    "capacitance": 0.00214,
    "clock": "false",
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      "rise_power hidden_pwr_template13": {
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    "max_transition": 1.0,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR"
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    "capacitance": 0.00285,
    "clock": "false",
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    "internal_power": {
      "fall_power hidden_pwr_template13": {
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      "rise_power hidden_pwr_template13": {
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    "function": "(A_N) | (!B)",
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    "max_capacitance": 0.07135,
    "power_down_function": "(!VPWR + VGND)",
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "timing": [
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