{
  "area": 23.976,
  "cell_footprint": "dlxtn",
  "cell_leakage_power": 244.6314,
  "driver_waveform_fall": "ramp",
  "driver_waveform_rise": "ramp",
  "latch IQ,IQ_N": {
    "data_in": "D",
    "enable": "!GATE_N"
  },
  "leakage_power": [
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      "value": 242.2494561,
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    },
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      "value": 246.6008198,
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    },
    {
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    {
      "value": 253.3762995,
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  "pg_pin VGND": {
    "pg_type": "primary_ground",
    "voltage_name": "VGND"
  },
  "pg_pin VNB": {
    "pg_type": "primary_ground",
    "voltage_name": "VNB"
  },
  "pg_pin VPB": {
    "pg_type": "primary_power",
    "voltage_name": "VPB"
  },
  "pg_pin VPWR": {
    "pg_type": "primary_power",
    "voltage_name": "VPWR"
  },
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    "clock": "false",
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    "fall_capacitance": 0.002296,
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    "max_transition": 1.5,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.002407,
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        "sim_opt": "runlvl=5 accurate=1",
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      {
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        "sim_opt": "runlvl=5 accurate=1",
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        "violation_delay_degrade_pct": 10
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    ]
  },
  "pin GATE_N": {
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    "clock": "true",
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    "fall_capacitance": 0.002478,
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      "rise_power hidden_pwr_template13": {
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        "values": [
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    "max_transition": 1.5,
    "min_pulse_width_low": 0.112684,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.002569
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  "pin Q": {
    "direction": "output",
    "function": "IQ",
    "internal_power": [
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