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| "cell_footprint": "dlrtp", |
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| "driver_waveform_rise": "ramp", |
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| "clear": "!RESET_B", |
| "data_in": "D", |
| "enable": "GATE" |
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| { |
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| { |
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| { |
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| { |
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| { |
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| { |
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| ], |
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| "voltage_name": "VGND" |
| }, |
| "pg_pin VNB": { |
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| "voltage_name": "VNB" |
| }, |
| "pg_pin VPB": { |
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| "voltage_name": "VPB" |
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| "pg_pin VPWR": { |
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| "voltage_name": "VPWR" |
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| }, |
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| "clock": "true", |
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| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
| "rise_capacitance": 0.002505 |
| }, |
| "pin Q": { |
| "direction": "output", |
| "function": "IQ", |
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| { |
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