{
  "area": 27.1728,
  "cell_footprint": "dfxtp",
  "cell_leakage_power": 147.5885,
  "driver_waveform_fall": "ramp",
  "driver_waveform_rise": "ramp",
  "ff IQ,IQ_N": {
    "clocked_on": "CLK",
    "next_state": "D"
  },
  "leakage_power": [
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      "value": 185.4978535,
      "when": "D&CLK"
    },
    {
      "value": 138.5436548,
      "when": "!D&!CLK"
    },
    {
      "value": 141.6557467,
      "when": "!D&CLK"
    },
    {
      "value": 124.6567507,
      "when": "D&!CLK"
    }
  ],
  "pg_pin VGND": {
    "pg_type": "primary_ground",
    "voltage_name": "VGND"
  },
  "pg_pin VNB": {
    "pg_type": "primary_ground",
    "voltage_name": "VNB"
  },
  "pg_pin VPB": {
    "pg_type": "primary_power",
    "voltage_name": "VPB"
  },
  "pg_pin VPWR": {
    "pg_type": "primary_power",
    "voltage_name": "VPWR"
  },
  "pin CLK": {
    "capacitance": 0.002704,
    "clock": "true",
    "direction": "input",
    "fall_capacitance": 0.002588,
    "internal_power": {
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          0.02602,
          0.03903,
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          0.13172,
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        "values": [
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      "rise_power hidden_pwr_template13": {
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        "values": [
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    "max_transition": 1.5,
    "min_pulse_width_high": 0.207156,
    "min_pulse_width_low": 0.470799,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.002821
  },
  "pin D": {
    "capacitance": 0.001688,
    "clock": "false",
    "direction": "input",
    "fall_capacitance": 0.001757,
    "internal_power": {
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        "values": [
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      "rise_power hidden_pwr_template13": {
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        "values": [
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    },
    "max_transition": 1.5,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.001618,
    "timing": [
      {
        "fall_constraint vio_10_10_1": {
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              0.3218242,
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        "related_pin": "CLK",
        "rise_constraint vio_10_10_1": {
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          "values": [
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        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "setup_rising",
        "violation_delay_degrade_pct": 10
      },
      {
        "fall_constraint vio_10_10_1": {
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          "values": [
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          ]
        },
        "related_pin": "CLK",
        "rise_constraint vio_10_10_1": {
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            0.125,
            0.25,
            0.5,
            0.75,
            1.0,
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            0.0625,
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            0.25,
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            0.75,
            1.0,
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          "values": [
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          ]
        },
        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "hold_rising",
        "violation_delay_degrade_pct": 10
      }
    ]
  },
  "pin Q": {
    "direction": "output",
    "function": "IQ",
    "internal_power": {
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        "index_2": [
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          0.03082,
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        "values": [
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        ]
      },
      "related_pin": "CLK",
      "rise_power pwr_template13x6": {
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        "index_2": [
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        "values": [
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