{
  "area": 36.7632,
  "cell_footprint": "dfrtp",
  "cell_leakage_power": 12.17183,
  "driver_waveform_fall": "ramp",
  "driver_waveform_rise": "ramp",
  "ff IQ,IQ_N": {
    "clear": "!RESET_B",
    "clocked_on": "CLK",
    "next_state": "D"
  },
  "leakage_power": [
    {
      "value": 17.811324,
      "when": "D&RESET_B&CLK"
    },
    {
      "value": 10.6344977,
      "when": "!D&RESET_B&!CLK"
    },
    {
      "value": 9.1607344,
      "when": "!D&!RESET_B&CLK"
    },
    {
      "value": 14.0443248,
      "when": "!D&RESET_B&CLK"
    },
    {
      "value": 16.3489968,
      "when": "D&RESET_B&!CLK"
    },
    {
      "value": 9.420563,
      "when": "D&!RESET_B&CLK"
    },
    {
      "value": 9.8471791,
      "when": "!D&!RESET_B&!CLK"
    },
    {
      "value": 10.1070334,
      "when": "D&!RESET_B&!CLK"
    }
  ],
  "pg_pin VGND": {
    "pg_type": "primary_ground",
    "voltage_name": "VGND"
  },
  "pg_pin VNB": {
    "pg_type": "primary_ground",
    "voltage_name": "VNB"
  },
  "pg_pin VPB": {
    "pg_type": "primary_power",
    "voltage_name": "VPB"
  },
  "pg_pin VPWR": {
    "pg_type": "primary_power",
    "voltage_name": "VPWR"
  },
  "pin CLK": {
    "capacitance": 0.002528,
    "clock": "true",
    "direction": "input",
    "fall_capacitance": 0.002422,
    "internal_power": {
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          0.0867333,
          0.1301,
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          0.9878,
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        "values": [
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      "rise_power hidden_pwr_template13": {
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    "max_transition": 5.0,
    "min_pulse_width_high": 0.341175,
    "min_pulse_width_low": 0.827815,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.002635
  },
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    "capacitance": 0.001642,
    "clock": "false",
    "direction": "input",
    "fall_capacitance": 0.001597,
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        "values": [
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      "rise_power hidden_pwr_template13": {
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    },
    "max_transition": 5.0,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.001686,
    "timing": [
      {
        "clk_width": 6.8e-08,
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              1.3837003,
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        "related_pin": "CLK",
        "rise_constraint vio_10_10_1": {
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        },
        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "setup_rising",
        "violation_delay_degrade_pct": 10
      },
      {
        "clk_width": 6.8e-08,
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          ]
        },
        "related_pin": "CLK",
        "rise_constraint vio_10_10_1": {
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            0.4166667,
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          "values": [
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        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "hold_rising",
        "violation_delay_degrade_pct": 10
      }
    ]
  },
  "pin Q": {
    "direction": "output",
    "function": "IQ",
    "internal_power": [
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}