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  "cell_footprint": "clkdlyinv",
  "cell_leakage_power": 0.0,
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    "voltage_name": "VGND"
  },
  "pg_pin VNB": {
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    "voltage_name": "VNB"
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  "pg_pin VPB": {
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    "voltage_name": "VPB"
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  "pg_pin VPWR": {
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    "voltage_name": "VPWR"
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    "clock": "false",
    "direction": "input",
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    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR"
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    "function": "(!A)",
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    "max_capacitance": 0.06812,
    "power_down_function": "(!VPWR + VGND)",
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
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      "timing_sense": "negative_unate"
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  }
}