{
  "area": 19.1808,
  "cell_footprint": "a221oi",
  "cell_leakage_power": 0.0,
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    "pg_type": "primary_ground",
    "voltage_name": "VGND"
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  "pg_pin VNB": {
    "pg_type": "primary_ground",
    "voltage_name": "VNB"
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    "pg_type": "primary_power",
    "voltage_name": "VPB"
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  "pg_pin VPWR": {
    "pg_type": "primary_power",
    "voltage_name": "VPWR"
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    "capacitance": 0.00625,
    "clock": "false",
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      "fall_power hidden_pwr_template13": {
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      "rise_power hidden_pwr_template13": {
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    "max_transition": 1.0,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR"
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  "pin A2": {
    "capacitance": 0.00559,
    "clock": "false",
    "direction": "input",
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      "fall_power hidden_pwr_template13": {
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      "rise_power hidden_pwr_template13": {
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    "max_transition": 1.0,
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    "related_power_pin": "VPWR"
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    "capacitance": 0.00629,
    "clock": "false",
    "direction": "input",
    "internal_power": {
      "fall_power hidden_pwr_template13": {
        "index_1": [
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        "values": [
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      "rise_power hidden_pwr_template13": {
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        "values": [
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    "max_transition": 1.0,
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    "capacitance": 0.00557,
    "clock": "false",
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      "fall_power hidden_pwr_template13": {
        "index_1": [
          0.01,
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        "values": [
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      "rise_power hidden_pwr_template13": {
        "index_1": [
          0.01,
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    "max_transition": 1.0,
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    "related_power_pin": "VPWR"
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    "capacitance": 0.00578,
    "clock": "false",
    "direction": "input",
    "internal_power": {
      "fall_power hidden_pwr_template13": {
        "index_1": [
          0.01,
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          0.13172,
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        "values": [
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      "rise_power hidden_pwr_template13": {
        "index_1": [
          0.01,
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        "values": [
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    "max_transition": 1.0,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR"
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    "function": "(!A1&!B1&!C1) | (!A1&!B2&!C1) | (!A2&!B1&!C1) | (!A2&!B2&!C1)",
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        "fall_power pwr_template13x6": {
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