| { |
| "area": 36.7632, |
| "cell_footprint": "sky130_fd_sc_ls__sdfxtp", |
| "cell_leakage_power": 11.48804, |
| "driver_waveform_fall": "ramp", |
| "driver_waveform_rise": "ramp", |
| "ff,IQ,IQ_N": { |
| "clocked_on": "CLK", |
| "next_state": "(D&!SCE) | (SCD&SCE)" |
| }, |
| "leakage_power": [ |
| { |
| "value": 13.8385694, |
| "when": "D&!SCD&!SCE&CLK" |
| }, |
| { |
| "value": 11.7102319, |
| "when": "!D&!SCD&SCE&CLK" |
| }, |
| { |
| "value": 11.2333636, |
| "when": "!D&SCD&!SCE&CLK" |
| }, |
| { |
| "value": 11.3836549, |
| "when": "!D&!SCD&!SCE&!CLK" |
| }, |
| { |
| "value": 10.5431788, |
| "when": "!D&!SCD&!SCE&CLK" |
| }, |
| { |
| "value": 11.967229, |
| "when": "D&!SCD&SCE&CLK" |
| }, |
| { |
| "value": 8.8867642, |
| "when": "D&SCD&!SCE&!CLK" |
| }, |
| { |
| "value": 10.3853219, |
| "when": "!D&SCD&SCE&!CLK" |
| }, |
| { |
| "value": 9.8578896, |
| "when": "D&SCD&SCE&!CLK" |
| }, |
| { |
| "value": 8.501682, |
| "when": "D&SCD&!SCE&CLK" |
| }, |
| { |
| "value": 9.5809343, |
| "when": "D&!SCD&!SCE&!CLK" |
| }, |
| { |
| "value": 14.6430263, |
| "when": "!D&SCD&SCE&CLK" |
| }, |
| { |
| "value": 12.4148887, |
| "when": "!D&!SCD&SCE&!CLK" |
| }, |
| { |
| "value": 14.1156393, |
| "when": "D&SCD&SCE&CLK" |
| }, |
| { |
| "value": 12.8080622, |
| "when": "D&!SCD&SCE&!CLK" |
| }, |
| { |
| "value": 11.9381367, |
| "when": "!D&SCD&!SCE&!CLK" |
| } |
| ], |
| "pg_pin,VGND": { |
| "pg_type": "primary_ground", |
| "related_bias_pin": "VPB", |
| "voltage_name": "VGND" |
| }, |
| "pg_pin,VNB": { |
| "pg_type": "nwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VNB" |
| }, |
| "pg_pin,VPB": { |
| "pg_type": "pwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VPB" |
| }, |
| "pg_pin,VPWR": { |
| "pg_type": "primary_power", |
| "related_bias_pin": "VNB", |
| "voltage_name": "VPWR" |
| }, |
| "pin,CLK": { |
| "capacitance": 0.002673, |
| "clock": "true", |
| "direction": "input", |
| "fall_capacitance": 0.002566, |
| "internal_power": { |
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| 1.48163, |
| 2.22233, |
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| ], |
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| 0.0159912, |
| 0.0159858, |
| 0.01599, |
| 0.0160086 |
| ] |
| }, |
| "rise_power,hidden_pwr_template13": { |
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| 0.0114847, |
| 0.0114675 |
| ] |
| } |
| }, |
| "max_transition": 5.0, |
| "min_pulse_width_high": 0.346667, |
| "min_pulse_width_low": 0.895922, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
| "rise_capacitance": 0.00278 |
| }, |
| "pin,D": { |
| "capacitance": 0.001785, |
| "clock": "false", |
| "direction": "input", |
| "fall_capacitance": 0.001698, |
| "internal_power": { |
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| 0.0057418, |
| 0.005729, |
| 0.0057213, |
| 0.0057211 |
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| 0.0008352, |
| 0.0008016, |
| 0.0007634 |
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| } |
| }, |
| "max_transition": 5.0, |
| "nextstate_type": "data", |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
| "rise_capacitance": 0.001873, |
| "timing": [ |
| { |
| "clk_width": 6.8e-08, |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| 0.890265, |
| 1.2578322, |
| 1.5961027, |
| 1.9124003 |
| ] |
| ] |
| }, |
| "related_pin": "CLK", |
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| 0.0333333, |
| 0.1041667, |
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| [ |
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| 1.8949038, |
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| [ |
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| [ |
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| 1.7561505, |
| 1.9699092 |
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| [ |
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| [ |
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| [ |
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| ] |
| }, |
| "sim_opt": "runlvl=5 accurate=1", |
| "timing_type": "setup_rising", |
| "violation_delay_degrade_pct": 10 |
| }, |
| { |
| "clk_width": 6.8e-08, |
| "fall_constraint,vio_10_10_1": { |
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| 0.0333333, |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| ] |
| }, |
| "related_pin": "CLK", |
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| }, |
| "test_cell": { |
| "ff,IQ,IQ_N": { |
| "clocked_on": "CLK", |
| "next_state": "D" |
| }, |
| "pin,CLK": { |
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| "pin,D": { |
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| "pin,SCD": { |
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| "pin,SCE": { |
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| "signal_type": "test_scan_enable" |
| } |
| } |
| } |
