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  "cell_footprint": "sky130_fd_sc_ls__dlclkp",
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  "clock_gating_integrated_cell": "latch_posedge",
  "driver_waveform_fall": "ramp",
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            0.1065799,
            0.1475582,
            0.2107004,
            0.3071673,
            0.4533081,
            0.673562,
            1.0037885,
            1.4991832
          ],
          [
            0.029915,
            0.0674091,
            0.0838009,
            0.109608,
            0.1496873,
            0.2123265,
            0.3080103,
            0.4538026,
            0.6730981,
            1.0044224,
            1.4986481
          ],
          [
            0.0346449,
            0.0740093,
            0.0901898,
            0.1145361,
            0.1533817,
            0.2145424,
            0.3094515,
            0.4551347,
            0.6748145,
            1.0045857,
            1.4990571
          ],
          [
            0.0410981,
            0.0833312,
            0.098788,
            0.1222783,
            0.1592116,
            0.2188622,
            0.3118411,
            0.457949,
            0.6758588,
            1.0068474,
            1.4970956
          ]
        ]
      },
      "timing_sense": "positive_unate"
    }
  },
  "pin,M0": {
    "direction": "internal",
    "internal_node": "M0",
    "related_ground_pin": "VNB",
    "related_power_pin": "VPWR"
  },
  "statetable,CLK GATE,M0": {
    "table": [
      "L L : - : L",
      "L H : - : H",
      "H - : - : N"
    ]
  }
}