| { |
| "area": 25.5744, |
| "cell_footprint": "sky130_fd_sc_ls__dlclkp", |
| "cell_leakage_power": 7.167289, |
| "clock_gating_integrated_cell": "latch_posedge", |
| "driver_waveform_fall": "ramp", |
| "driver_waveform_rise": "ramp", |
| "leakage_power": [ |
| { |
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| "when": "!GATE&CLK" |
| }, |
| { |
| "value": 7.3928059, |
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| }, |
| { |
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| }, |
| { |
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| } |
| ], |
| "pg_pin,VGND": { |
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| "related_bias_pin": "VPB", |
| "voltage_name": "VGND" |
| }, |
| "pg_pin,VNB": { |
| "pg_type": "nwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VNB" |
| }, |
| "pg_pin,VPB": { |
| "pg_type": "pwell", |
| "physical_connection": "device_layer", |
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| }, |
| "pg_pin,VPWR": { |
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| "related_bias_pin": "VNB", |
| "voltage_name": "VPWR" |
| }, |
| "pin,CLK": { |
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| "clock": "true", |
| "clock_gate_clock_pin": "true", |
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| }, |
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| }, |
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| "clock_gate_enable_pin": "true", |
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| }, |
| { |
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| }, |
| "sim_opt": "runlvl=5 accurate=1", |
| "timing_type": "hold_rising", |
| "violation_delay_degrade_pct": 10 |
| } |
| ] |
| }, |
| "pin,GCLK": { |
| "clock_gate_out_pin": "true", |
| "direction": "output", |
| "internal_power": { |
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| 0.7084622, |
| 1.0478606, |
| 1.5577456 |
| ], |
| [ |
| 0.0414633, |
| 0.1273038, |
| 0.1702963, |
| 0.2350963, |
| 0.3343783, |
| 0.4837307, |
| 0.7102151, |
| 1.0472505, |
| 1.5575758 |
| ], |
| [ |
| 0.0414783, |
| 0.1276994, |
| 0.1698023, |
| 0.235314, |
| 0.3335255, |
| 0.4837849, |
| 0.709271, |
| 1.0476523, |
| 1.5577868 |
| ], |
| [ |
| 0.0424841, |
| 0.1282348, |
| 0.1703375, |
| 0.235431, |
| 0.3338199, |
| 0.4838334, |
| 0.7092312, |
| 1.0477139, |
| 1.555835 |
| ], |
| [ |
| 0.0460489, |
| 0.130466, |
| 0.1722699, |
| 0.2359509, |
| 0.3348374, |
| 0.4829733, |
| 0.7092678, |
| 1.0494194, |
| 1.5567455 |
| ], |
| [ |
| 0.0502605, |
| 0.135034, |
| 0.1758475, |
| 0.2388794, |
| 0.3361226, |
| 0.4856202, |
| 0.7114732, |
| 1.0511666, |
| 1.5575906 |
| ], |
| [ |
| 0.057161, |
| 0.1408455, |
| 0.1812037, |
| 0.2434435, |
| 0.3394411, |
| 0.4859888, |
| 0.7104872, |
| 1.0517469, |
| 1.5637325 |
| ], |
| [ |
| 0.06804, |
| 0.1500457, |
| 0.1894443, |
| 0.2498032, |
| 0.3445763, |
| 0.489863, |
| 0.7124397, |
| 1.048825, |
| 1.5589788 |
| ], |
| [ |
| 0.08611, |
| 0.1656474, |
| 0.2020054, |
| 0.260708, |
| 0.3527971, |
| 0.494766, |
| 0.7163827, |
| 1.0551172, |
| 1.5624946 |
| ], |
| [ |
| 0.110192, |
| 0.1908391, |
| 0.2260011, |
| 0.2799848, |
| 0.3660121, |
| 0.5041603, |
| 0.7221481, |
| 1.0553642, |
| 1.5612533 |
| ] |
| ] |
| }, |
| "timing_sense": "positive_unate" |
| } |
| }, |
| "pin,M0": { |
| "direction": "internal", |
| "internal_node": "M0", |
| "related_ground_pin": "VNB", |
| "related_power_pin": "VPWR" |
| }, |
| "statetable,CLK GATE,M0": { |
| "table": [ |
| "L L : - : L", |
| "L H : - : H", |
| "H - : - : N" |
| ] |
| } |
| } |
