{ | |
"area": 36.7632, | |
"cell_footprint": "sky130_fd_sc_ls__sdfxtp", | |
"cell_leakage_power": 0.0006252758, | |
"driver_waveform_fall": "ramp", | |
"driver_waveform_rise": "ramp", | |
"ff,IQ,IQ_N": { | |
"clocked_on": "CLK", | |
"next_state": "(D&!SCE) | (SCD&SCE)" | |
}, | |
"leakage_power": [ | |
{ | |
"value": 0.0006687, | |
"when": "D&SCD&!SCE&!CLK" | |
}, | |
{ | |
"value": 0.0004965, | |
"when": "!D&SCD&SCE&!CLK" | |
}, | |
{ | |
"value": 0.0006365, | |
"when": "D&SCD&SCE&!CLK" | |
}, | |
{ | |
"value": 0.0007916, | |
"when": "D&!SCD&!SCE&CLK" | |
}, | |
{ | |
"value": 0.0006119, | |
"when": "!D&!SCD&SCE&CLK" | |
}, | |
{ | |
"value": 0.000579, | |
"when": "!D&SCD&!SCE&CLK" | |
}, | |
{ | |
"value": 0.0005736, | |
"when": "!D&!SCD&!SCE&!CLK" | |
}, | |
{ | |
"value": 0.0004277, | |
"when": "!D&!SCD&!SCE&CLK" | |
}, | |
{ | |
"value": 0.0005566, | |
"when": "D&!SCD&SCE&CLK" | |
}, | |
{ | |
"value": 0.0006183, | |
"when": "D&SCD&!SCE&CLK" | |
}, | |
{ | |
"value": 0.0006688, | |
"when": "D&!SCD&!SCE&!CLK" | |
}, | |
{ | |
"value": 0.0006192, | |
"when": "!D&SCD&SCE&CLK" | |
}, | |
{ | |
"value": 0.0006635, | |
"when": "!D&!SCD&SCE&!CLK" | |
}, | |
{ | |
"value": 0.0007593, | |
"when": "D&SCD&SCE&CLK" | |
}, | |
{ | |
"value": 0.0007025, | |
"when": "D&!SCD&SCE&!CLK" | |
}, | |
{ | |
"value": 0.0006307, | |
"when": "!D&SCD&!SCE&!CLK" | |
} | |
], | |
"pg_pin,VGND": { | |
"pg_type": "primary_ground", | |
"related_bias_pin": "VPB", | |
"voltage_name": "VGND" | |
}, | |
"pg_pin,VNB": { | |
"pg_type": "nwell", | |
"physical_connection": "device_layer", | |
"voltage_name": "VNB" | |
}, | |
"pg_pin,VPB": { | |
"pg_type": "pwell", | |
"physical_connection": "device_layer", | |
"voltage_name": "VPB" | |
}, | |
"pg_pin,VPWR": { | |
"pg_type": "primary_power", | |
"related_bias_pin": "VNB", | |
"voltage_name": "VPWR" | |
}, | |
"pin,CLK": { | |
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"clock": "true", | |
"direction": "input", | |
"fall_capacitance": 0.002299, | |
"internal_power": { | |
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"min_pulse_width_low": 1.224496, | |
"related_ground_pin": "VGND", | |
"related_power_pin": "VPWR", | |
"rise_capacitance": 0.00259 | |
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"pin,D": { | |
"capacitance": 0.001668, | |
"clock": "false", | |
"direction": "input", | |
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"max_transition": 5.0, | |
"nextstate_type": "data", | |
"related_ground_pin": "VGND", | |
"related_power_pin": "VPWR", | |
"rise_capacitance": 0.001757, | |
"timing": [ | |
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"related_pin": "CLK", | |
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}, | |
"sim_opt": "runlvl=5 accurate=1", | |
"timing_type": "setup_rising", | |
"violation_delay_degrade_pct": 10 | |
}, | |
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