{ | |
"area": 41.5584, | |
"cell_footprint": "sky130_fd_sc_ls__sdfxbp", | |
"cell_leakage_power": 22.50491, | |
"driver_waveform_fall": "ramp", | |
"driver_waveform_rise": "ramp", | |
"ff,IQ,IQ_N": { | |
"clocked_on": "CLK", | |
"next_state": "(D&!SCE) | (SCD&SCE)" | |
}, | |
"leakage_power": [ | |
{ | |
"value": 25.8039172, | |
"when": "D&!SCD&!SCE&CLK" | |
}, | |
{ | |
"value": 22.6184849, | |
"when": "!D&!SCD&SCE&CLK" | |
}, | |
{ | |
"value": 21.7282317, | |
"when": "!D&SCD&!SCE&CLK" | |
}, | |
{ | |
"value": 22.2135572, | |
"when": "!D&!SCD&!SCE&!CLK" | |
}, | |
{ | |
"value": 21.0741202, | |
"when": "!D&!SCD&!SCE&CLK" | |
}, | |
{ | |
"value": 23.3048176, | |
"when": "D&!SCD&SCE&CLK" | |
}, | |
{ | |
"value": 18.9034797, | |
"when": "D&SCD&!SCE&!CLK" | |
}, | |
{ | |
"value": 21.2444657, | |
"when": "!D&SCD&SCE&!CLK" | |
}, | |
{ | |
"value": 20.4227355, | |
"when": "D&SCD&SCE&!CLK" | |
}, | |
{ | |
"value": 18.179291, | |
"when": "D&SCD&!SCE&CLK" | |
}, | |
{ | |
"value": 20.0164845, | |
"when": "D&!SCD&!SCE&!CLK" | |
}, | |
{ | |
"value": 27.0320424, | |
"when": "!D&SCD&SCE&CLK" | |
}, | |
{ | |
"value": 23.8859066, | |
"when": "!D&!SCD&SCE&!CLK" | |
}, | |
{ | |
"value": 26.2103814, | |
"when": "D&SCD&SCE&CLK" | |
}, | |
{ | |
"value": 24.444887, | |
"when": "D&!SCD&SCE&!CLK" | |
}, | |
{ | |
"value": 22.9958275, | |
"when": "!D&SCD&!SCE&!CLK" | |
} | |
], | |
"pg_pin,VGND": { | |
"pg_type": "primary_ground", | |
"related_bias_pin": "VPB", | |
"voltage_name": "VGND" | |
}, | |
"pg_pin,VNB": { | |
"pg_type": "nwell", | |
"physical_connection": "device_layer", | |
"voltage_name": "VNB" | |
}, | |
"pg_pin,VPB": { | |
"pg_type": "pwell", | |
"physical_connection": "device_layer", | |
"voltage_name": "VPB" | |
}, | |
"pg_pin,VPWR": { | |
"pg_type": "primary_power", | |
"related_bias_pin": "VNB", | |
"voltage_name": "VPWR" | |
}, | |
"pin,CLK": { | |
"capacitance": 0.002706, | |
"clock": "true", | |
"direction": "input", | |
"fall_capacitance": 0.002571, | |
"internal_power": { | |
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0.02602, | |
0.03903, | |
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0.08782, | |
0.13172, | |
0.19757, | |
0.29634, | |
0.44449, | |
0.6667, | |
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1.5 | |
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"rise_power,hidden_pwr_template13": { | |
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"values": [ | |
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0.0154135, | |
0.0153326, | |
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"min_pulse_width_low": 0.565271, | |
"related_ground_pin": "VGND", | |
"related_power_pin": "VPWR", | |
"rise_capacitance": 0.002841 | |
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"pin,D": { | |
"capacitance": 0.001773, | |
"clock": "false", | |
"direction": "input", | |
"fall_capacitance": 0.001675, | |
"internal_power": { | |
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0.0074481, | |
0.0074453, | |
0.0074475 | |
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0.44449, | |
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"values": [ | |
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0.0014306, | |
0.0013725, | |
0.0012918 | |
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"max_transition": 1.5, | |
"nextstate_type": "data", | |
"related_ground_pin": "VGND", | |
"related_power_pin": "VPWR", | |
"rise_capacitance": 0.001871, | |
"timing": [ | |
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[ | |
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[ | |
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0.7620912, | |
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"related_pin": "CLK", | |
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[ | |
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[ | |
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[ | |
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[ | |
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[ | |
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[ | |
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0.4935365, | |
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] | |
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}, | |
"sim_opt": "runlvl=5 accurate=1", | |
"timing_type": "setup_rising", | |
"violation_delay_degrade_pct": 10 | |
}, | |
{ | |
"fall_constraint,vio_10_10_1": { | |
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[ | |
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[ | |
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[ | |
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[ | |
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[ | |
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0.75, | |
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1.5 | |
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[ | |
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[ | |
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[ | |
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[ | |
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[ | |
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}, | |
"sim_opt": "runlvl=5 accurate=1", | |
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