commit 86b4f7974db09d0e1808615b1466695a0143b249
author Tim 'mithro' Ansell <me@mith.ro> Wed Oct 28 20:07:45 2020 -0700
committer Tim 'mithro' Ansell <tansell@google.com> Wed Oct 28 20:07:45 2020 -0700
tree 0e8f18fa8d237d839fe591773142eb8c1d676ff2
parent 623269dc828fff55705725cb6256aec080ade465
parent bdf37537c854f82df3a2fa048c890f156837245e

verilog: Fixing power pins usage in non-powerpin mode.

Previously even when `USE_POWER_PIN` was not defined, the drive strength
wrappers where still defining the power pins as ports.

Fixes https://github.com/google/skywater-pdk/issues/181

Signed-off-by: Tim 'mithro' Ansell <tansell@google.com>

README.rst

diff --git a/README.rst b/README.rst
index dfab356..7481165 100644
--- a/README.rst
+++ b/README.rst
@@ -1,5 +1,5 @@
 :lib:`sky130_fd_sc_ls` - SKY130 Low Speed Digital Standard Cells (SkyWater Provided)
 ====================================================================================
 
-Initial release of version (0, 1, 0).
+Initial release of version (0, 1, 1).
 

cells/diode/sky130_fd_sc_ls__diode_2.lef

diff --git a/cells/diode/sky130_fd_sc_ls__diode_2.lef b/cells/diode/sky130_fd_sc_ls__diode_2.lef
index bd01920..3a6620e 100644
--- a/cells/diode/sky130_fd_sc_ls__diode_2.lef
+++ b/cells/diode/sky130_fd_sc_ls__diode_2.lef
@@ -27,6 +27,7 @@
   SITE unit ;
   PIN DIODE
     ANTENNADIFFAREA  0.641700 ;
+    ANTENNAGATEAREA  0.000000 ;
     DIRECTION INPUT ;
     PORT
       LAYER li1 ;