| { |
| "area": 28.7712, |
| "cell_footprint": "sky130_fd_sc_ls__dlclkp", |
| "cell_leakage_power": 12.56454, |
| "clock_gating_integrated_cell": "latch_posedge", |
| "driver_waveform_fall": "ramp", |
| "driver_waveform_rise": "ramp", |
| "leakage_power": [ |
| { |
| "value": 12.8562165, |
| "when": "!GATE&CLK" |
| }, |
| { |
| "value": 12.892718, |
| "when": "GATE&!CLK" |
| }, |
| { |
| "value": 10.0407442, |
| "when": "GATE&CLK" |
| }, |
| { |
| "value": 14.4684762, |
| "when": "!GATE&!CLK" |
| } |
| ], |
| "pg_pin,VGND": { |
| "pg_type": "primary_ground", |
| "related_bias_pin": "VPB", |
| "voltage_name": "VGND" |
| }, |
| "pg_pin,VNB": { |
| "pg_type": "nwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VNB" |
| }, |
| "pg_pin,VPB": { |
| "pg_type": "pwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VPB" |
| }, |
| "pg_pin,VPWR": { |
| "pg_type": "primary_power", |
| "related_bias_pin": "VNB", |
| "voltage_name": "VPWR" |
| }, |
| "pin,CLK": { |
| "capacitance": 0.004598, |
| "clock": "true", |
| "clock_gate_clock_pin": "true", |
| "direction": "input", |
| "fall_capacitance": 0.004426, |
| "internal_power": { |
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| } |
| }, |
| "max_transition": 1.5, |
| "min_pulse_width_low": 0.325067, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
| "rise_capacitance": 0.00477 |
| }, |
| "pin,GATE": { |
| "capacitance": 0.002383, |
| "clock": "false", |
| "clock_gate_enable_pin": "true", |
| "direction": "input", |
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| 0.014683, |
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| }, |
| "max_transition": 1.5, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
| "rise_capacitance": 0.002514, |
| "timing": [ |
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| 0.3279277 |
| ] |
| ] |
| }, |
| "related_pin": "CLK", |
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| }, |
| "sim_opt": "runlvl=5 accurate=1", |
| "timing_type": "setup_rising", |
| "violation_delay_degrade_pct": 10 |
| }, |
| { |
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| 0.0625, |
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| 0.75, |
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| ] |
| }, |
| "related_pin": "CLK", |
| "rise_constraint,vio_10_10_1": { |
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| 0.03125, |
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| 0.125, |
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| ] |
| }, |
| "sim_opt": "runlvl=5 accurate=1", |
| "timing_type": "hold_rising", |
| "violation_delay_degrade_pct": 10 |
| } |
| ] |
| }, |
| "pin,GCLK": { |
| "clock_gate_out_pin": "true", |
| "direction": "output", |
| "internal_power": { |
| "fall_power,pwr_template13x12": { |
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| 1.5 |
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| }, |
| "related_pin": "CLK", |
| "rise_transition,delay_template13x12": { |
| "index_1": [ |
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| ] |
| }, |
| "timing_sense": "positive_unate" |
| } |
| }, |
| "pin,M0": { |
| "direction": "internal", |
| "internal_node": "M0", |
| "related_ground_pin": "VNB", |
| "related_power_pin": "VPWR" |
| }, |
| "statetable,CLK GATE,M0": { |
| "table": [ |
| "L L : - : L", |
| "L H : - : H", |
| "H - : - : N" |
| ] |
| } |
| } |
