| { |
| "area": 55.944, |
| "cell_footprint": "sky130_fd_sc_ls__sedfxtp", |
| "cell_leakage_power": 0.001194549, |
| "driver_waveform_fall": "ramp", |
| "driver_waveform_rise": "ramp", |
| "ff,IQ,IQ_N": { |
| "clocked_on": "CLK", |
| "next_state": "(D&DE&!SCE) | (IQ&!DE&!SCE) | (SCD&SCE)" |
| }, |
| "leakage_power": [ |
| { |
| "value": 0.0007322, |
| "when": "!D&!SCE&!SCD&CLK" |
| }, |
| { |
| "value": 0.0009456, |
| "when": "D&!SCE&!SCD&CLK" |
| }, |
| { |
| "value": 0.0012913, |
| "when": "D&SCE&!SCD&CLK" |
| }, |
| { |
| "value": 0.0010555, |
| "when": "D&!SCE&SCD&CLK" |
| }, |
| { |
| "value": 0.0011622, |
| "when": "D&!SCE&!SCD&!CLK" |
| }, |
| { |
| "value": 0.0013262, |
| "when": "!D&SCE&!SCD&CLK" |
| }, |
| { |
| "value": 0.0012148, |
| "when": "!D&!SCE&SCD&CLK" |
| }, |
| { |
| "value": 0.0011608, |
| "when": "!D&!SCE&!SCD&!CLK" |
| }, |
| { |
| "value": 0.00145, |
| "when": "!D&SCE&SCD&CLK" |
| }, |
| { |
| "value": 0.0012152, |
| "when": "!D&SCE&!SCD&!CLK" |
| }, |
| { |
| "value": 0.0014722, |
| "when": "D&SCE&SCD&CLK" |
| }, |
| { |
| "value": 0.0012374, |
| "when": "D&SCE&!SCD&!CLK" |
| }, |
| { |
| "value": 0.0011618, |
| "when": "D&!SCE&SCD&!CLK" |
| }, |
| { |
| "value": 0.0011786, |
| "when": "!D&SCE&SCD&!CLK" |
| }, |
| { |
| "value": 0.0013165, |
| "when": "D&SCE&SCD&!CLK" |
| }, |
| { |
| "value": 0.0011924, |
| "when": "!D&!SCE&SCD&!CLK" |
| } |
| ], |
| "pg_pin,VGND": { |
| "pg_type": "primary_ground", |
| "related_bias_pin": "VPB", |
| "voltage_name": "VGND" |
| }, |
| "pg_pin,VNB": { |
| "pg_type": "nwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VNB" |
| }, |
| "pg_pin,VPB": { |
| "pg_type": "pwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VPB" |
| }, |
| "pg_pin,VPWR": { |
| "pg_type": "primary_power", |
| "related_bias_pin": "VNB", |
| "voltage_name": "VPWR" |
| }, |
| "pin,CLK": { |
| "capacitance": 0.002388, |
| "clock": "true", |
| "direction": "input", |
| "fall_capacitance": 0.002266, |
| "internal_power": { |
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| 0.0578333, |
| 0.0867333, |
| 0.1301, |
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| 0.292733, |
| 0.4390667, |
| 0.658567, |
| 0.9878, |
| 1.48163, |
| 2.22233, |
| 3.33333, |
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| ], |
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| 0.0168557, |
| 0.0169682, |
| 0.017137, |
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| 0.0171022, |
| 0.0170208, |
| 0.0168986, |
| 0.0168715, |
| 0.0168309, |
| 0.01677, |
| 0.0166786 |
| ] |
| }, |
| "rise_power,hidden_pwr_template13": { |
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| ], |
| "values": [ |
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| 0.0137476, |
| 0.0136861, |
| 0.0135937, |
| 0.0134552 |
| ] |
| } |
| }, |
| "max_transition": 5.0, |
| "min_pulse_width_high": 1.134409, |
| "min_pulse_width_low": 1.303597, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
| "rise_capacitance": 0.002511 |
| }, |
| "pin,D": { |
| "capacitance": 0.001733, |
| "clock": "false", |
| "direction": "input", |
| "fall_capacitance": 0.001635, |
| "internal_power": { |
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| ], |
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| 0.0095039, |
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| 0.0098488, |
| 0.0098401, |
| 0.0098271, |
| 0.0098076 |
| ] |
| }, |
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| 0.0076549, |
| 0.0076208, |
| 0.0075696, |
| 0.0074927 |
| ] |
| } |
| }, |
| "max_transition": 5.0, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
| "rise_capacitance": 0.001831, |
| "timing": [ |
| { |
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| ], |
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| [ |
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| 3.226284, |
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| [ |
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| [ |
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| 4.0240813, |
| 4.5124982, |
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| [ |
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| 3.3286871, |
| 3.818325, |
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| [ |
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| [ |
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| [ |
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| 3.3627312, |
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| [ |
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| [ |
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| 1.4052661, |
| 1.8924622, |
| 2.3796585, |
| 2.8680754, |
| 3.3503887 |
| ] |
| ] |
| }, |
| "related_pin": "CLK", |
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| 0.0333333, |
| 0.1041667, |
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| 0.4166667, |
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| 3.0066658 |
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| [ |
| 0.6872485, |
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| 2.2805103, |
| 2.6322083, |
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| [ |
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| 2.2257141, |
| 2.5786329, |
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| [ |
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| 2.141757, |
| 2.4910137, |
| 2.8268426 |
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| [ |
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| 2.364603, |
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| 1.8769999 |
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| ] |
| }, |
| "sim_opt": "runlvl=5 accurate=1", |
| "timing_type": "setup_rising", |
| "violation_delay_degrade_pct": 10 |
| }, |
| { |
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| 0.0333333, |
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| [ |
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| [ |
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| [ |
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| ] |
| ] |
| }, |
| "related_pin": "CLK", |
| "rise_constraint,vio_10_10_1": { |
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| 0.0333333, |
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| } |
| ] |
| }, |
| "test_cell": { |
| "ff,IQ,IQ_N": { |
| "clocked_on": "CLK", |
| "next_state": "(D&DE) | (IQ&!DE)" |
| }, |
| "pin,CLK": { |
| "direction": "input" |
| }, |
| "pin,D": { |
| "direction": "input" |
| }, |
| "pin,DE": { |
| "direction": "input" |
| }, |
| "pin,Q": { |
| "direction": "output", |
| "function": "IQ", |
| "signal_type": "test_scan_out" |
| }, |
| "pin,SCD": { |
| "direction": "input", |
| "signal_type": "test_scan_in" |
| }, |
| "pin,SCE": { |
| "direction": "input", |
| "signal_type": "test_scan_enable" |
| } |
| } |
| } |
