| { |
| "area": 25.5744, |
| "cell_footprint": "sky130_fd_sc_ls__dlclkp", |
| "cell_leakage_power": 0.0001459329, |
| "clock_gating_integrated_cell": "latch_posedge", |
| "driver_waveform_fall": "ramp", |
| "driver_waveform_rise": "ramp", |
| "leakage_power": [ |
| { |
| "value": 0.0001517, |
| "when": "!GATE&CLK" |
| }, |
| { |
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| "when": "GATE&!CLK" |
| }, |
| { |
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| "when": "GATE&CLK" |
| }, |
| { |
| "value": 0.0001414, |
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| } |
| ], |
| "pg_pin,VGND": { |
| "pg_type": "primary_ground", |
| "related_bias_pin": "VPB", |
| "voltage_name": "VGND" |
| }, |
| "pg_pin,VNB": { |
| "pg_type": "nwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VNB" |
| }, |
| "pg_pin,VPB": { |
| "pg_type": "pwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VPB" |
| }, |
| "pg_pin,VPWR": { |
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| "related_bias_pin": "VNB", |
| "voltage_name": "VPWR" |
| }, |
| "pin,CLK": { |
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| "clock": "true", |
| "clock_gate_clock_pin": "true", |
| "direction": "input", |
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| }, |
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| "related_power_pin": "VPWR", |
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| }, |
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| "clock": "false", |
| "clock_gate_enable_pin": "true", |
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| }, |
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| }, |
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| }, |
| "sim_opt": "runlvl=5 accurate=1", |
| "timing_type": "hold_rising", |
| "violation_delay_degrade_pct": 10 |
| } |
| ] |
| }, |
| "pin,GCLK": { |
| "clock_gate_out_pin": "true", |
| "direction": "output", |
| "internal_power": { |
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| [ |
| 0.0850357, |
| 0.3652467, |
| 0.5080701, |
| 0.722429, |
| 1.0397692, |
| 1.5226708, |
| 2.2388558, |
| 3.3194345, |
| 4.9363083 |
| ], |
| [ |
| 0.084111, |
| 0.3649394, |
| 0.5081707, |
| 0.7207518, |
| 1.0399054, |
| 1.5186651, |
| 2.239992, |
| 3.3234608, |
| 4.9492352 |
| ], |
| [ |
| 0.0848343, |
| 0.365475, |
| 0.5086176, |
| 0.7197672, |
| 1.0387677, |
| 1.5218953, |
| 2.2392785, |
| 3.317483, |
| 4.9368793 |
| ], |
| [ |
| 0.0841869, |
| 0.3656679, |
| 0.5063717, |
| 0.719924, |
| 1.0428337, |
| 1.5199197, |
| 2.2448772, |
| 3.318489, |
| 4.9422919 |
| ], |
| [ |
| 0.0851913, |
| 0.365053, |
| 0.5080137, |
| 0.72232, |
| 1.0394964, |
| 1.5196632, |
| 2.238703, |
| 3.3185283, |
| 4.9472573 |
| ], |
| [ |
| 0.0884624, |
| 0.3668081, |
| 0.5074675, |
| 0.719646, |
| 1.0387318, |
| 1.5203554, |
| 2.2447917, |
| 3.3233347, |
| 4.9360778 |
| ], |
| [ |
| 0.0934031, |
| 0.3687489, |
| 0.5105137, |
| 0.7247896, |
| 1.0404141, |
| 1.5237812, |
| 2.2387017, |
| 3.3199155, |
| 4.9391535 |
| ], |
| [ |
| 0.0991708, |
| 0.3729627, |
| 0.5124852, |
| 0.7239368, |
| 1.0453504, |
| 1.5216748, |
| 2.2459401, |
| 3.3213325, |
| 4.9378439 |
| ], |
| [ |
| 0.1074023, |
| 0.3779284, |
| 0.5172863, |
| 0.7268427, |
| 1.045666, |
| 1.5256754, |
| 2.2478299, |
| 3.3279659, |
| 4.9449165 |
| ] |
| ] |
| }, |
| "timing_sense": "positive_unate" |
| } |
| }, |
| "pin,M0": { |
| "direction": "internal", |
| "internal_node": "M0", |
| "related_ground_pin": "VNB", |
| "related_power_pin": "VPWR" |
| }, |
| "statetable,CLK GATE,M0": { |
| "table": [ |
| "L L : - : L", |
| "L H : - : H", |
| "H - : - : N" |
| ] |
| } |
| } |
