verilog: Fixing ordering of ports in primitives.

Verilog requires the first signal in a primitive's pin list must be the output.

Signed-off-by: Tim 'mithro' Ansell <tansell@google.com>

README.rst

diff --git a/README.rst b/README.rst
index dfab356..7481165 100644
--- a/README.rst
+++ b/README.rst
@@ -1,5 +1,5 @@
 :lib:`sky130_fd_sc_ls` - SKY130 Low Speed Digital Standard Cells (SkyWater Provided)
 ====================================================================================
 
-Initial release of version (0, 1, 0).
+Initial release of version (0, 1, 1).
 

cells/diode/sky130_fd_sc_ls__diode_2.lef

diff --git a/cells/diode/sky130_fd_sc_ls__diode_2.lef b/cells/diode/sky130_fd_sc_ls__diode_2.lef
index bd01920..3a6620e 100644
--- a/cells/diode/sky130_fd_sc_ls__diode_2.lef
+++ b/cells/diode/sky130_fd_sc_ls__diode_2.lef
@@ -27,6 +27,7 @@
   SITE unit ;
   PIN DIODE
     ANTENNADIFFAREA  0.641700 ;
+    ANTENNAGATEAREA  0.000000 ;
     DIRECTION INPUT ;
     PORT
       LAYER li1 ;