commit 26dc994264fd69e07b17c7fbd06a6db57c5e6ff2
author Tim 'mithro' Ansell <me@mith.ro> Fri Oct 02 10:01:02 2020 -0700
committer Tim 'mithro' Ansell <tansell@google.com> Fri Oct 02 10:01:02 2020 -0700
tree c051f1d9677403c7eabaccddd5d1f4cb22c2c75c
parent fd4c4436958103d29fe1d12a5001a2cebfbbc582
parent d8c2717829bd09cbf64eec3778dd90fc2a2fafcd

verilog: Fixing ordering of ports in primitives.

Verilog requires the first signal in a primitive's pin list must be the output.

Signed-off-by: Tim 'mithro' Ansell <tansell@google.com>

README.rst

diff --git a/README.rst b/README.rst
index dfab356..7481165 100644
--- a/README.rst
+++ b/README.rst
@@ -1,5 +1,5 @@
 :lib:`sky130_fd_sc_ls` - SKY130 Low Speed Digital Standard Cells (SkyWater Provided)
 ====================================================================================
 
-Initial release of version (0, 1, 0).
+Initial release of version (0, 1, 1).
 

cells/diode/sky130_fd_sc_ls__diode_2.lef

diff --git a/cells/diode/sky130_fd_sc_ls__diode_2.lef b/cells/diode/sky130_fd_sc_ls__diode_2.lef
index bd01920..3a6620e 100644
--- a/cells/diode/sky130_fd_sc_ls__diode_2.lef
+++ b/cells/diode/sky130_fd_sc_ls__diode_2.lef
@@ -27,6 +27,7 @@
   SITE unit ;
   PIN DIODE
     ANTENNADIFFAREA  0.641700 ;
+    ANTENNAGATEAREA  0.000000 ;
     DIRECTION INPUT ;
     PORT
       LAYER li1 ;