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  "clock_gating_integrated_cell": "latch_posedge",
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      "related_pin": "CLK",
      "rise_transition,delay_template13x13": {
        "index_1": [
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      "timing_sense": "positive_unate"
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  },
  "pin,M0": {
    "direction": "internal",
    "internal_node": "M0",
    "related_ground_pin": "VNB",
    "related_power_pin": "VPWR"
  },
  "statetable,CLK GATE,M0": {
    "table": [
      "L L : - : L",
      "L H : - : H",
      "H - : - : N"
    ]
  }
}