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  "cell_footprint": "sky130_fd_sc_ls__dlclkp",
  "cell_leakage_power": 0.03394967,
  "clock_gating_integrated_cell": "latch_posedge",
  "driver_waveform_fall": "ramp",
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            0.0794293,
            0.0994051,
            0.130568,
            0.1798765,
            0.2548722,
            0.3703471,
            0.5454002,
            0.8097222
          ],
          [
            0.0477065,
            0.0664345,
            0.0755036,
            0.0878499,
            0.1064786,
            0.1358277,
            0.1833338,
            0.2574913,
            0.3714391,
            0.5481311,
            0.8084183
          ],
          [
            0.0597246,
            0.0808709,
            0.0882981,
            0.0999525,
            0.1184516,
            0.145611,
            0.1893018,
            0.2612826,
            0.3742751,
            0.5489322,
            0.8099963
          ],
          [
            0.0760129,
            0.0992065,
            0.1075933,
            0.1194113,
            0.1364312,
            0.162593,
            0.2035556,
            0.2702043,
            0.3788509,
            0.550014,
            0.8111622
          ],
          [
            0.0988689,
            0.1234063,
            0.1352805,
            0.1466994,
            0.1645803,
            0.1895388,
            0.2258618,
            0.2865473,
            0.3896274,
            0.5544223,
            0.8145734
          ]
        ]
      },
      "timing_sense": "positive_unate"
    }
  },
  "pin,M0": {
    "direction": "internal",
    "internal_node": "M0",
    "related_ground_pin": "VNB",
    "related_power_pin": "VPWR"
  },
  "statetable,CLK GATE,M0": {
    "table": [
      "L L : - : L",
      "L H : - : H",
      "H - : - : N"
    ]
  }
}