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  "cell_leakage_power": 0.004095127,
  "clock_gating_integrated_cell": "latch_posedge",
  "driver_waveform_fall": "ramp",
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  "statetable,CLK GATE,M0": {
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      "L L : - : L",
      "L H : - : H",
      "H - : - : N"
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}