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  "area": 22.3776,
  "cell_footprint": "sky130_fd_sc_ls__dlclkp",
  "cell_leakage_power": 10.80445,
  "clock_gating_integrated_cell": "latch_posedge",
  "driver_waveform_fall": "ramp",
  "driver_waveform_rise": "ramp",
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    "voltage_name": "VNB"
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        "sim_opt": "runlvl=5 accurate=1",
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    "direction": "internal",
    "internal_node": "M0",
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    "related_power_pin": "VPWR"
  },
  "statetable,CLK GATE,M0": {
    "table": [
      "L L : - : L",
      "L H : - : H",
      "H - : - : N"
    ]
  }
}