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  "cell_footprint": "sky130_fd_sc_ls__dlclkp",
  "cell_leakage_power": 202.8266,
  "clock_gating_integrated_cell": "latch_posedge",
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            0.0834282,
            0.1094818,
            0.1502199,
            0.2128178,
            0.308854,
            0.4542717,
            0.6722239,
            1.0029635,
            1.4962278
          ],
          [
            0.033536,
            0.0741484,
            0.0912766,
            0.1172051,
            0.1566956,
            0.2195509,
            0.3143142,
            0.4594657,
            0.6767261,
            1.0054072,
            1.4963526
          ],
          [
            0.0405226,
            0.0835069,
            0.1013834,
            0.1271224,
            0.1669209,
            0.2288827,
            0.3241145,
            0.4689222,
            0.6846114,
            1.0104964,
            1.4995762
          ]
        ]
      },
      "timing_sense": "positive_unate"
    }
  },
  "pin,M0": {
    "direction": "internal",
    "internal_node": "M0",
    "related_ground_pin": "VNB",
    "related_power_pin": "VPWR"
  },
  "statetable,CLK GATE,M0": {
    "table": [
      "L L : - : L",
      "L H : - : H",
      "H - : - : N"
    ]
  }
}