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  "area": 15.984,
  "cell_footprint": "or4bb",
  "cell_leakage_power": 0.0,
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    "pg_type": "primary_ground",
    "voltage_name": "VGND"
  },
  "pg_pin VNB": {
    "pg_type": "primary_ground",
    "voltage_name": "VNB"
  },
  "pg_pin VPB": {
    "pg_type": "primary_power",
    "voltage_name": "VPB"
  },
  "pg_pin VPWR": {
    "pg_type": "primary_power",
    "voltage_name": "VPWR"
  },
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    "capacitance": 0.00246,
    "clock": "false",
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      "rise_power hidden_pwr_template13": {
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    "max_transition": 1.0,
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    "related_power_pin": "VPWR"
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    "capacitance": 0.00249,
    "clock": "false",
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      "fall_power hidden_pwr_template13": {
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      "rise_power hidden_pwr_template13": {
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    "related_power_pin": "VPWR"
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    "clock": "false",
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      "fall_power hidden_pwr_template13": {
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        "values": [
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      "rise_power hidden_pwr_template13": {
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    "related_power_pin": "VPWR"
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    "clock": "false",
    "direction": "input",
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      "fall_power hidden_pwr_template13": {
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      "rise_power hidden_pwr_template13": {
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    "max_transition": 1.0,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR"
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  "pin X": {
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    "function": "(A) | (B) | (!C_N) | (!D_N)",
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