{
  "area": 43.1568,
  "cell_footprint": "edfxtp",
  "cell_leakage_power": 0.0005305307,
  "driver_waveform_fall": "ramp",
  "driver_waveform_rise": "ramp",
  "ff IQ,IQ_N": {
    "clocked_on": "CLK",
    "next_state": "(D&DE) | (IQ&!DE)"
  },
  "leakage_power": [
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      "value": 0.0005292,
      "when": "!D&CLK"
    },
    {
      "value": 0.0003178,
      "when": "D&CLK"
    },
    {
      "value": 0.0005385,
      "when": "D&!CLK"
    },
    {
      "value": 0.0007367,
      "when": "!D&!CLK"
    }
  ],
  "pg_pin VGND": {
    "pg_type": "primary_ground",
    "voltage_name": "VGND"
  },
  "pg_pin VNB": {
    "pg_type": "primary_ground",
    "voltage_name": "VNB"
  },
  "pg_pin VPB": {
    "pg_type": "primary_power",
    "voltage_name": "VPB"
  },
  "pg_pin VPWR": {
    "pg_type": "primary_power",
    "voltage_name": "VPWR"
  },
  "pin CLK": {
    "capacitance": 0.00237,
    "clock": "true",
    "direction": "input",
    "fall_capacitance": 0.002246,
    "internal_power": {
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        "index_1": [
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        "values": [
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      "rise_power hidden_pwr_template13": {
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        "values": [
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    },
    "max_transition": 5.0,
    "min_pulse_width_high": 0.781753,
    "min_pulse_width_low": 1.500249,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.002494
  },
  "pin D": {
    "capacitance": 0.001537,
    "clock": "false",
    "direction": "input",
    "fall_capacitance": 0.001443,
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        "values": [
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      "rise_power hidden_pwr_template13": {
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        "values": [
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    },
    "max_transition": 5.0,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.001631,
    "timing": [
      {
        "fall_constraint vio_10_10_1": {
          "index_1": [
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            0.1041667,
            0.2083333,
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              3.8010993
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              2.0561722,
              2.5470304,
              3.0439922,
              3.5385126
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              0.4018752,
              0.4331795,
              0.4830927,
              0.6012296,
              0.8375035,
              1.3246996,
              1.815558,
              2.307637,
              2.8021572,
              3.2966776
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          ]
        },
        "related_pin": "CLK",
        "rise_constraint vio_10_10_1": {
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            0.1041667,
            0.2083333,
            0.4166667,
            0.8333333,
            1.6666667,
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          "values": [
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        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "setup_rising",
        "violation_delay_degrade_pct": 10
      },
      {
        "fall_constraint vio_10_10_1": {
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          "values": [
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          ]
        },
        "related_pin": "CLK",
        "rise_constraint vio_10_10_1": {
          "index_1": [
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            0.2083333,
            0.4166667,
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          "values": [
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        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "hold_rising",
        "violation_delay_degrade_pct": 10
      }
    ]
  },
  "pin DE": {
    "capacitance": 0.002829,
    "clock": "false",
    "direction": "input",
    "fall_capacitance": 0.002652,
    "internal_power": {
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        "values": [
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      "rise_power hidden_pwr_template13": {
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        "values": [
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    "max_transition": 5.0,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.003007,
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        "fall_constraint vio_10_10_1": {
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          "values": [
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