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  "area": 12.7872,
  "cell_footprint": "o22a",
  "cell_leakage_power": 0.0,
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    "pg_type": "primary_ground",
    "voltage_name": "VGND"
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  "pg_pin VNB": {
    "pg_type": "primary_ground",
    "voltage_name": "VNB"
  },
  "pg_pin VPB": {
    "pg_type": "primary_power",
    "voltage_name": "VPB"
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  "pg_pin VPWR": {
    "pg_type": "primary_power",
    "voltage_name": "VPWR"
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    "capacitance": 0.00251,
    "clock": "false",
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      "rise_power hidden_pwr_template13": {
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    "max_transition": 1.0,
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    "capacitance": 0.00264,
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      "fall_power hidden_pwr_template13": {
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      "rise_power hidden_pwr_template13": {
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    "capacitance": 0.00278,
    "clock": "false",
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      "fall_power hidden_pwr_template13": {
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      "rise_power hidden_pwr_template13": {
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    "max_transition": 1.0,
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    "capacitance": 0.00308,
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      "fall_power hidden_pwr_template13": {
        "index_1": [
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      "rise_power hidden_pwr_template13": {
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    "related_power_pin": "VPWR"
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    "function": "(A1&B1) | (A2&B1) | (A1&B2) | (A2&B2)",
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