| { |
| "area": 55.944, |
| "cell_footprint": "sky130_fd_sc_ls__sedfxtp", |
| "cell_leakage_power": 294.2316, |
| "driver_waveform_fall": "ramp", |
| "driver_waveform_rise": "ramp", |
| "ff,IQ,IQ_N": { |
| "clocked_on": "CLK", |
| "next_state": "(D&DE&!SCE) | (IQ&!DE&!SCE) | (SCD&SCE)" |
| }, |
| "leakage_power": [ |
| { |
| "value": 220.4864131, |
| "when": "!D&!SCE&!SCD&CLK" |
| }, |
| { |
| "value": 212.2855278, |
| "when": "D&!SCE&!SCD&CLK" |
| }, |
| { |
| "value": 332.8358105, |
| "when": "D&SCE&!SCD&CLK" |
| }, |
| { |
| "value": 224.6778052, |
| "when": "D&!SCE&SCD&CLK" |
| }, |
| { |
| "value": 237.4525394, |
| "when": "D&!SCE&!SCD&!CLK" |
| }, |
| { |
| "value": 358.725714, |
| "when": "!D&SCE&!SCD&CLK" |
| }, |
| { |
| "value": 326.0981032, |
| "when": "!D&!SCE&SCD&CLK" |
| }, |
| { |
| "value": 321.1260378, |
| "when": "!D&!SCE&!SCD&!CLK" |
| }, |
| { |
| "value": 421.8073855, |
| "when": "!D&SCE&SCD&CLK" |
| }, |
| { |
| "value": 328.2603984, |
| "when": "!D&SCE&!SCD&!CLK" |
| }, |
| { |
| "value": 424.1395004, |
| "when": "D&SCE&SCD&CLK" |
| }, |
| { |
| "value": 330.6023757, |
| "when": "D&SCE&!SCD&!CLK" |
| }, |
| { |
| "value": 204.4231309, |
| "when": "D&!SCE&SCD&!CLK" |
| }, |
| { |
| "value": 232.7259523, |
| "when": "!D&SCE&SCD&!CLK" |
| }, |
| { |
| "value": 207.6789798, |
| "when": "D&SCE&SCD&!CLK" |
| }, |
| { |
| "value": 324.3803519, |
| "when": "!D&!SCE&SCD&!CLK" |
| } |
| ], |
| "pg_pin,VGND": { |
| "pg_type": "primary_ground", |
| "related_bias_pin": "VPB", |
| "voltage_name": "VGND" |
| }, |
| "pg_pin,VNB": { |
| "pg_type": "nwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VNB" |
| }, |
| "pg_pin,VPB": { |
| "pg_type": "pwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VPB" |
| }, |
| "pg_pin,VPWR": { |
| "pg_type": "primary_power", |
| "related_bias_pin": "VNB", |
| "voltage_name": "VPWR" |
| }, |
| "pin,CLK": { |
| "capacitance": 0.002738, |
| "clock": "true", |
| "direction": "input", |
| "fall_capacitance": 0.002655, |
| "internal_power": { |
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| 0.01, |
| 0.01735, |
| 0.02602, |
| 0.03903, |
| 0.05855, |
| 0.08782, |
| 0.13172, |
| 0.19757, |
| 0.29634, |
| 0.44449, |
| 0.6667, |
| 1.0, |
| 1.5 |
| ], |
| "values": [ |
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| 0.0225113, |
| 0.0222456, |
| 0.0220459, |
| 0.0218382, |
| 0.021543, |
| 0.021192, |
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| 0.0205428, |
| 0.0205032, |
| 0.0205356, |
| 0.020676, |
| 0.0209787 |
| ] |
| }, |
| "rise_power,hidden_pwr_template13": { |
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| 0.01, |
| 0.01735, |
| 0.02602, |
| 0.03903, |
| 0.05855, |
| 0.08782, |
| 0.13172, |
| 0.19757, |
| 0.29634, |
| 0.44449, |
| 0.6667, |
| 1.0, |
| 1.5 |
| ], |
| "values": [ |
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| 0.016683, |
| 0.0166372, |
| 0.0166484, |
| 0.0167449, |
| 0.0169692 |
| ] |
| } |
| }, |
| "max_transition": 1.5, |
| "min_pulse_width_high": 0.53671, |
| "min_pulse_width_low": 0.579551, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
| "rise_capacitance": 0.002821 |
| }, |
| "pin,D": { |
| "capacitance": 0.001857, |
| "clock": "false", |
| "direction": "input", |
| "fall_capacitance": 0.001783, |
| "internal_power": { |
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| 0.01, |
| 0.01735, |
| 0.02602, |
| 0.03903, |
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| 0.19757, |
| 0.29634, |
| 0.44449, |
| 0.6667, |
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| ], |
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| 0.0085266, |
| 0.0087909, |
| 0.0099105, |
| 0.0116691, |
| 0.0115726, |
| 0.011507, |
| 0.0114879, |
| 0.0115386 |
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| }, |
| "rise_power,hidden_pwr_template13": { |
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| 0.01735, |
| 0.02602, |
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| 0.44449, |
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| 0.00819, |
| 0.0079971, |
| 0.0078001 |
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| } |
| }, |
| "max_transition": 1.5, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
| "rise_capacitance": 0.001932, |
| "timing": [ |
| { |
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| 0.03125, |
| 0.0625, |
| 0.125, |
| 0.25, |
| 0.5, |
| 0.75, |
| 1.0, |
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| [ |
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| [ |
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| [ |
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| 0.9089824, |
| 1.0058249, |
| 1.100226, |
| 1.1909648 |
| ] |
| ] |
| }, |
| "related_pin": "CLK", |
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| 0.01, |
| 0.03125, |
| 0.0625, |
| 0.125, |
| 0.25, |
| 0.5, |
| 0.75, |
| 1.0, |
| 1.25, |
| 1.5 |
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| 0.75, |
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| ], |
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| [ |
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| [ |
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| 0.762905, |
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| ] |
| }, |
| "sim_opt": "runlvl=5 accurate=1", |
| "timing_type": "setup_rising", |
| "violation_delay_degrade_pct": 10 |
| }, |
| { |
| "fall_constraint,vio_10_10_1": { |
| "index_1": [ |
| 0.01, |
| 0.03125, |
| 0.0625, |
| 0.125, |
| 0.25, |
| 0.5, |
| 0.75, |
| 1.0, |
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| [ |
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| [ |
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| ] |
| ] |
| }, |
| "related_pin": "CLK", |
| "rise_constraint,vio_10_10_1": { |
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| 0.01, |
| 0.03125, |
| 0.0625, |
| 0.125, |
| 0.25, |
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| 0.75, |
| 1.0, |
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| 1.5 |
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| }, |
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| }, |
| "test_cell": { |
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| "next_state": "(D&DE) | (IQ&!DE)" |
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| "pin,DE": { |
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| "pin,SCD": { |
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| "pin,SCE": { |
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| "signal_type": "test_scan_enable" |
| } |
| } |
| } |
