| { |
| "area": 27.1728, |
| "cell_footprint": "sky130_fd_sc_ls__sdlclkp", |
| "cell_leakage_power": 0.0337026, |
| "clock_gating_integrated_cell": "latch_posedge_precontrol", |
| "driver_waveform_fall": "ramp", |
| "driver_waveform_rise": "ramp", |
| "leakage_power": [ |
| { |
| "value": 0.0344979, |
| "when": "!GATE&!SCE&CLK" |
| }, |
| { |
| "value": 0.031748, |
| "when": "GATE&!SCE&!CLK" |
| }, |
| { |
| "value": 0.0352004, |
| "when": "!GATE&SCE&!CLK" |
| }, |
| { |
| "value": 0.0375349, |
| "when": "!GATE&SCE&CLK" |
| }, |
| { |
| "value": 0.0317477, |
| "when": "GATE&SCE&!CLK" |
| }, |
| { |
| "value": 0.0307272, |
| "when": "!GATE&!SCE&!CLK" |
| }, |
| { |
| "value": 0.0340825, |
| "when": "GATE&!SCE&CLK" |
| }, |
| { |
| "value": 0.0340822, |
| "when": "GATE&SCE&CLK" |
| } |
| ], |
| "pg_pin,VGND": { |
| "pg_type": "primary_ground", |
| "related_bias_pin": "VPB", |
| "voltage_name": "VGND" |
| }, |
| "pg_pin,VNB": { |
| "pg_type": "nwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VNB" |
| }, |
| "pg_pin,VPB": { |
| "pg_type": "pwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VPB" |
| }, |
| "pg_pin,VPWR": { |
| "pg_type": "primary_power", |
| "related_bias_pin": "VNB", |
| "voltage_name": "VPWR" |
| }, |
| "pin,CLK": { |
| "capacitance": 0.004363, |
| "clock": "true", |
| "clock_gate_clock_pin": "true", |
| "direction": "input", |
| "fall_capacitance": 0.004146, |
| "internal_power": { |
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| 0.01774, |
| 0.0180547, |
| 0.0185269 |
| ] |
| }, |
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| 0.006966 |
| ] |
| } |
| }, |
| "max_transition": 5.0, |
| "min_pulse_width_low": 0.217656, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
| "rise_capacitance": 0.00458 |
| }, |
| "pin,GATE": { |
| "capacitance": 0.002308, |
| "clock": "false", |
| "clock_gate_enable_pin": "true", |
| "direction": "input", |
| "fall_capacitance": 0.002195, |
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| 0.0218313, |
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| 0.0132479, |
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| }, |
| "max_transition": 5.0, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
| "rise_capacitance": 0.002421, |
| "timing": [ |
| { |
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| 1.1535299, |
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| 1.3048972, |
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| [ |
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| 1.1044305, |
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| 1.4709128 |
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| [ |
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| 1.107957, |
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| 0.9293275, |
| 1.1406447, |
| 1.3336516, |
| 1.5120098 |
| ] |
| ] |
| }, |
| "related_pin": "CLK", |
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| 0.335252, |
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| }, |
| "sim_opt": "runlvl=5 accurate=1", |
| "timing_type": "setup_rising", |
| "violation_delay_degrade_pct": 10 |
| }, |
| { |
| "clk_width": 6.8e-08, |
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| ] |
| }, |
| "related_pin": "CLK", |
| "rise_constraint,vio_10_10_1": { |
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| 0.0333333, |
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| ] |
| ] |
| }, |
| "sim_opt": "runlvl=5 accurate=1", |
| "timing_type": "hold_rising", |
| "violation_delay_degrade_pct": 10 |
| } |
| ] |
| }, |
| "pin,GCLK": { |
| "clock_gate_out_pin": "true", |
| "direction": "output", |
| "internal_power": { |
| "fall_power,pwr_template13x9": { |
| "index_1": [ |
| 0.0333333, |
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| 0.9878, |
| 1.48163, |
| 2.22233, |
| 3.33333, |
| 5 |
| ], |
| "index_2": [ |
| 0, |
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| }, |
| "statetable,CLK GATE SCE,M0": { |
| "table": [ |
| "L L L : - : L", |
| "L L H : - : H", |
| "L H L : - : H", |
| "L H H : - : H", |
| "H - - : - : N" |
| ] |
| } |
| } |
