| { |
| "area": 39.96, |
| "cell_footprint": "sky130_fd_sc_ls__sdfxtp", |
| "cell_leakage_power": 0.008614261, |
| "driver_waveform_fall": "ramp", |
| "driver_waveform_rise": "ramp", |
| "ff,IQ,IQ_N": { |
| "clocked_on": "CLK", |
| "next_state": "(D&!SCE) | (SCD&SCE)" |
| }, |
| "leakage_power": [ |
| { |
| "value": 0.0114426, |
| "when": "D&!SCD&!SCE&CLK" |
| }, |
| { |
| "value": 0.0091137, |
| "when": "!D&!SCD&SCE&CLK" |
| }, |
| { |
| "value": 0.0070894, |
| "when": "!D&SCD&!SCE&CLK" |
| }, |
| { |
| "value": 0.0081903, |
| "when": "!D&!SCD&!SCE&!CLK" |
| }, |
| { |
| "value": 0.004338, |
| "when": "!D&!SCD&!SCE&CLK" |
| }, |
| { |
| "value": 0.006551, |
| "when": "D&!SCD&SCE&CLK" |
| }, |
| { |
| "value": 0.0086431, |
| "when": "D&SCD&!SCE&CLK" |
| }, |
| { |
| "value": 0.0087299, |
| "when": "D&!SCD&!SCE&!CLK" |
| }, |
| { |
| "value": 0.0092592, |
| "when": "!D&SCD&SCE&CLK" |
| }, |
| { |
| "value": 0.0103273, |
| "when": "!D&!SCD&SCE&!CLK" |
| }, |
| { |
| "value": 0.0114368, |
| "when": "D&SCD&SCE&CLK" |
| }, |
| { |
| "value": 0.0104033, |
| "when": "D&!SCD&SCE&!CLK" |
| }, |
| { |
| "value": 0.008303, |
| "when": "!D&SCD&!SCE&!CLK" |
| }, |
| { |
| "value": 0.0087298, |
| "when": "D&SCD&!SCE&!CLK" |
| }, |
| { |
| "value": 0.0065465, |
| "when": "!D&SCD&SCE&!CLK" |
| }, |
| { |
| "value": 0.0087242, |
| "when": "D&SCD&SCE&!CLK" |
| } |
| ], |
| "pg_pin,VGND": { |
| "pg_type": "primary_ground", |
| "related_bias_pin": "VPB", |
| "voltage_name": "VGND" |
| }, |
| "pg_pin,VNB": { |
| "pg_type": "nwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VNB" |
| }, |
| "pg_pin,VPB": { |
| "pg_type": "pwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VPB" |
| }, |
| "pg_pin,VPWR": { |
| "pg_type": "primary_power", |
| "related_bias_pin": "VNB", |
| "voltage_name": "VPWR" |
| }, |
| "pin,CLK": { |
| "capacitance": 0.002618, |
| "clock": "true", |
| "direction": "input", |
| "fall_capacitance": 0.002484, |
| "internal_power": { |
| "fall_power,hidden_pwr_template13": { |
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| 0.0578333, |
| 0.0867333, |
| 0.1301, |
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| 0.2927333, |
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| 0.6585667, |
| 0.9878, |
| 1.4816333, |
| 2.2223333, |
| 3.3333333, |
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| ], |
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| 0.0270124, |
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| 0.026576, |
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| 0.0264857, |
| 0.0263992, |
| 0.0263476, |
| 0.02627, |
| 0.0261539, |
| 0.0259797 |
| ] |
| }, |
| "rise_power,hidden_pwr_template13": { |
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| "values": [ |
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| 0.0193607, |
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| 0.0191515, |
| 0.0189633, |
| 0.0186809 |
| ] |
| } |
| }, |
| "max_transition": 1.5, |
| "min_pulse_width_high": 0.218141, |
| "min_pulse_width_low": 0.505951, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
| "rise_capacitance": 0.002752 |
| }, |
| "pin,D": { |
| "capacitance": 0.001794, |
| "clock": "false", |
| "direction": "input", |
| "fall_capacitance": 0.001688, |
| "internal_power": { |
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| 0.0095344, |
| 0.0095197, |
| 0.0094976, |
| 0.0094644 |
| ] |
| }, |
| "rise_power,hidden_pwr_template13": { |
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| 0.00231, |
| 0.0022534, |
| 0.0021686, |
| 0.0020415 |
| ] |
| } |
| }, |
| "max_transition": 1.5, |
| "nextstate_type": "data", |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
| "rise_capacitance": 0.0019, |
| "timing": [ |
| { |
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| [ |
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| 1.0611634, |
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| [ |
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| [ |
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| 1.0172181, |
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| [ |
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| [ |
| 0.3846986, |
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| 1.0212871, |
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| [ |
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| 0.3336243, |
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| 0.9610657, |
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| [ |
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| 0.2831686, |
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| 0.6485657, |
| 0.7820293, |
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| [ |
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| 0.6066549, |
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| 0.9985007 |
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| [ |
| 0.193862, |
| 0.2017884, |
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| 0.4373841, |
| 0.5659648, |
| 0.7006491, |
| 0.8304505, |
| 0.9590312 |
| ] |
| ] |
| }, |
| "related_pin": "CLK", |
| "rise_constraint,vio_10_10_1": { |
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| 0.0333333, |
| 0.1041667, |
| 0.2083333, |
| 0.4166667, |
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| 3.3333333, |
| 4.1666667, |
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| ], |
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| ], |
| "values": [ |
| [ |
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| 0.4420553, |
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| [ |
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| 0.5911927, |
| 0.659959, |
| 0.721401 |
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| [ |
| 0.2154277, |
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| 0.4150045, |
| 0.5008607, |
| 0.5757305, |
| 0.643276, |
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| [ |
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| 0.1936504, |
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| 0.3853008, |
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| 0.5460267, |
| 0.614793, |
| 0.6774557 |
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| [ |
| 0.1458477, |
| 0.1562155, |
| 0.1692363, |
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| 0.5024883, |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| 0.2852031, |
| 0.3551901, |
| 0.4166322, |
| 0.4744121 |
| ] |
| ] |
| }, |
| "sim_opt": "runlvl=5 accurate=1", |
| "timing_type": "setup_rising", |
| "violation_delay_degrade_pct": 10 |
| }, |
| { |
| "fall_constraint,vio_10_10_1": { |
| "index_1": [ |
| 0.0333333, |
| 0.1041667, |
| 0.2083333, |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| ] |
| }, |
| "related_pin": "CLK", |
| "rise_constraint,vio_10_10_1": { |
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| 0.0333333, |
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| }, |
| "related_pin": "CLK", |
| "rise_constraint,vio_10_10_1": { |
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| ] |
| }, |
| "sim_opt": "runlvl=5 accurate=1", |
| "timing_type": "hold_rising", |
| "violation_delay_degrade_pct": 10 |
| } |
| ] |
| }, |
| "test_cell": { |
| "ff,IQ,IQ_N": { |
| "clocked_on": "CLK", |
| "next_state": "D" |
| }, |
| "pin,CLK": { |
| "direction": "input" |
| }, |
| "pin,D": { |
| "direction": "input" |
| }, |
| "pin,Q": { |
| "direction": "output", |
| "function": "IQ", |
| "signal_type": "test_scan_out" |
| }, |
| "pin,SCD": { |
| "direction": "input", |
| "signal_type": "test_scan_in" |
| }, |
| "pin,SCE": { |
| "direction": "input", |
| "signal_type": "test_scan_enable" |
| } |
| } |
| } |
