| { |
| "area": 36.7632, |
| "cell_footprint": "sky130_fd_sc_ls__sdfxtp", |
| "cell_leakage_power": 0.0006252758, |
| "driver_waveform_fall": "ramp", |
| "driver_waveform_rise": "ramp", |
| "ff,IQ,IQ_N": { |
| "clocked_on": "CLK", |
| "next_state": "(D&!SCE) | (SCD&SCE)" |
| }, |
| "leakage_power": [ |
| { |
| "value": 0.0006687, |
| "when": "D&SCD&!SCE&!CLK" |
| }, |
| { |
| "value": 0.0004965, |
| "when": "!D&SCD&SCE&!CLK" |
| }, |
| { |
| "value": 0.0006365, |
| "when": "D&SCD&SCE&!CLK" |
| }, |
| { |
| "value": 0.0007916, |
| "when": "D&!SCD&!SCE&CLK" |
| }, |
| { |
| "value": 0.0006119, |
| "when": "!D&!SCD&SCE&CLK" |
| }, |
| { |
| "value": 0.000579, |
| "when": "!D&SCD&!SCE&CLK" |
| }, |
| { |
| "value": 0.0005736, |
| "when": "!D&!SCD&!SCE&!CLK" |
| }, |
| { |
| "value": 0.0004277, |
| "when": "!D&!SCD&!SCE&CLK" |
| }, |
| { |
| "value": 0.0005566, |
| "when": "D&!SCD&SCE&CLK" |
| }, |
| { |
| "value": 0.0006183, |
| "when": "D&SCD&!SCE&CLK" |
| }, |
| { |
| "value": 0.0006688, |
| "when": "D&!SCD&!SCE&!CLK" |
| }, |
| { |
| "value": 0.0006192, |
| "when": "!D&SCD&SCE&CLK" |
| }, |
| { |
| "value": 0.0006635, |
| "when": "!D&!SCD&SCE&!CLK" |
| }, |
| { |
| "value": 0.0007593, |
| "when": "D&SCD&SCE&CLK" |
| }, |
| { |
| "value": 0.0007025, |
| "when": "D&!SCD&SCE&!CLK" |
| }, |
| { |
| "value": 0.0006307, |
| "when": "!D&SCD&!SCE&!CLK" |
| } |
| ], |
| "pg_pin,VGND": { |
| "pg_type": "primary_ground", |
| "related_bias_pin": "VPB", |
| "voltage_name": "VGND" |
| }, |
| "pg_pin,VNB": { |
| "pg_type": "nwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VNB" |
| }, |
| "pg_pin,VPB": { |
| "pg_type": "pwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VPB" |
| }, |
| "pg_pin,VPWR": { |
| "pg_type": "primary_power", |
| "related_bias_pin": "VNB", |
| "voltage_name": "VPWR" |
| }, |
| "pin,CLK": { |
| "capacitance": 0.002444, |
| "clock": "true", |
| "direction": "input", |
| "fall_capacitance": 0.002299, |
| "internal_power": { |
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| 1.48163, |
| 2.22233, |
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| 0.0167775, |
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| 0.0166513, |
| 0.0166106, |
| 0.0165496, |
| 0.016458 |
| ] |
| }, |
| "rise_power,hidden_pwr_template13": { |
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| 0.0122681, |
| 0.0121726, |
| 0.0120293 |
| ] |
| } |
| }, |
| "max_transition": 5.0, |
| "min_pulse_width_high": 0.484028, |
| "min_pulse_width_low": 1.224496, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
| "rise_capacitance": 0.00259 |
| }, |
| "pin,D": { |
| "capacitance": 0.001668, |
| "clock": "false", |
| "direction": "input", |
| "fall_capacitance": 0.00158, |
| "internal_power": { |
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| 0.0060624, |
| 0.0060577, |
| 0.0060505, |
| 0.0060398 |
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| }, |
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| 0.0012244, |
| 0.0011898, |
| 0.001138 |
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| } |
| }, |
| "max_transition": 5.0, |
| "nextstate_type": "data", |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
| "rise_capacitance": 0.001757, |
| "timing": [ |
| { |
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| [ |
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| [ |
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| [ |
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| 1.2186341, |
| 1.7278029, |
| 2.2345304, |
| 2.7375957 |
| ] |
| ] |
| }, |
| "related_pin": "CLK", |
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| [ |
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| [ |
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| 2.0610549, |
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| [ |
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| 1.9624491, |
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| [ |
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| ] |
| }, |
| "sim_opt": "runlvl=5 accurate=1", |
| "timing_type": "setup_rising", |
| "violation_delay_degrade_pct": 10 |
| }, |
| { |
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| 0.0333333, |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| }, |
| "related_pin": "CLK", |
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| }, |
| "test_cell": { |
| "ff,IQ,IQ_N": { |
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| "next_state": "D" |
| }, |
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| "pin,Q": { |
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| "pin,SCD": { |
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| }, |
| "pin,SCE": { |
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| "signal_type": "test_scan_enable" |
| } |
| } |
| } |
