| { | |
| "area": 47.952, | |
| "cell_footprint": "sky130_fd_sc_ls__sdfsbp", | |
| "cell_leakage_power": 55.40686, | |
| "driver_waveform_fall": "ramp", | |
| "driver_waveform_rise": "ramp", | |
| "ff,IQ,IQ_N": { | |
| "clocked_on": "CLK", | |
| "next_state": "(D&!SCE) | (SCD&SCE)", | |
| "preset": "!SET_B" | |
| }, | |
| "leakage_power": [ | |
| { | |
| "value": 52.0909929, | |
| "when": "D&!SCD&!SCE&SET_B&CLK" | |
| }, | |
| { | |
| "value": 44.8133335, | |
| "when": "!D&!SCD&SCE&SET_B&CLK" | |
| }, | |
| { | |
| "value": 42.3546744, | |
| "when": "!D&SCD&!SCE&SET_B&CLK" | |
| }, | |
| { | |
| "value": 39.2423729, | |
| "when": "!D&!SCD&!SCE&SET_B&!CLK" | |
| }, | |
| { | |
| "value": 46.5532786, | |
| "when": "!D&!SCD&!SCE&!SET_B&CLK" | |
| }, | |
| { | |
| "value": 47.6067434, | |
| "when": "!D&!SCD&!SCE&SET_B&CLK" | |
| }, | |
| { | |
| "value": 52.2361816, | |
| "when": "D&!SCD&SCE&SET_B&CLK" | |
| }, | |
| { | |
| "value": 42.7901305, | |
| "when": "D&SCD&!SCE&SET_B&CLK" | |
| }, | |
| { | |
| "value": 43.8473009, | |
| "when": "D&!SCD&!SCE&SET_B&!CLK" | |
| }, | |
| { | |
| "value": 44.6117241, | |
| "when": "D&!SCD&!SCE&!SET_B&CLK" | |
| }, | |
| { | |
| "value": 55.4068578, | |
| "when": "!D&SCD&SCE&SET_B&CLK" | |
| }, | |
| { | |
| "value": 42.9274145, | |
| "when": "!D&!SCD&SCE&SET_B&!CLK" | |
| }, | |
| { | |
| "value": 50.2383202, | |
| "when": "!D&!SCD&SCE&!SET_B&CLK" | |
| }, | |
| { | |
| "value": 53.5942704, | |
| "when": "D&SCD&SCE&SET_B&CLK" | |
| }, | |
| { | |
| "value": 43.8722552, | |
| "when": "D&!SCD&SCE&SET_B&!CLK" | |
| }, | |
| { | |
| "value": 51.1822726, | |
| "when": "D&!SCD&SCE&!SET_B&CLK" | |
| }, | |
| { | |
| "value": 40.4656539, | |
| "when": "!D&SCD&!SCE&SET_B&!CLK" | |
| }, | |
| { | |
| "value": 47.7770037, | |
| "when": "!D&SCD&!SCE&!SET_B&CLK" | |
| }, | |
| { | |
| "value": 40.9722425, | |
| "when": "D&SCD&!SCE&SET_B&!CLK" | |
| }, | |
| { | |
| "value": 41.7371062, | |
| "when": "D&SCD&!SCE&!SET_B&CLK" | |
| }, | |
| { | |
| "value": 45.2404372, | |
| "when": "D&!SCD&SCE&!SET_B&!CLK" | |
| }, | |
| { | |
| "value": 43.2764473, | |
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| }, | |
| { | |
| "value": 47.1640504, | |
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| }, | |
| { | |
| "value": 47.9289177, | |
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| }, | |
| { | |
| "value": 45.3496902, | |
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| }, | |
| { | |
| "value": 46.1158862, | |
| "when": "D&SCD&SCE&!SET_B&CLK" | |
| }, | |
| { | |
| "value": 40.6096703, | |
| "when": "!D&!SCD&!SCE&!SET_B&!CLK" | |
| }, | |
| { | |
| "value": 41.8351647, | |
| "when": "!D&SCD&!SCE&!SET_B&!CLK" | |
| }, | |
| { | |
| "value": 44.2978099, | |
| "when": "!D&!SCD&SCE&!SET_B&!CLK" | |
| }, | |
| { | |
| "value": 45.090367, | |
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| }, | |
| { | |
| "value": 41.7731734, | |
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| }, | |
| { | |
| "value": 38.8985555, | |
| "when": "D&SCD&!SCE&!SET_B&!CLK" | |
| } | |
| ], | |
| "pg_pin,VGND": { | |
| "pg_type": "primary_ground", | |
| "related_bias_pin": "VPB", | |
| "voltage_name": "VGND" | |
| }, | |
| "pg_pin,VNB": { | |
| "pg_type": "nwell", | |
| "physical_connection": "device_layer", | |
| "voltage_name": "VNB" | |
| }, | |
| "pg_pin,VPB": { | |
| "pg_type": "pwell", | |
| "physical_connection": "device_layer", | |
| "voltage_name": "VPB" | |
| }, | |
| "pg_pin,VPWR": { | |
| "pg_type": "primary_power", | |
| "related_bias_pin": "VNB", | |
| "voltage_name": "VPWR" | |
| }, | |
| "pin,CLK": { | |
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| "clock": "true", | |
| "direction": "input", | |
| "fall_capacitance": 0.002738, | |
| "internal_power": { | |
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| "rise_power,hidden_pwr_template13": { | |
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| 0.0492757, | |
| 0.0638617 | |
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| } | |
| }, | |
| "max_transition": 1.0, | |
| "min_pulse_width_high": 0.16761, | |
| "min_pulse_width_low": 0.178595, | |
| "related_ground_pin": "VGND", | |
| "related_power_pin": "VPWR", | |
| "rise_capacitance": 0.002978 | |
| }, | |
| "pin,D": { | |
| "capacitance": 0.001979, | |
| "clock": "false", | |
| "direction": "input", | |
| "fall_capacitance": 0.001914, | |
| "internal_power": { | |
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| 0.0271751 | |
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| }, | |
| "rise_power,hidden_pwr_template13": { | |
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| } | |
| }, | |
| "max_transition": 1.0, | |
| "nextstate_type": "data", | |
| "related_ground_pin": "VGND", | |
| "related_power_pin": "VPWR", | |
| "rise_capacitance": 0.002044, | |
| "timing": [ | |
| { | |
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| [ | |
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| [ | |
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| }, | |
| "related_pin": "CLK", | |
| "rise_constraint,vio_10_10_1": { | |
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| "values": [ | |
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| }, | |
| "sim_opt": "runlvl=5 accurate=1", | |
| "timing_type": "setup_rising", | |
| "violation_delay_degrade_pct": 10 | |
| }, | |
| { | |
| "fall_constraint,vio_10_10_1": { | |
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