| { |
| "area": 43.1568, |
| "cell_footprint": "sky130_fd_sc_ls__edfxtp", |
| "cell_leakage_power": 0.03271764, |
| "driver_waveform_fall": "ramp", |
| "driver_waveform_rise": "ramp", |
| "ff,IQ,IQ_N": { |
| "clocked_on": "CLK", |
| "next_state": "(D&DE) | (IQ&!DE)" |
| }, |
| "leakage_power": [ |
| { |
| "value": 0.036229, |
| "when": "!D&CLK" |
| }, |
| { |
| "value": 0.0331472, |
| "when": "D&CLK" |
| }, |
| { |
| "value": 0.0305149, |
| "when": "D&!CLK" |
| }, |
| { |
| "value": 0.0309795, |
| "when": "!D&!CLK" |
| } |
| ], |
| "pg_pin,VGND": { |
| "pg_type": "primary_ground", |
| "related_bias_pin": "VPB", |
| "voltage_name": "VGND" |
| }, |
| "pg_pin,VNB": { |
| "pg_type": "nwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VNB" |
| }, |
| "pg_pin,VPB": { |
| "pg_type": "pwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VPB" |
| }, |
| "pg_pin,VPWR": { |
| "pg_type": "primary_power", |
| "related_bias_pin": "VNB", |
| "voltage_name": "VPWR" |
| }, |
| "pin,CLK": { |
| "capacitance": 0.002339, |
| "clock": "true", |
| "direction": "input", |
| "fall_capacitance": 0.002219, |
| "internal_power": { |
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| ], |
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| ] |
| }, |
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| ] |
| } |
| }, |
| "max_transition": 5.0, |
| "min_pulse_width_high": 0.905809, |
| "min_pulse_width_low": 1.767042, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
| "rise_capacitance": 0.00246 |
| }, |
| "pin,D": { |
| "capacitance": 0.001519, |
| "clock": "false", |
| "direction": "input", |
| "fall_capacitance": 0.001439, |
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| 0.005948, |
| 0.0059464, |
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| 0.0059406 |
| ] |
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| 0.0028375, |
| 0.0027843 |
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| }, |
| "max_transition": 5.0, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
| "rise_capacitance": 0.0016, |
| "timing": [ |
| { |
| "clk_width": 6.8e-08, |
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| [ |
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| [ |
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| [ |
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| 4.302944, |
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| [ |
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| 2.4432705, |
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| 3.4481805, |
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| [ |
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| 3.127, |
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| [ |
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| [ |
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| 2.0609193, |
| 2.5688674, |
| 3.0694914, |
| 3.5749981 |
| ] |
| ] |
| }, |
| "related_pin": "CLK", |
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| [ |
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| 2.0974047, |
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| [ |
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| 2.3079084, |
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| [ |
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| 2.1644078, |
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| [ |
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| }, |
| "sim_opt": "runlvl=5 accurate=1", |
| "timing_type": "setup_rising", |
| "violation_delay_degrade_pct": 10 |
| }, |
| { |
| "clk_width": 6.8e-08, |
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| ] |
| }, |
| "related_pin": "CLK", |
| "rise_constraint,vio_10_10_1": { |
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| 0.0333333, |
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| ] |
| }, |
| "sim_opt": "runlvl=5 accurate=1", |
| "timing_type": "hold_rising", |
| "violation_delay_degrade_pct": 10 |
| } |
| ] |
| }, |
| "pin,DE": { |
| "capacitance": 0.002784, |
| "clock": "false", |
| "direction": "input", |
| "fall_capacitance": 0.002609, |
| "internal_power": { |
| "fall_power,hidden_pwr_template13": { |
| "index_1": [ |
| 0.0333333, |
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| 1.48163, |
| 2.22233, |
| 3.33333, |
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| 0.0064784 |
| ] |
| }, |
| "rise_power,hidden_pwr_template13": { |
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