| { |
| "area": 43.1568, |
| "cell_footprint": "sky130_fd_sc_ls__edfxtp", |
| "cell_leakage_power": 21.80853, |
| "driver_waveform_fall": "ramp", |
| "driver_waveform_rise": "ramp", |
| "ff,IQ,IQ_N": { |
| "clocked_on": "CLK", |
| "next_state": "(D&DE) | (IQ&!DE)" |
| }, |
| "leakage_power": [ |
| { |
| "value": 21.5201847, |
| "when": "!D&CLK" |
| }, |
| { |
| "value": 17.1847248, |
| "when": "D&CLK" |
| }, |
| { |
| "value": 19.1735143, |
| "when": "D&!CLK" |
| }, |
| { |
| "value": 29.3557108, |
| "when": "!D&!CLK" |
| } |
| ], |
| "pg_pin,VGND": { |
| "pg_type": "primary_ground", |
| "related_bias_pin": "VPB", |
| "voltage_name": "VGND" |
| }, |
| "pg_pin,VNB": { |
| "pg_type": "nwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VNB" |
| }, |
| "pg_pin,VPB": { |
| "pg_type": "pwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VPB" |
| }, |
| "pg_pin,VPWR": { |
| "pg_type": "primary_power", |
| "related_bias_pin": "VNB", |
| "voltage_name": "VPWR" |
| }, |
| "pin,CLK": { |
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| "clock": "true", |
| "direction": "input", |
| "fall_capacitance": 0.002525, |
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| }, |
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| "min_pulse_width_low": 0.715767, |
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| "related_power_pin": "VPWR", |
| "rise_capacitance": 0.002733 |
| }, |
| "pin,D": { |
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| }, |
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| "related_power_pin": "VPWR", |
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| 1.1856752, |
| 1.297166 |
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| ] |
| }, |
| "related_pin": "CLK", |
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| "sim_opt": "runlvl=5 accurate=1", |
| "timing_type": "setup_rising", |
| "violation_delay_degrade_pct": 10 |
| }, |
| { |
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| ] |
| }, |
| "related_pin": "CLK", |
| "rise_constraint,vio_10_10_1": { |
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| 0.03125, |
| 0.0625, |
| 0.125, |
| 0.25, |
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| 0.75, |
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| }, |
| "sim_opt": "runlvl=5 accurate=1", |
| "timing_type": "hold_rising", |
| "violation_delay_degrade_pct": 10 |
| } |
| ] |
| }, |
| "pin,DE": { |
| "capacitance": 0.003114, |
| "clock": "false", |
| "direction": "input", |
| "fall_capacitance": 0.003008, |
| "internal_power": { |
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