{
  "area": 36.7632,
  "cell_footprint": "dfxbp",
  "cell_leakage_power": 19.45948,
  "driver_waveform_fall": "ramp",
  "driver_waveform_rise": "ramp",
  "ff IQ,IQ_N": {
    "clocked_on": "CLK",
    "next_state": "D"
  },
  "leakage_power": [
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      "value": 22.5370655,
      "when": "D&CLK"
    },
    {
      "value": 17.0408683,
      "when": "!D&!CLK"
    },
    {
      "value": 19.5018917,
      "when": "!D&CLK"
    },
    {
      "value": 18.7581044,
      "when": "D&!CLK"
    }
  ],
  "pg_pin VGND": {
    "pg_type": "primary_ground",
    "voltage_name": "VGND"
  },
  "pg_pin VNB": {
    "pg_type": "primary_ground",
    "voltage_name": "VNB"
  },
  "pg_pin VPB": {
    "pg_type": "primary_power",
    "voltage_name": "VPB"
  },
  "pg_pin VPWR": {
    "pg_type": "primary_power",
    "voltage_name": "VPWR"
  },
  "pin CLK": {
    "capacitance": 0.002644,
    "clock": "true",
    "direction": "input",
    "fall_capacitance": 0.002522,
    "internal_power": {
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        "index_1": [
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          0.02602,
          0.03903,
          0.05855,
          0.08782,
          0.13172,
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          0.29634,
          0.44449,
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        "values": [
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          0.025005,
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      },
      "rise_power hidden_pwr_template13": {
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        "values": [
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    },
    "max_transition": 1.5,
    "min_pulse_width_high": 0.309318,
    "min_pulse_width_low": 0.488375,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.002767
  },
  "pin D": {
    "capacitance": 0.001671,
    "clock": "false",
    "direction": "input",
    "fall_capacitance": 0.001742,
    "internal_power": {
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        "values": [
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      "rise_power hidden_pwr_template13": {
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        ],
        "values": [
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    },
    "max_transition": 1.5,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.0016,
    "timing": [
      {
        "fall_constraint vio_10_10_1": {
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            0.5,
            0.75,
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              0.3181621,
              0.4284323,
              0.5350404,
              0.6343242
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          ]
        },
        "related_pin": "CLK",
        "rise_constraint vio_10_10_1": {
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            0.125,
            0.25,
            0.5,
            0.75,
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          "values": [
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          ]
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        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "setup_rising",
        "violation_delay_degrade_pct": 10
      },
      {
        "fall_constraint vio_10_10_1": {
          "index_1": [
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            0.5,
            0.75,
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          "values": [
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          ]
        },
        "related_pin": "CLK",
        "rise_constraint vio_10_10_1": {
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            0.0625,
            0.125,
            0.25,
            0.5,
            0.75,
            1.0,
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            0.0625,
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            0.25,
            0.5,
            0.75,
            1.0,
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          "values": [
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          ]
        },
        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "hold_rising",
        "violation_delay_degrade_pct": 10
      }
    ]
  },
  "pin Q": {
    "direction": "output",
    "function": "IQ",
    "internal_power": {
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        "index_2": [
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          0.02405,
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        "values": [
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        ]
      },
      "related_pin": "CLK",
      "rise_power pwr_template13x7": {
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        "index_2": [
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