

                  ##################################################
                  ##                                              ##
                  ##         C A L I B R E    S Y S T E M         ##
                  ##                                              ##
                  ##             L V S   R E P O R T              ##
                  ##                                              ##
                  ##################################################


REPORT FILE NAME:         sky130_fd_sc_lp__nor2_lp.lvs.report
LAYOUT NAME:              svdb/sky130_fd_sc_lp__nor2_lp.sp ('sky130_fd_sc_lp__nor2_lp')
SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/nor2/sky130_fd_sc_lp__nor2_lp.spice ('sky130_fd_sc_lp__nor2_lp')
RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
CREATION TIME:            Wed Sep  2 10:07:54 2020
CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
USER NAME:                hlusk
CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018


                               OVERALL COMPARISON RESULTS


                  #   #         #####################  
                   # #          #                   #  
                    #           #     INCORRECT     #  
                   # #          #                   #  
                  #   #         #####################  


  Error:    Different numbers of ports.
  Error:    Connectivity errors.


**************************************************************************************************************
                                      CELL  SUMMARY
**************************************************************************************************************

  Result         Layout                        Source
  -----------    -----------                   --------------
  INCORRECT      sky130_fd_sc_lp__nor2_lp      sky130_fd_sc_lp__nor2_lp


**************************************************************************************************************
                                      LVS PARAMETERS
**************************************************************************************************************


o LVS Setup:

   // LVS COMPONENT TYPE PROPERTY
   // LVS COMPONENT SUBTYPE PROPERTY
   // LVS PIN NAME PROPERTY
   // LVS POWER NAME
   // LVS GROUND NAME
   LVS CELL SUPPLY                        NO
   LVS RECOGNIZE GATES                    ALL
   LVS IGNORE PORTS                       NO
   LVS CHECK PORT NAMES                   YES
   LVS IGNORE TRIVIAL NAMED PORTS         NO
   LVS BUILTIN DEVICE PIN SWAP            YES
   LVS ALL CAPACITOR PINS SWAPPABLE       NO
   LVS DISCARD PINS BY DEVICE             YES
   LVS SOFT SUBSTRATE PINS                NO
   LVS INJECT LOGIC                       NO
   LVS EXPAND UNBALANCED CELLS            YES
   LVS FLATTEN INSIDE CELL                NO
   LVS EXPAND SEED PROMOTIONS             NO
   LVS PRESERVE PARAMETERIZED CELLS       NO
   LVS GLOBALS ARE PORTS                  YES
   LVS REVERSE WL                         NO
   LVS SPICE PREFER PINS                  YES
   LVS SPICE SLASH IS SPACE               NO
   LVS SPICE ALLOW FLOATING PINS          YES
   LVS SPICE ALLOW INLINE PARAMETERS      NO
   LVS SPICE ALLOW UNQUOTED STRINGS       YES
   LVS SPICE CONDITIONAL LDD              NO
   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
   // LVS SPICE EXCLUDE CELL SOURCE
   // LVS SPICE EXCLUDE CELL LAYOUT
   LVS SPICE IMPLIED MOS AREA             NO
   // LVS SPICE MULTIPLIER NAME
   LVS SPICE OVERRIDE GLOBALS             YES
   LVS SPICE REDEFINE PARAM               YES
   LVS SPICE REPLICATE DEVICES            YES
   LVS SPICE SCALE X PARAMETERS           NO
   LVS SPICE STRICT WL                    YES
   // LVS SPICE OPTION
   LVS STRICT SUBTYPES                    YES
   LVS EXACT SUBTYPES                     NO
   LAYOUT CASE                            NO
   SOURCE CASE                            NO
   LVS COMPARE CASE                       NO
   LVS DOWNCASE DEVICE                    NO
   LVS REPORT MAXIMUM                     50
   LVS PROPERTY RESOLUTION MAXIMUM        ALL
   LVS SIGNATURE MAXIMUM                  ALL
   // LVS FILTER UNUSED OPTION
   // LVS REPORT OPTION
   LVS REPORT UNITS                       YES
   // LVS NON USER NAME PORT
   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
   // LVS NON USER NAME INSTANCE
   // LVS IGNORE DEVICE PIN
   // LVS PREFER NETS FILTER SOURCE
   // LVS PREFER NETS FILTER LAYOUT

   // Device Type Map

   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT

   // Reduction

   LVS REDUCE SERIES MOS                  NO
   LVS REDUCE PARALLEL MOS                NO
   LVS REDUCE SEMI SERIES MOS             NO
   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
   LVS REDUCE PARALLEL BIPOLAR            NO
   LVS REDUCE SERIES CAPACITORS           NO
   LVS REDUCE PARALLEL CAPACITORS         NO
   LVS REDUCE SERIES RESISTORS            NO
   LVS REDUCE PARALLEL RESISTORS          NO
   LVS REDUCE PARALLEL DIODES             NO

   LVS REDUCE  condiode  PARALLEL
   LVS REDUCE  condiodeHvPsub  PARALLEL
   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
   LVS REDUCE  Q(npnpar1x1)  PARALLEL
   LVS REDUCE  Q(npnpar1x2)  PARALLEL
   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
   LVS REDUCE  D  SERIES POS NEG NO
   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
   LVS REDUCE  R  SERIES POS NEG NO
   LVS REDUCE  R(short)  PARALLEL
   LVS REDUCE  R(short)  SERIES POS NEG NO
   LVS REDUCE  R(fuse)  PARALLEL NO
   LVS REDUCE  R(fuse)  SERIES POS NEG NO
   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
   LVS REDUCE  R(metop)  SERIES POS NEG NO
   LVS REDUCTION PRIORITY                 PARALLEL
   
   LVS SHORT EQUIVALENT NODES             NO

   // Filter

   LVS FILTER  R(cds_thru)  SHORT SOURCE
   LVS FILTER  R(cds_thru)  SHORT LAYOUT
   LVS FILTER  Dpar  OPEN SOURCE
   LVS FILTER  Dpar  OPEN LAYOUT
   LVS FILTER  Probe  OPEN SOURCE
   LVS FILTER  Probe  OPEN LAYOUT
   LVS FILTER  icecap  OPEN SOURCE
   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
   LVS FILTER  s8fmlt_termx  OPEN SOURCE
   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
   LVS FILTER  D  OPEN SOURCE
   LVS FILTER  diff_dev  OPEN SOURCE
   LVS FILTER  diff_dev  OPEN LAYOUT
   LVS FILTER  tap_dev  OPEN SOURCE
   LVS FILTER  tap_dev  OPEN LAYOUT
   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT

   // Trace Property

   TRACE PROPERTY  xcnwvc  m m 0
   TRACE PROPERTY  xcnwvc  w w 0
   TRACE PROPERTY  xcnwvc  l l 0
   TRACE PROPERTY  xcnwvc2  m m 0
   TRACE PROPERTY  xcnwvc2  w w 0
   TRACE PROPERTY  xcnwvc2  l l 0
   TRACE PROPERTY  xchvnwc  m m 0
   TRACE PROPERTY  q(npnpar1x1)  m m 0
   TRACE PROPERTY  q(npnpar1x2)  m m 0
   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
   TRACE PROPERTY  q(pnppar)  barea barea 0
   TRACE PROPERTY  q(pnppar)  bperi bperi 0
   TRACE PROPERTY  q(pnppar)  earea earea 0
   TRACE PROPERTY  q(pnppar)  eperi eperi 0
   TRACE PROPERTY  q(pnppar)  m m 0
   TRACE PROPERTY  q(pnppar5x)  barea barea 0
   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
   TRACE PROPERTY  q(pnppar5x)  earea earea 0
   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
   TRACE PROPERTY  q(pnppar5x)  m m 0
   TRACE PROPERTY  d(ndiode)  a a 1
   TRACE PROPERTY  d(ndiode)  p p 1
   TRACE PROPERTY  d(ndiode)  m m 0
   TRACE PROPERTY  d(ndiode_h)  a a 1
   TRACE PROPERTY  d(ndiode_h)  p p 1
   TRACE PROPERTY  d(ndiode_h)  m m 0
   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
   TRACE PROPERTY  d(pdiode)  a a 1
   TRACE PROPERTY  d(pdiode)  p p 1
   TRACE PROPERTY  d(pdiode)  m m 0
   TRACE PROPERTY  d(pdiode_h)  a a 1
   TRACE PROPERTY  d(pdiode_h)  p p 1
   TRACE PROPERTY  d(pdiode_h)  m m 0
   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
   TRACE PROPERTY  xcmvpp  m m 0
   TRACE PROPERTY  xcmvpp_2  m m 0
   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
   TRACE PROPERTY  xcmvpp5  m m 0
   TRACE PROPERTY  xcmvpp4  m m 0
   TRACE PROPERTY  xcmvpp3  m m 0
   TRACE PROPERTY  r(mrdn)  w w 1
   TRACE PROPERTY  r(mrdn)  l l 1
   TRACE PROPERTY  r(mrdn)  m m 0
   TRACE PROPERTY  r(mrdn_hv)  w w 1
   TRACE PROPERTY  r(mrdn_hv)  l l 1
   TRACE PROPERTY  r(mrdn_hv)  m m 0
   TRACE PROPERTY  r(mrdp)  w w 1
   TRACE PROPERTY  r(mrdp)  l l 1
   TRACE PROPERTY  r(mrdp)  m m 0
   TRACE PROPERTY  r(mrdp_hv)  w w 1
   TRACE PROPERTY  r(mrdp_hv)  l l 1
   TRACE PROPERTY  r(mrdp_hv)  m m 0
   TRACE PROPERTY  r(mrl1)  w w 1
   TRACE PROPERTY  r(mrl1)  l l 1
   TRACE PROPERTY  r(mrl1)  m m 0
   TRACE PROPERTY  r(xpwres)  w w 1
   TRACE PROPERTY  r(xpwres)  l l 1
   TRACE PROPERTY  r(xpwres)  m m 0
   TRACE PROPERTY  r(short)  m m 0
   TRACE PROPERTY  r(fuse)  w w 1
   TRACE PROPERTY  r(fuse)  l l 1
   TRACE PROPERTY  r(fuse)  m m 0
   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
   TRACE PROPERTY  d(nwdiode_victim)  a a 10
   TRACE PROPERTY  d(nwdiode_victim)  p p 10
   TRACE PROPERTY  d(nwdiode_victim)  m m 0
   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0

   // User Trace Property

   TRACE PROPERTY  mn(nshort)  m mult w l
   TRACE PROPERTY  mn(npass)  m mult w l
   TRACE PROPERTY  mn(nlowvt)  m mult w l
   TRACE PROPERTY  m(sonos_e)  m mult w l
   TRACE PROPERTY  m  m mult w l
   TRACE PROPERTY  m(fnpass)  m mult w l
   TRACE PROPERTY  mn(nhv)  m mult w l
   TRACE PROPERTY  mn(nhvnative)  m mult w l
   TRACE PROPERTY  mn(ntvnative)  m mult w l
   TRACE PROPERTY  mp(pshort)  m mult w l
   TRACE PROPERTY  mp  m mult w l
   TRACE PROPERTY  mp(phighvt)  m mult w l
   TRACE PROPERTY  mp(plowvt)  m mult w l
   TRACE PROPERTY  mp(phv)  m mult w l
   TRACE PROPERTY  mn(nshortesd)  m mult w l
   TRACE PROPERTY  mn(nhvesd)  m mult w l
   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
   TRACE PROPERTY  mp(phvesd)  m mult w l
   TRACE PROPERTY  nvhv  m mult w l
   TRACE PROPERTY  n20vhv1  m mult w l
   TRACE PROPERTY  n20nativevhv1  m mult w l
   TRACE PROPERTY  n20vhviso1  m mult w l
   TRACE PROPERTY  n20nativevhviso1  m mult w l
   TRACE PROPERTY  pvhv  m mult w l
   TRACE PROPERTY  p20vhv1  m mult w l
   TRACE PROPERTY  c(xcmimc1)  w l m
   TRACE PROPERTY  c(xcmimc2)  w l m
   TRACE PROPERTY  r(mrp1)  m w l
   TRACE PROPERTY  xhrpoly_0p35  m w l
   TRACE PROPERTY  xuhrpoly_0p35  m w l
   TRACE PROPERTY  xhrpoly_0p69  m w l
   TRACE PROPERTY  xuhrpoly_0p69  m w l
   TRACE PROPERTY  xhrpoly_1p41  m w l
   TRACE PROPERTY  xuhrpoly_1p41  m w l
   TRACE PROPERTY  xhrpoly_2p85  m w l
   TRACE PROPERTY  xuhrpoly_2p85  m w l


                   CELL COMPARISON RESULTS ( TOP LEVEL )


                  #   #         #####################  
                   # #          #                   #  
                    #           #     INCORRECT     #  
                   # #          #                   #  
                  #   #         #####################  


  Error:    Different numbers of ports (see below).
  Error:    Connectivity errors.

LAYOUT CELL NAME:         sky130_fd_sc_lp__nor2_lp
SOURCE CELL NAME:         sky130_fd_sc_lp__nor2_lp

--------------------------------------------------------------------------------------------------------------

INITIAL NUMBERS OF OBJECTS
--------------------------

                Layout    Source         Component Type
                ------    ------         --------------
 Ports:              7         5    *

 Nets:              10        10

 Instances:          4         4         MN (4 pins)
                     2         2         MP (4 pins)
                     1         0    *    Dpar (2 pins)
                ------    ------
 Total Inst:         7         6


NUMBERS OF OBJECTS AFTER TRANSFORMATION
---------------------------------------

                Layout    Source         Component Type
                ------    ------         --------------
 Ports:              7         5    *

 Nets:               7         7

 Instances:          2         2         SMN2 (4 pins)
                     1         1         SMP2 (4 pins)
                ------    ------
 Total Inst:         3         3


       * = Number of objects in layout different from number in source.


**************************************************************************************************************
                                 INCORRECT OBJECTS
**************************************************************************************************************


LEGEND:
-------

  ne  = Naming Error (same layout name found in source
        circuit, but object was matched otherwise).


**************************************************************************************************************
                                   INCORRECT NETS

DISC#  LAYOUT NAME                                               SOURCE NAME
**************************************************************************************************************

  1    Net VPB                                                   VPB
           VPWR                                                 
       --- 2 Connections On This Net ---                         --- 2 Connections On This Net ---

--------------------------------------------------------------------------------------------------------------

  2    Net VNB                                                   VNB
           VGND                                                 
       --- 3 Connections On This Net ---                         --- 3 Connections On This Net ---

--------------------------------------------------------------------------------------------------------------

  3    ** missing net **                                         w_0_0#

--------------------------------------------------------------------------------------------------------------

  4    ** missing net **                                         w_n38_331#


**************************************************************************************************************
                                 INCORRECT INSTANCES

DISC#  LAYOUT NAME                                               SOURCE NAME
**************************************************************************************************************

  5    M4(0.500,2.450)  MP(PHIGHVT)                              M1004  MP(PHIGHVT)
         g: A                                                      g: A
         b: VPB                                                    ** VPB **
         ** missing net **                                         b: w_n38_331#

--------------------------------------------------------------------------------------------------------------

  6    M5(0.890,2.450)  MP(PHIGHVT)                              M1005  MP(PHIGHVT)
         g: B                                                      g: B
         b: VPB                                                    ** VPB **
         ** missing net **                                         b: w_n38_331#

--------------------------------------------------------------------------------------------------------------

  7    M2(1.320,0.560)  MN(NSHORT)                               M1003  MN(NSHORT)
         g: B                                                      g: B
         b: VNB                                                    ** VNB **
         ** missing net **                                         b: w_0_0#

--------------------------------------------------------------------------------------------------------------

  8    M3(1.710,0.560)  MN(NSHORT)                               M1001  MN(NSHORT)
         g: B                                                      g: B
         b: VNB                                                    ** VNB **
         ** missing net **                                         b: w_0_0#

--------------------------------------------------------------------------------------------------------------

  9    M0(0.500,0.560)  MN(NSHORT)                               M1000  MN(NSHORT)
         g: A                                                      g: A
         b: VNB                                                    ** VNB **
         ** missing net **                                         b: w_0_0#

--------------------------------------------------------------------------------------------------------------

 10    M1(0.890,0.560)  MN(NSHORT)                               M1002  MN(NSHORT)
         g: A                                                      g: A
         b: VNB                                                    ** VNB **
         ** missing net **                                         b: w_0_0#


**************************************************************************************************************
                               INFORMATION AND WARNINGS
**************************************************************************************************************


                  Matched    Matched    Unmatched    Unmatched    Component
                   Layout     Source       Layout       Source    Type
                  -------    -------    ---------    ---------    ---------
   Ports:               7          5            0            0

   Nets:                7          5            0            2

   Instances:           2          2            0            0    SMN2
                        1          1            0            0    SMP2
                  -------    -------    ---------    ---------
   Total Inst:          3          3            0            0


o Statistics:

   1 layout instance was filtered and its pins removed from adjoining nets.


o Layout Names That Are Missing In The Source:

   Ports:        VPWR VGND
   Nets:         VPWR VGND


o Initial Correspondence Points:

   Ports:        VNB VPB A B Y


**************************************************************************************************************
                                         SUMMARY
**************************************************************************************************************

Total CPU Time:      0 sec
Total Elapsed Time:  0 sec