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| "cell_footprint": "sky130_fd_sc_lp__sdlclkp", | |
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| "clock_gating_integrated_cell": "latch_posedge_precontrol", | |
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| "related_bias_pin": "VPB", | |
| "voltage_name": "VGND" | |
| }, | |
| "pg_pin,VNB": { | |
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| "physical_connection": "device_layer", | |
| "voltage_name": "VNB" | |
| }, | |
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| "voltage_name": "VPWR" | |
| }, | |
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| "clock_gate_clock_pin": "true", | |
| "direction": "input", | |
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| }, | |
| "pin,GCLK": { | |
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| }, | |
| "timing_sense": "positive_unate" | |
| } | |
| }, | |
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| "internal_node": "M0", | |
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| "related_power_pin": "VPWR" | |
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| "clock": "false", | |
| "clock_gate_test_pin": "true", | |
| "direction": "input", | |
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| }, | |
| "max_transition": 1.0, | |
| "related_ground_pin": "VGND", | |
| "related_power_pin": "VPWR", | |
| "timing": [ | |
| { | |
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